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[RFA] PowerPC E500mc64 support

Freescale would like to contribute this patch to binutils.

It enables gcc for the new Freescale 64 bit core.

The patch was tested for powerpc64 with no regressions.
We thanks in advance for your time to review and commit the patch.

Regards,
Edmar

bfd/ChangeLog
2009-12-09  Edmar Wienskoski  <edmar@freescale.com>

	* archures.c: Add bfd_mach_ppc_e500mc64.
	* bfd-in2.h: Regenerate.
	* cpu-powerpc.c (bfd_powerpc_archs): Add entry for
	bfd_mach_ppc_e500mc64.

gas/ChangeLog
2009-12-09  Edmar Wienskoski  <edmar@freescale.com>

	* config/tc-ppc.c (md_show_usage): Document -me500mc64.

opcodes/ChangeLog
2009-12-09  Edmar Wienskoski  <edmar@freescale.com>

	* ppc-dis.c (ppc_opts): Add entry for "e500mc64".

diff -ru binutils-2.20-20091209/bfd/archures.c binutils-2.20-e500mc64-20091209/bfd/archures.c
--- binutils-2.20-20091209/bfd/archures.c	2009-12-09 11:20:59.000000000 -0600
+++ binutils-2.20-e500mc64-20091209/bfd/archures.c	2009-12-09 12:17:54.000000000 -0600
@@ -230,6 +230,7 @@
 .#define bfd_mach_ppc_7400	7400
 .#define bfd_mach_ppc_e500      500
 .#define bfd_mach_ppc_e500mc    5001
+.#define bfd_mach_ppc_e500mc64    5005
 .  bfd_arch_rs6000,    {* IBM RS/6000 *}
 .#define bfd_mach_rs6k		6000
 .#define bfd_mach_rs6k_rs1	6001
diff -ru binutils-2.20-20091209/bfd/bfd-in2.h binutils-2.20-e500mc64-20091209/bfd/bfd-in2.h
--- binutils-2.20-20091209/bfd/bfd-in2.h	2009-12-09 11:20:59.000000000 -0600
+++ binutils-2.20-e500mc64-20091209/bfd/bfd-in2.h	2009-12-09 12:17:54.000000000 -0600
@@ -1901,6 +1901,7 @@
 #define bfd_mach_ppc_7400      7400
 #define bfd_mach_ppc_e500      500
 #define bfd_mach_ppc_e500mc    5001
+#define bfd_mach_ppc_e500mc64    5005
   bfd_arch_rs6000,    /* IBM RS/6000 */
 #define bfd_mach_rs6k          6000
 #define bfd_mach_rs6k_rs1      6001
diff -ru binutils-2.20-20091209/bfd/cpu-powerpc.c binutils-2.20-e500mc64-20091209/bfd/cpu-powerpc.c
--- binutils-2.20-20091209/bfd/cpu-powerpc.c	2009-12-09 11:21:02.000000000 -0600
+++ binutils-2.20-e500mc64-20091209/bfd/cpu-powerpc.c	2009-12-09 12:22:51.000000000 -0600
@@ -299,6 +299,20 @@
     &bfd_powerpc_archs[15]
   },
   {
+    64, /* 64 bits in a word */
+    64, /* 64 bits in an address */
+    8,  /* 8 bits in a byte */
+    bfd_arch_powerpc,
+    bfd_mach_ppc_e500mc64,
+    "powerpc",
+    "powerpc:e500mc64",
+    3,
+    FALSE, /* not the default */
+    powerpc_compatible,
+    bfd_default_scan,
+    &bfd_powerpc_archs[16]
+  },
+  {
     32,       /* 32 bits in a word */
     32,       /* 32 bits in an address */
     8,        /* 8 bits in a byte */
@@ -310,7 +324,7 @@
     FALSE, /* not the default */
     powerpc_compatible,
     bfd_default_scan,
-    &bfd_powerpc_archs[16]
+    &bfd_powerpc_archs[17]
   },
   {
     32, /* 32 bits in a word */
diff -ru binutils-2.20-20091209/gas/config/tc-ppc.c binutils-2.20-e500mc64-20091209/gas/config/tc-ppc.c
--- binutils-2.20-20091209/gas/config/tc-ppc.c	2009-12-09 11:21:36.000000000 -0600
+++ binutils-2.20-e500mc64-20091209/gas/config/tc-ppc.c	2009-12-09 15:01:40.000000000 -0600
@@ -1209,7 +1209,8 @@
 -mvsx			generate code for Vector-Scalar (VSX) instructions\n\
 -me300			generate code for PowerPC e300 family\n\
 -me500, -me500x2	generate code for Motorola e500 core complex\n\
--me500mc,               generate code for Freescale e500mc core complex\n\
+-me500mc,		generate code for Freescale e500mc core complex\n\
+-me500mc64,		generate code for Freescale e500mc64 core complex\n\
 -mspe			generate code for Motorola SPE instructions\n\
 -mregnames		Allow symbolic names for registers\n\
 -mno-regnames		Do not allow symbolic names for registers\n"));
diff -ru binutils-2.20-20091209/opcodes/ppc-dis.c binutils-2.20-e500mc64-20091209/opcodes/ppc-dis.c
--- binutils-2.20-20091209/opcodes/ppc-dis.c	2009-12-09 11:22:28.000000000 -0600
+++ binutils-2.20-e500mc64-20091209/opcodes/ppc-dis.c	2009-12-09 12:17:54.000000000 -0600
@@ -114,6 +114,11 @@
 		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
 		| PPC_OPCODE_E500MC),
     0 },
+  { "e500mc64",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
+		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
+		| PPC_OPCODE_64 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+		| PPC_OPCODE_POWER7),
+    0 },
   { "e500x2",  (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
 		| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
 		| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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