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[patch] mep: avoid short bsr's
- From: DJ Delorie <dj at redhat dot com>
- To: binutils at sourceware dot org
- Date: Tue, 23 Jun 2009 21:45:03 -0400
- Subject: [patch] mep: avoid short bsr's
Another way we make sure branches can reach in VLIW mode. Avoid the
short BSR form in VLIW mode.
[cgen]
* cpu/mep.opc (mep_cgen_insn_supported_asm): New, skip the short
version of BSR when assembling VLIW bundles. Use it in mep-asm.c
[opcodes]
* mep-asm.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
Index: cgen/cpu/mep.opc
===================================================================
RCS file: /cvs/src/src/cgen/cpu/mep.opc,v
retrieving revision 1.7
diff -p -U3 -r1.7 mep.opc
--- cgen/cpu/mep.opc 28 May 2009 22:53:08 -0000 1.7
+++ cgen/cpu/mep.opc 24 Jun 2009 01:26:46 -0000
@@ -75,12 +75,14 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_a
)
extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- asm.c */
#include "elf/mep.h"
#define CGEN_VALIDATE_INSN_SUPPORTED
+#define mep_cgen_insn_supported mep_cgen_insn_supported_asm
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
@@ -1641,3 +1643,15 @@ mep_cgen_insn_supported (CGEN_CPU_DESC c
return (ok1 && ok2 && ok3);
}
+
+int
+mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ /* If we're assembling VLIW packets, ignore the 12-bit BSR as we
+ can't relax that. The 24-bit BSR is matched instead. */
+ if (insn->base->num == MEP_INSN_BSR12
+ && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64))
+ return 0;
+
+ return mep_cgen_insn_supported (cd, insn);
+}
Index: opcodes/mep-asm.c
===================================================================
RCS file: /cvs/src/src/opcodes/mep-asm.c,v
retrieving revision 1.10
diff -p -U3 -r1.10 mep-asm.c
--- opcodes/mep-asm.c 28 May 2009 22:53:08 -0000 1.10
+++ opcodes/mep-asm.c 24 Jun 2009 01:26:46 -0000
@@ -54,6 +54,7 @@ static const char * parse_insn_normal
#include "elf/mep.h"
#define CGEN_VALIDATE_INSN_SUPPORTED
+#define mep_cgen_insn_supported mep_cgen_insn_supported_asm
const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
Index: opcodes/mep-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mep-opc.c,v
retrieving revision 1.10
diff -p -U3 -r1.10 mep-opc.c
--- opcodes/mep-opc.c 27 May 2009 01:49:45 -0000 1.10
+++ opcodes/mep-opc.c 24 Jun 2009 01:26:47 -0000
@@ -163,6 +163,18 @@ mep_cgen_insn_supported (CGEN_CPU_DESC c
return (ok1 && ok2 && ok3);
}
+
+int
+mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
+{
+ /* If we're assembling VLIW packets, ignore the 12-bit BSR as we
+ can't relax that. The 24-bit BSR is matched instead. */
+ if (insn->base->num == MEP_INSN_BSR12
+ && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64))
+ return 0;
+
+ return mep_cgen_insn_supported (cd, insn);
+}
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
Index: opcodes/mep-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/mep-opc.h,v
retrieving revision 1.8
diff -p -U3 -r1.8 mep-opc.h
--- opcodes/mep-opc.h 27 May 2009 01:49:46 -0000 1.8
+++ opcodes/mep-opc.h 24 Jun 2009 01:26:47 -0000
@@ -96,6 +96,7 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_a
)
extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
+extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *);
/* -- asm.c */
/* Enum declaration for mep instruction types. */