Re: regarding assembling branch instruction

[Nick Clifton <nickc at redhat dot com>]

Hi Siva,

> Initially our custom processor support only one unconditional branch 
> instruction 'bra' of 20 bit range (32 bit instruction).
> Now we are planned to add 16 bit unconditional branch instruction 'bra' 
> of 8 bit range.
> both shares same instruction name 'bra'.But it leading a problem for us.
> For example:
>
> bra Label
> nop
> nop
> ...
> Label: nop
>
> In first pass 'Label'  address is treated as 0 so it is selecting 16 bit 
> instruction.
> In second pass it finds that the 'Label' is out of 8 bit range and fails 
> to generate appropriate 32bit instruction opcode.

Either a) delay selecting the opcode to use until the second pass or
b) always generate the larger (32bit) opcode in the assembler and then 
in the linker add code to select the shorter opcode if it can be used. 
(This process is known as "linker relaxation" and quite a few ports do 
it.  For an example have a look at bfd/elf-m10300.c).

Cheers
  Nick