This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] Lexra binutils


Sergey Lapin wrote:
> On Wed, Sep 17, 2008 at 08:47:47PM +0400, Sergey Lapin wrote:
> > > opcodes/mips-opc.c:
> > > #define I1U INSN_ISA1_UNALIGNED
> > > ...
> > > -{"lwl",     "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0,           I1}
> > > -{"lwl",     "t,A(b)",  0,    (int) M_LWL_AB,   INSN_MACRO, 0,              I1}
> > > +{"lwl",     "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0,           I1U}
> > > +{"lwl",     "t,A(b)",  0,    (int) M_LWL_AB,   INSN_MACRO, 0,              I1U}
> > > ...
> > 
> > I would keep the ISA1 / I1 meaning for MIPS I, as this is a well known
> > standard for many people.
> Sorry, I can't get, what you would suggest there?
> If keeping I1, then we can't use bits additively.
> Or you suggest create something like ILX and mark with it
> all instructions which are supported?

The latter, I called I1- ("MIPS I minus") what you call ILX.
That way, the progression of ISA supersets is I1- -> I1 -> I2 ...

> > > And all the stuff with adding CPU in both tc-mips.c and BFD.
> > > Will it be sufficient?
> > 
> > It also needs a E_MIPS_MACH value. Do the old Lexra toolchains set
> > this flag?
> No, just R3000.

Then we should add a new value for Lexra (so the linker can complain
if it is asked to link non-Lexra objects into a Lexra binary).


Thiemo


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]