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Re: PING : [PATCH] Add support for Xilinx FP/APU to PowerPC
- From: Michael Eager <eager at eagercon dot com>
- To: Michael Eager <eager at eagercon dot com>, binutils at sourceware dot org
- Date: Tue, 29 Jul 2008 11:18:38 -0700
- Subject: Re: PING : [PATCH] Add support for Xilinx FP/APU to PowerPC
- References: <480CDDE3.3080103@eagercon.com> <48372E5F.4050505@eagercon.com> <20080527055620.GE10726@bubble.grove.modra.org> <4845B14A.6020907@eagercon.com> <4859211A.9010809@eagercon.com> <20080726150434.GB13087@bubble.grove.modra.org>
Alan Modra wrote:
On Wed, Jun 18, 2008 at 07:52:10AM -0700, Michael Eager wrote:
I revised the patch and changed the APU macro so that rc is factored
out, like the A() macro. This makes it easier to put the opcodes in
order. I did notice that there was a re-use of an opcode in one of
the added instructions. I removed this instruction (and the similar
ones) and will submit those as a patch when I resolve the conflict.
It still isn't sorted, and I don't believe you should have PPC32 in
the op flags as this will enable the instructions for any cpu that
sets PPC_OPCODE_PPC. The following patch does this, but I notice that
the udi instructions are odd in that the "dot" form has rc=0 and
the non-dot form has rc=1. Are you sure this is correct?
Sorry about the sorting.
Yes, the PPC32 flag should be removed. This was inherited from
some long-ago patch and I just copied it over unchanged.
The use of the rc field (opposite from most other "dot" instructions)
matches the documentation. I checked with the hardware folks and they
confirmed that this is correct and was intentional.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077