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Re: [PATCH, MIPS] Add support for CPUs with no FPU
- From: Thiemo Seufer <ths at networkno dot de>
- To: Adam Nemet <anemet at caviumnetworks dot com>
- Cc: binutils at sourceware dot org
- Date: Sat, 16 Feb 2008 13:24:20 +0000
- Subject: Re: [PATCH, MIPS] Add support for CPUs with no FPU
- References: <18358.7414.677959.951389@localhost.localdomain>
Adam Nemet wrote:
> This patch adds support for soft-float targets and generalizes single-float
> support.
>
> CPU targets can now be marked as single-float or soft-float. These are used
> by default and can be overridden with command-line options or asm directives.
> So that we don't have to remember another set of options I used the GCC names:
> -msoft-float/-mhard-float -msingle-float/-mdouble-float.
>
> Instructions in the optable are marked with FP_S or FP_D if they require
> single-precision or a double-precision FPU. (Two instructions prefx and cop1
> were missing this marking.) I use these flags to decide whether the
> instruction should be enabled for single-float or soft-float.
>
> The code to check the flags is in a new function encapsulating
> OPCODE_IS_MEMBER in tc-mips.c. One consequence of not doing this inside
> OPCODE_IS_MEMBER in mips.h which is shared with the disassembler is that even
> for a soft-float target we will disassemble fp instructions. This matches how
> r4650 used to work WRT dfp instruction. If I did it other way then we would
> need matching command-line options in the disassembler to revert the CPU
> defaults. I am not sure it would be worth the complication.
Note that the lack of such options for ASEs is a bug, not a feature.
IMHO implementing an appropriate -M flag for FP would be worthwile as
a diagnostics aid, regardless of the default value. (I don't regard it
as a requirement for this patch.)
I have for some years now the idea to improve the disassembler behaviour,
but never got around to do it: Implement a "generic" architecture for the
disassembler which switches on disassembly of all non-conflicting
instructions it knows about. This would then become the default setting,
and prompt a large amount of testsuite adjustments ...
> I added support for marking macros as requiring single-float or double-float
> support. The bits to track this are in the pinfo2 field. Another option
> would be to use the match field which as far as I know should always be zero
> for macros. (Confusingly enough, the drem macros have 3 as their match field.
> Is that a typo?)
Looks like a typo to me.
[snip]
> -#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
> -#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
> -#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
> -#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
> -#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
> -#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
> -#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
> +#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
> +#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
> +#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
> +#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
> +#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
> +#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
> +#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
> +#define MIPS_CPU_FLOAT_OPS_NONE 0x0080 /* CPU has no FPU */
> +#define MIPS_CPU_FLOAT_OPS_SINGLE 0x0100 /* CPU has no 64-bit FPU */
This comment (and some more further down) are misleading, you meant
a FPU with doubles being implemented, not one with 64-bit wide
registers (as selected by -mfp64).
[snip]
> +static bfd_boolean
> +is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
> +{
> + int isa = mips_opts.isa;
> + int fp_s, fp_d;
> +
> + if (mips_opts.ase_mdmx)
> + isa |= INSN_MDMX;
> + if (mips_opts.ase_dsp)
> + isa |= INSN_DSP;
> + if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
> + isa |= INSN_DSP64;
> + if (mips_opts.ase_dspr2)
> + isa |= INSN_DSPR2;
> + if (mips_opts.ase_mt)
> + isa|= INSN_MT;
Formatting.
Thiemo