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RE: [PATCH] Add x86 SSE5 instructions to the GNU binary utilities


Yes SSE5 uses the same opcode (0f 24) for move test registers. The only
way to disambiguate is that the 3rd opcode does not have upper 2 bits
set. 

It is better to do this test in print_insn() than in get_valid_dis386()
because the only way to disambiguate this case is by using the 3rd
opcode and not modrm bits. 
That is why I removed OPC_EXT_45.

Also, thanks for the comments on the assembler. I'll make the
appropriate changes to the patch.

Thanks,
- Dwarak


> -----Original Message-----
> From: H.J. Lu [mailto:hjl@lucon.org]
> Sent: Thursday, September 13, 2007 3:38 PM
> To: rajagopal, dwarak
> Cc: binutils@sourceware.org; Meissner, Michael; Harle, Christophe
> Subject: Re: [PATCH] Add x86 SSE5 instructions to the GNU binary
utilities
> 
> On Thu, Sep 13, 2007 at 03:08:54PM -0500, rajagopal, dwarak wrote:
> > The enclosed patch adds support for the SSE5 instructions to the
> > assembler and disassembler.
> >
> > I have made changes to the original patch so that it uses bitfields
(the
> > new infrastructure changes which H.J had checked in last week) for
> > cpu_flag, opcode_modifier and operand_types for the new
instructions.
> >
> 
> Did SSE5 reuse the same opcode for move test registers? If not,
> please don't remove OPC_EXT_45. You can use
> 
> {
>   /* OPC_EXT_45 */
>   { THREE_BYTE_SSE5_0F7A }
>   { "movL",          { Td, Rd } },
> }
> 
> 
> H.J.
> 




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