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On August 30th, AMD announced the new SSE5 instruction set that will be part of future processors. The programmer's guide for these new instructions is located at: http://developer.amd.com/assets/sse5_43479_BDAPMU_3-00_8-27-07.pdf The enclosed patch adds support for the SSE5 instructions to the assembler and disassembler. I had to gzip the patch file to get it small enough to be able to post (i386-tbl.h and the new test are too big). Is it ok to apply this patch? If not, what changes would people prefer? It turned out the old move from test register instructions that were in the I386 and I486 processors but is not in modern processors overlaps with the SSE5 encoding (0x0f24). These can be disambiguated because the move from test register instruction always uses MODRM encoding with the upper 2 bits set (for register/register encoding), and none of the SSE5 instructions set the upper 2 bits. I needed 3 extra opcode_modifier bits to implement SSE5, and only two bits are available without going to long long. I modified the structures to add an opcode_modifier2 field, and I changed the i386-gen.c program so that existing lines in the i386-opc.tbl file will be handled without modifying them. I can modify all of the instruction lines to add the 0 field if people would prefer. Note, I had originally posted this to the bug-bintutils@gnu.org, instead of binutils@sourceware.org. Sorry about the duplicate post. -- Michael Meissner, AMD 90 Central Street, MS 83-29, Boxborough, MA, 01719, USA michael.meissner@amd.com
Attachment:
sse5-binutils.patch.gz
Description: GNU Zip compressed data
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