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[PATCH] MIPS gas: Update 24k/24ke CPU name aliases
- From: Thiemo Seufer <ths at networkno dot de>
- To: binutils at sourceware dot org
- Date: Mon, 6 Nov 2006 14:44:09 +0000
- Subject: [PATCH] MIPS gas: Update 24k/24ke CPU name aliases
Hello All,
I applied the appended patch, it syncs the 24k/24ke CPU names with
recent gcc changes, and add a missing DSP default flag to the 34k
configurations.
Thiemo
2006-11-06 Thiemo Seufer <ths@mips.com>
* config/tc-mips.c (mips_cpu_info_table): Remove 24k/24ke aliases.
34k always has DSP ASE.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.358
diff -u -p -r1.358 tc-mips.c
--- gas/config/tc-mips.c 3 Nov 2006 16:32:04 -0000 1.358
+++ gas/config/tc-mips.c 6 Nov 2006 14:26:19 -0000
@@ -14580,19 +14580,20 @@ static const struct mips_cpu_info mips_c
{ "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
/* 24ke is a 24k with DSP ASE, other ASEs are optional. */
- { "24ke", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
- /* 34k is a 24k with MT ASE, other ASEs are optional. */
- { "34kc", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kf", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kx", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* 34k is a 24k with DSP and MT ASE, other ASEs are optional. */
+ { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
/* MIPS 64 */
{ "5kc", 0, ISA_MIPS64, CPU_MIPS64 },