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[PATCH] Not throw away (M) mode for vector multipy instruction in bfin gas

Previously, if the MAC1 operation comes as the second operand in a
vector Multiply 16-Bit Operands instruction and has (M) mode flag, the
(M) mode flag was thown away by gas. This patch fixes it. I also add
more check conditions for both vector
and scalar Multiply 16-Bit Operands instructions in this patch. It
will result better diagnositic information for users. It also adds
some bits in bfin gas regression testsuite for this bug. Committed.

Jie 
gas/

	* config/bfin-parse.y (asm_1): Better check and deal with
	vector and scalar Multiply 16-Bit Operands instructions.

gas/testsuite

	* gas/bfin/vector2.s, gas/bfin/vector2.d: Test to ensure (m) is not
	thrown away.

Index: config/bfin-parse.y
===================================================================
RCS file: /cvs/src/src/gas/config/bfin-parse.y,v
retrieving revision 1.6
diff -u -r1.6 bfin-parse.y
--- config/bfin-parse.y	23 May 2006 04:23:41 -0000	1.6
+++ config/bfin-parse.y	25 May 2006 03:59:50 -0000
@@ -1730,7 +1730,7 @@
 	      $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
 			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
 			      &$1, 0, &$3.s0, &$3.s1, 1);
-		}	
+	    }
 	}
 
 	| REG ASSIGN multiply_halfregs opt_mode 
@@ -1739,6 +1739,9 @@
 	  if (!IS_DREG ($1))
 	    return yyerror ("Dreg expected");
 
+	  if (IS_EVEN ($1) && $4.MM)
+	    return yyerror ("(M) not allowed with MAC0");
+
 	  if (!IS_EVEN ($1))
 	    {
 	      notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
@@ -1747,15 +1750,13 @@
 			      IS_H ($3.s0), IS_H ($3.s1), 0, 0,
 			      &$1, 0, &$3.s0, &$3.s1, 0);
 	    }
-	  else if ($4.MM == 0)
+	  else
 	    {
 	      notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
 	      $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
 			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
 			      &$1,  0, &$3.s0, &$3.s1, 1);
 	    }
-	  else
-	    return yyerror ("Register or mode mismatch");
 	}
 
 	| HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
@@ -1764,57 +1765,56 @@
 	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
 	    return yyerror ("Dregs expected");
 
+	  if (!IS_HCOMPL($1, $6))
+	    return yyerror ("Dest registers mismatch");
+
 	  if (check_multiply_halfregs (&$3, &$8) < 0)
 	    return -1;
 
-	  if (IS_H ($1) && !IS_H ($6))
-	    {
-	      notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
-		       "dregs_lo = multiply_halfregs opt_mode\n");
-	      $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
-			      IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	    }
-	  else if (!IS_H ($1) && IS_H ($6) && $4.MM == 0)
-	    {
-	      $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
-			      IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	    }
+	  if ((!IS_H ($1) && $4.MM)
+	      || (!IS_H ($6) && $9.MM))
+	    return yyerror ("(M) not allowed with MAC0");
+
+	  notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
+		    "dregs_lo = multiply_halfregs opt_mode\n");
+
+	  if (IS_H ($1))
+	    $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
+			    IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
 	  else
-	    return yyerror ("Multfunc Register or mode mismatch");
+	    $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
+			    IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
 	}
 
-	| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode 
+	| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
 	{
 	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
 	    return yyerror ("Dregs expected");
 
+	  if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
+	      || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
+	    return yyerror ("Dest registers mismatch");
+
 	  if (check_multiply_halfregs (&$3, &$8) < 0)
 	    return -1;
 
+	  if ((IS_EVEN ($1) && $4.MM)
+	      || (IS_EVEN ($6) && $9.MM))
+	    return yyerror ("(M) not allowed with MAC0");
+
 	  notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
 		   "dregs = multiply_halfregs opt_mode\n");
-	  if (IS_EVEN ($1))
-	    {
-	      if ($6.regno - $1.regno != 1 || $4.MM != 0)
-		return yyerror ("Dest registers or mode mismatch");
 
-	      /*   op1       MM      mmod  */
-	      $$ = DSP32MULT (0, 0, $9.mod, 1, 1,
-			      IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	      
-	    }
-	  else
-	    {
-	      if ($1.regno - $6.regno != 1)
-		return yyerror ("Dest registers mismatch");
-	      
-	      $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
-			      IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	    }
+	  if (IS_EVEN ($1))
+	    $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
+			    IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
+	  else
+	    $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
+			    IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
 	}
 
 
Index: testsuite/gas/bfin/vector2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/bfin/vector2.d,v
retrieving revision 1.1
diff -u -r1.1 vector2.d
--- testsuite/gas/bfin/vector2.d	30 Sep 2005 15:10:16 -0000	1.1
+++ testsuite/gas/bfin/vector2.d	25 May 2006 03:59:51 -0000
@@ -469,3 +469,6 @@
  734:	00 9e 32 9c 
  738:	8b c8 9a 2f 	R6 = \(a0 \+= R3.H \* R2.H\) \(FU\) \|\| I2-=M0 \|\| NOP;
  73c:	72 9e 00 00 
+ 740:	14 c2 1a a0 	R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L;
+ 744:	1c c2 b8 60 	R3 = R7.L \* R0.H \(M\), R2 = R7.L \* R0.L;
+ 748:	1c c0 b8 60 	R3 = \(a1 = R7.L \* R0.H\) \(M\), R2 = \(a0 = R7.L \* R0.L\);
\ No newline at end of file
Index: testsuite/gas/bfin/vector2.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/bfin/vector2.s,v
retrieving revision 1.1
diff -u -r1.1 vector2.s
--- testsuite/gas/bfin/vector2.s	30 Sep 2005 15:10:16 -0000	1.1
+++ testsuite/gas/bfin/vector2.s	25 May 2006 03:59:51 -0000
@@ -666,3 +666,8 @@
 r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ;
 /* which the assembler expands into:
 r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */
+
+/* Test for ensure (m) is not thown away.  */
+r0.l=r3.l*r2.l, r0.h=r3.h*r2.l (m) ;
+R2 = R7.L * R0.L, R3 = R7.L * R0.H (m);
+R2 = (A0 = R7.L * R0.L), R3 = ( A1 = R7.L * R0.H) (m);
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