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PATCH: Fix disassembling x86-64 control register
- From: "H. J. Lu" <hjl at lucon dot org>
- To: binutils at sources dot redhat dot com
- Date: Sat, 11 Feb 2006 08:54:30 -0800
- Subject: PATCH: Fix disassembling x86-64 control register
Control registers in 64bit mode are always 64bit. We disassemble
control register move as "movl" today. I am checking this patch to
turn it to "movq".
We have the same problem with debug register. But the assembler
rejects "%dr14", which is reserved, like "%cr14.". I will fix it
in a separate patch.
H.J.
----
gas/testsuite/
2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix".
* gas/i386/x86-64-crx-suffix.d: New file.
* i386/x86-64-crx.d: Likewise.
* x86-64-crx.s: Likewise.
opcodes/
2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c ('Z'): Add a new macro.
(dis386_twobyte): Use "movZ" for control register moves.
--- binutils/gas/testsuite/gas/i386/i386.exp.64 2005-12-14 09:20:29.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/i386.exp 2006-02-11 08:40:25.000000000 -0800
@@ -132,6 +132,8 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-vmx"
run_dump_test "immed64"
run_dump_test "x86-64-prescott"
+ run_dump_test "x86-64-crx"
+ run_dump_test "x86-64-crx-suffix"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
--- binutils/gas/testsuite/gas/i386/x86-64-crx-suffix.d.64 2006-02-11 07:10:30.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/x86-64-crx-suffix.d 2006-02-11 07:50:46.000000000 -0800
@@ -0,0 +1,21 @@
+#objdump: -dwMsuffix
+#name: x86-64 control register related opcodes (with suffixes)
+#source: x86-64-crx.s
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq[ ]+?%cr8,%rax
+[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq[ ]+?%cr8,%rdi
+[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq[ ]+?%rax,%cr8
+[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq[ ]+?%rdi,%cr8
+[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq[ ]+?%cr8,%rax
+[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq[ ]+?%cr8,%rdi
+[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq[ ]+?%rax,%cr8
+[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq[ ]+?%rdi,%cr8
+[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq[ ]+?%cr8,%rax
+[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq[ ]+?%cr8,%rdi
+[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq[ ]+?%rax,%cr8
+[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq[ ]+?%rdi,%cr8
--- binutils/gas/testsuite/gas/i386/x86-64-crx.d.64 2006-02-11 07:13:45.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/x86-64-crx.d 2006-02-11 07:50:35.000000000 -0800
@@ -0,0 +1,21 @@
+#objdump: -dw
+#name: x86-64 control register related opcodes
+#source: x86-64-crx.s
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq?[ ]+?%cr8,%rax
+[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq?[ ]+?%cr8,%rdi
+[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq?[ ]+?%rax,%cr8
+[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq?[ ]+?%rdi,%cr8
+[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq?[ ]+?%cr8,%rax
+[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq?[ ]+?%cr8,%rdi
+[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq?[ ]+?%rax,%cr8
+[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq?[ ]+?%rdi,%cr8
+[ ]*[0-9a-f]+: 44 0f 20 c0[ ]+movq?[ ]+?%cr8,%rax
+[ ]*[0-9a-f]+: 44 0f 20 c7[ ]+movq?[ ]+?%cr8,%rdi
+[ ]*[0-9a-f]+: 44 0f 22 c0[ ]+movq?[ ]+?%rax,%cr8
+[ ]*[0-9a-f]+: 44 0f 22 c7[ ]+movq?[ ]+?%rdi,%cr8
--- binutils/gas/testsuite/gas/i386/x86-64-crx.s.64 2006-02-11 07:13:35.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/x86-64-crx.s 2006-02-11 07:22:41.000000000 -0800
@@ -0,0 +1,18 @@
+.text
+_start:
+ movq %cr8, %rax
+ movq %cr8, %rdi
+ movq %rax, %cr8
+ movq %rdi, %cr8
+
+.att_syntax noprefix
+ movq cr8, rax
+ movq cr8, rdi
+ movq rax, cr8
+ movq rdi, cr8
+
+.intel_syntax noprefix
+ mov rax, cr8
+ mov rdi, cr8
+ mov cr8, rax
+ mov cr8, rdi
--- binutils/opcodes/i386-dis.c.64 2005-12-10 16:45:18.000000000 -0800
+++ binutils/opcodes/i386-dis.c 2006-02-11 08:42:27.000000000 -0800
@@ -491,6 +491,7 @@ struct dis386 {
'W' => print 'b' or 'w' ("w" or "de" in intel mode)
'X' => print 's', 'd' depending on data16 prefix (for XMM)
'Y' => 'q' if instruction has an REX 64bit overwrite prefix
+ 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
Many of the above letters print nothing in Intel mode. See "putop"
for the details.
@@ -830,9 +831,9 @@ static const struct dis386 dis386_twobyt
{ "(bad)", XX, XX, XX },
{ "(bad)", XX, XX, XX },
/* 20 */
- { "movL", Rm, Cm, XX },
+ { "movZ", Rm, Cm, XX },
{ "movL", Rm, Dm, XX },
- { "movL", Cm, Rm, XX },
+ { "movZ", Cm, Rm, XX },
{ "movL", Dm, Rm, XX },
{ "movL", Rd, Td, XX },
{ "(bad)", XX, XX, XX },
@@ -2856,6 +2857,15 @@ putop (const char *template, int sizefla
break;
*obufp++ = 'l';
break;
+ case 'Z':
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
case 'L':
if (intel_syntax)
break;