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RFA: arm maverick disassembly
- From: James Lemke <jim at wasabisystems dot com>
- To: binutils at sources dot redhat dot com
- Date: Fri, 07 Oct 2005 17:44:03 -0400
- Subject: RFA: arm maverick disassembly
I got a report of incorrect disassembly of mrc opcodes as cfmsub32.
E.G.
was ee102610 cfmsub32 mvax0, mvfx2, mvfx0, mvfx0
should be ee102610 mrc 6, 0, r2, cr0, cr0, {0}
I found that 6 of the Maverick CDP opcodes do not depend on bit 4 when
they should. Patch attached.
Tested on x86-linux x arm-elf.
No change in binutils results.
gcc results had no regressions and 15 improvements:
2x unsupported -> pass gcc.dg/cpp/trad/num-sign.c
13x untested -> pass gcc.dg/pch/valid-[123].c & warn-1.c
Not sure that this qualifies for the "obvious" rule.
OK to commit?
--
Jim Lemke jim@wasabisystems.com Orillia, Ontario
Index: ChangeLog
===================================================================
RCS file: /cvs/src/src/opcodes/ChangeLog,v
retrieving revision 1.768
diff -u -p -r1.768 ChangeLog
--- ChangeLog 7 Mar 2005 20:05:43 -0000 1.768
+++ ChangeLog 7 Oct 2005 14:28:45 -0000
@@ -1,3 +1,8 @@
+2005-10-07 James Lemke <jim@wasabisystems.com>
+
+ * arm-dis.c (asm_opcodes): 6 of the Cirrus Maverick CDP opcodes
+ were not checking bit 4.
+
2005-03-07 Aldy Hernandez <aldyh@redhat.com>
* ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
Index: arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.41
diff -u -p -r1.41 arm-dis.c
--- arm-dis.c 29 Nov 2004 10:12:57 -0000 1.41
+++ arm-dis.c 7 Oct 2005 14:28:46 -0000
@@ -571,8 +571,8 @@ static const struct arm_opcode arm_opcod
{ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
{ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
{ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
- {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
- {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
+ {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
+ {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
{ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
@@ -599,10 +599,10 @@ static const struct arm_opcode arm_opcod
{ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* Generic coprocessor instructions */
{ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},