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Thumb32 assembler (49/69)
- From: Zack Weinberg <zack at codesourcery dot com>
- To: binutils <binutils at sourceware dot org>
- Date: Tue, 26 Apr 2005 02:56:22 -0700
- Subject: Thumb32 assembler (49/69)
This patch begins a series of structural changes to the instruction
table itself. It introduces macros which expand a single table entry
for each instruction into all the necessary conditional variants.
This allows us to remove build_arm_ops_hsh. They also take the
processor-variant value from a secondary #define, which means it
doesn't have to appear in each and every entry.
arm_cond_hsh and the conds array are unused after this patch, but I
keep them around, because they'll be wanted later, to implement the IT
instruction.
zw
* config/tc-arm.c (conds): Move next to insns. Remove "nv".
(struct asm_opcode): Remove cond_offset field.
(struct thumb_opcode): Delete.
(md_assemble): Declare opcode variable just once. Thumb insn
size is 4 if opcode value is larger than 0xffff.
(CE, CM, UE, UF, TI): New notational macros.
(insns, tinsns): Reformat using notational macros.
(build_arm_ops_hsh): Delete.
(md_begin): Fill in arm_ops_hsh like other hashes.
===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c (revision 51)
+++ gas/config/tc-arm.c (revision 52)
@@ -247,26 +247,6 @@
#define COND_ALWAYS 0xe0000000
#define COND_MASK 0xf0000000
-static const struct asm_cond conds[] =
-{
- {"eq", 0x00000000},
- {"ne", 0x10000000},
- {"cs", 0x20000000}, {"hs", 0x20000000},
- {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
- {"mi", 0x40000000},
- {"pl", 0x50000000},
- {"vs", 0x60000000},
- {"vc", 0x70000000},
- {"hi", 0x80000000},
- {"ls", 0x90000000},
- {"ge", 0xa0000000},
- {"lt", 0xb0000000},
- {"gt", 0xc0000000},
- {"le", 0xd0000000},
- {"al", 0xe0000000},
- {"nv", 0xf0000000}
-};
-
struct asm_psr
{
const char *template;
@@ -396,10 +376,6 @@
/* Basic instruction code. */
unsigned long value;
- /* Offset into the template where the condition code (if any) will be.
- If zero, then the instruction is never conditional. */
- unsigned cond_offset;
-
/* Which architecture variant provides this instruction. */
unsigned long variant;
@@ -498,23 +474,6 @@
#define THUMB_PP_PC_LR 0x0100
#define THUMB_LOAD_BIT 0x0800
-struct thumb_opcode
-{
- /* Basic string to match. */
- const char * template;
-
- /* Basic instruction code. */
- unsigned long value;
-
- int size;
-
- /* Which CPU variants this exists for. */
- unsigned long variant;
-
- /* Function to call to parse args. */
- void (* parms) (char *);
-};
-
#define BAD_ARGS _("bad arguments to instruction")
#define BAD_PC _("r15 not allowed here")
#define BAD_COND _("instruction is not conditional")
@@ -7022,6 +6981,7 @@
md_assemble (char * str)
{
char *p;
+ const struct asm_opcode * opcode;
/* Align the previous label if needed. */
if (last_label_seen != NULL)
@@ -7048,8 +7008,6 @@
if (thumb_mode)
{
- const struct thumb_opcode * opcode;
-
opcode = hash_find_n (arm_tops_hsh, str, p - str);
if (opcode)
@@ -7063,7 +7021,7 @@
mapping_state (MAP_THUMB);
inst.instruction = opcode->value;
- inst.size = opcode->size;
+ inst.size = (opcode->value > 0xffff ? 4 : 2);
skip_whitespace (p);
opcode->parms (p);
output_inst (str);
@@ -7072,8 +7030,6 @@
}
else
{
- const struct asm_opcode * opcode;
-
opcode = hash_find_n (arm_ops_hsh, str, p - str);
if (opcode)
@@ -7398,1214 +7354,1323 @@
#endif
};
+/* Table of all conditional suffixes. 0xF... is for special-case,
+ unconditional instructions. */
+static const struct asm_cond conds[] =
+{
+ {"eq", 0x00000000},
+ {"ne", 0x10000000},
+ {"cs", 0x20000000}, {"hs", 0x20000000},
+ {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
+ {"mi", 0x40000000},
+ {"pl", 0x50000000},
+ {"vs", 0x60000000},
+ {"vc", 0x70000000},
+ {"hi", 0x80000000},
+ {"ls", 0x90000000},
+ {"ge", 0xa0000000},
+ {"lt", 0xb0000000},
+ {"gt", 0xc0000000},
+ {"le", 0xd0000000},
+ {"al", 0xe0000000}
+};
+
+/* Table of ARM-format instructions. These macros assemble the conditional
+ variants of each instruction from its bare form. */
+
+#define CE(mnem, opcode, aenc) \
+ { #mnem, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "eq", 0x0 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "ne", 0x1 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "cs", 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "hs", 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "cc", 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "ul", 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "lo", 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "mi", 0x4 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "pl", 0x5 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "vs", 0x6 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "vc", 0x7 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "hi", 0x8 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "ls", 0x9 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "ge", 0xa ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "lt", 0xb ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "gt", 0xc ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "le", 0xd ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #mnem "al", 0xe ## opcode, ARM_VARIANT, do_ ## aenc }
+
+#define CM(m1, m2, opcode, aenc) \
+ { #m1 #m2, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "eq" #m2, 0x0 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "ne" #m2, 0x1 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "cs" #m2, 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "hs" #m2, 0x2 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "cc" #m2, 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "ul" #m2, 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "lo" #m2, 0x3 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "mi" #m2, 0x4 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "pl" #m2, 0x5 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "vs" #m2, 0x6 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "vc" #m2, 0x7 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "hi" #m2, 0x8 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "ls" #m2, 0x9 ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "ge" #m2, 0xa ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "lt" #m2, 0xb ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "gt" #m2, 0xc ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "le" #m2, 0xd ## opcode, ARM_VARIANT, do_ ## aenc }, \
+ { #m1 "al" #m2, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }
+
+#define UE(mnem, opcode, aenc) \
+ { #mnem, 0xe ## opcode, ARM_VARIANT, do_ ## aenc }
+
+#define UF(mnem, opcode, aenc) \
+ { #mnem, 0xf ## opcode, ARM_VARIANT, do_ ## aenc }
+
static const struct asm_opcode insns[] =
{
- /* Core ARM Instructions. */
- {"and", 0xe0000000, 3, ARM_EXT_V1, do_arit},
- {"ands", 0xe0100000, 3, ARM_EXT_V1, do_arit},
- {"eor", 0xe0200000, 3, ARM_EXT_V1, do_arit},
- {"eors", 0xe0300000, 3, ARM_EXT_V1, do_arit},
- {"sub", 0xe0400000, 3, ARM_EXT_V1, do_arit},
- {"subs", 0xe0500000, 3, ARM_EXT_V1, do_arit},
- {"rsb", 0xe0600000, 3, ARM_EXT_V1, do_arit},
- {"rsbs", 0xe0700000, 3, ARM_EXT_V1, do_arit},
- {"add", 0xe0800000, 3, ARM_EXT_V1, do_arit},
- {"adds", 0xe0900000, 3, ARM_EXT_V1, do_arit},
- {"adc", 0xe0a00000, 3, ARM_EXT_V1, do_arit},
- {"adcs", 0xe0b00000, 3, ARM_EXT_V1, do_arit},
- {"sbc", 0xe0c00000, 3, ARM_EXT_V1, do_arit},
- {"sbcs", 0xe0d00000, 3, ARM_EXT_V1, do_arit},
- {"rsc", 0xe0e00000, 3, ARM_EXT_V1, do_arit},
- {"rscs", 0xe0f00000, 3, ARM_EXT_V1, do_arit},
- {"orr", 0xe1800000, 3, ARM_EXT_V1, do_arit},
- {"orrs", 0xe1900000, 3, ARM_EXT_V1, do_arit},
- {"bic", 0xe1c00000, 3, ARM_EXT_V1, do_arit},
- {"bics", 0xe1d00000, 3, ARM_EXT_V1, do_arit},
+#define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
+ CE(and, 0000000, arit),
+ CM(and,s, 0100000, arit),
+ CE(eor, 0200000, arit),
+ CM(eor,s, 0300000, arit),
+ CE(sub, 0400000, arit),
+ CM(sub,s, 0500000, arit),
+ CE(rsb, 0600000, arit),
+ CM(rsb,s, 0700000, arit),
+ CE(add, 0800000, arit),
+ CM(add,s, 0900000, arit),
+ CE(adc, 0a00000, arit),
+ CM(adc,s, 0b00000, arit),
+ CE(sbc, 0c00000, arit),
+ CM(sbc,s, 0d00000, arit),
+ CE(rsc, 0e00000, arit),
+ CM(rsc,s, 0f00000, arit),
+ CE(orr, 1800000, arit),
+ CM(orr,s, 1900000, arit),
+ CE(bic, 1c00000, arit),
+ CM(bic,s, 1d00000, arit),
+
+ CE(tst, 1100000, cmp),
+ CM(tst,s, 1100000, cmp),
+ CM(tst,p, 110f000, cmp),
+ CE(teq, 1300000, cmp),
+ CM(teq,s, 1300000, cmp),
+ CM(teq,p, 130f000, cmp),
+ CE(cmp, 1500000, cmp),
+ CM(cmp,s, 1500000, cmp),
+ CM(cmp,p, 150f000, cmp),
+ CE(cmn, 1700000, cmp),
+ CM(cmn,s, 1700000, cmp),
+ CM(cmn,p, 170f000, cmp),
- {"tst", 0xe1100000, 3, ARM_EXT_V1, do_cmp},
- {"tsts", 0xe1100000, 3, ARM_EXT_V1, do_cmp},
- {"tstp", 0xe110f000, 3, ARM_EXT_V1, do_cmp},
- {"teq", 0xe1300000, 3, ARM_EXT_V1, do_cmp},
- {"teqs", 0xe1300000, 3, ARM_EXT_V1, do_cmp},
- {"teqp", 0xe130f000, 3, ARM_EXT_V1, do_cmp},
- {"cmp", 0xe1500000, 3, ARM_EXT_V1, do_cmp},
- {"cmps", 0xe1500000, 3, ARM_EXT_V1, do_cmp},
- {"cmpp", 0xe150f000, 3, ARM_EXT_V1, do_cmp},
- {"cmn", 0xe1700000, 3, ARM_EXT_V1, do_cmp},
- {"cmns", 0xe1700000, 3, ARM_EXT_V1, do_cmp},
- {"cmnp", 0xe170f000, 3, ARM_EXT_V1, do_cmp},
+ CE(mov, 1a00000, mov),
+ CM(mov,s, 1b00000, mov),
+ CE(mvn, 1e00000, mov),
+ CM(mvn,s, 1f00000, mov),
- {"mov", 0xe1a00000, 3, ARM_EXT_V1, do_mov},
- {"movs", 0xe1b00000, 3, ARM_EXT_V1, do_mov},
- {"mvn", 0xe1e00000, 3, ARM_EXT_V1, do_mov},
- {"mvns", 0xe1f00000, 3, ARM_EXT_V1, do_mov},
+ CE(ldr, 4100000, ldst),
+ CM(ldr,b, 4500000, ldst),
+ CM(ldr,t, 4300000, ldstt),
+ CM(ldr,bt, 4700000, ldstt),
+ CE(str, 4000000, ldst),
+ CM(str,b, 4400000, ldst),
+ CM(str,t, 4200000, ldstt),
+ CM(str,bt, 4600000, ldstt),
- {"ldr", 0xe4100000, 3, ARM_EXT_V1, do_ldst},
- {"ldrb", 0xe4500000, 3, ARM_EXT_V1, do_ldst},
- {"ldrt", 0xe4300000, 3, ARM_EXT_V1, do_ldstt},
- {"ldrbt", 0xe4700000, 3, ARM_EXT_V1, do_ldstt},
- {"str", 0xe4000000, 3, ARM_EXT_V1, do_ldst},
- {"strb", 0xe4400000, 3, ARM_EXT_V1, do_ldst},
- {"strt", 0xe4200000, 3, ARM_EXT_V1, do_ldstt},
- {"strbt", 0xe4600000, 3, ARM_EXT_V1, do_ldstt},
+ CM(stm,ia, 8800000, ldmstm),
+ CM(stm,ib, 9800000, ldmstm),
+ CM(stm,da, 8000000, ldmstm),
+ CM(stm,db, 9000000, ldmstm),
+ CM(stm,fd, 9000000, ldmstm),
+ CM(stm,fa, 9800000, ldmstm),
+ CM(stm,ea, 8800000, ldmstm),
+ CM(stm,ed, 8000000, ldmstm),
- {"stmia", 0xe8800000, 3, ARM_EXT_V1, do_ldmstm},
- {"stmib", 0xe9800000, 3, ARM_EXT_V1, do_ldmstm},
- {"stmda", 0xe8000000, 3, ARM_EXT_V1, do_ldmstm},
- {"stmdb", 0xe9000000, 3, ARM_EXT_V1, do_ldmstm},
- {"stmfd", 0xe9000000, 3, ARM_EXT_V1, do_ldmstm},
- {"stmfa", 0xe9800000, 3, ARM_EXT_V1, do_ldmstm},
- {"stmea", 0xe8800000, 3, ARM_EXT_V1, do_ldmstm},
- {"stmed", 0xe8000000, 3, ARM_EXT_V1, do_ldmstm},
+ CM(ldm,ia, 8900000, ldmstm),
+ CM(ldm,ib, 9900000, ldmstm),
+ CM(ldm,da, 8100000, ldmstm),
+ CM(ldm,db, 9100000, ldmstm),
+ CM(ldm,fd, 8900000, ldmstm),
+ CM(ldm,fa, 8100000, ldmstm),
+ CM(ldm,ea, 9100000, ldmstm),
+ CM(ldm,ed, 9900000, ldmstm),
- {"ldmia", 0xe8900000, 3, ARM_EXT_V1, do_ldmstm},
- {"ldmib", 0xe9900000, 3, ARM_EXT_V1, do_ldmstm},
- {"ldmda", 0xe8100000, 3, ARM_EXT_V1, do_ldmstm},
- {"ldmdb", 0xe9100000, 3, ARM_EXT_V1, do_ldmstm},
- {"ldmfd", 0xe8900000, 3, ARM_EXT_V1, do_ldmstm},
- {"ldmfa", 0xe8100000, 3, ARM_EXT_V1, do_ldmstm},
- {"ldmea", 0xe9100000, 3, ARM_EXT_V1, do_ldmstm},
- {"ldmed", 0xe9900000, 3, ARM_EXT_V1, do_ldmstm},
-
- {"swi", 0xef000000, 3, ARM_EXT_V1, do_swi},
+ CE(swi, f000000, swi),
#ifdef TE_WINCE
/* XXX This is the wrong place to do this. Think multi-arch. */
- {"bl", 0xeb000000, 2, ARM_EXT_V1, do_branch},
- {"b", 0xea000000, 1, ARM_EXT_V1, do_branch},
+ CE(b, a000000, branch),
+ CE(bl, b000000, branch),
#else
- {"bl", 0xebfffffe, 2, ARM_EXT_V1, do_branch},
- {"b", 0xeafffffe, 1, ARM_EXT_V1, do_branch},
+ CE(b, afffffe, branch),
+ CE(bl, bfffffe, branch),
#endif
/* Pseudo ops. */
- {"adr", 0xe28f0000, 3, ARM_EXT_V1, do_adr},
- {"adrl", 0xe28f0000, 3, ARM_EXT_V1, do_adrl},
- {"nop", 0xe1a00000, 3, ARM_EXT_V1, do_nop},
+ CE(adr, 28f0000, adr),
+ CM(adr,l, 28f0000, adrl),
+ CE(nop, 1a00000, nop),
- /* ARM 2 multiplies. */
- {"mul", 0xe0000090, 3, ARM_EXT_V2, do_mul},
- {"muls", 0xe0100090, 3, ARM_EXT_V2, do_mul},
- {"mla", 0xe0200090, 3, ARM_EXT_V2, do_mla},
- {"mlas", 0xe0300090, 3, ARM_EXT_V2, do_mla},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
+ CE(mul, 0000090, mul),
+ CM(mul,s, 0100090, mul),
+ CE(mla, 0200090, mla),
+ CM(mla,s, 0300090, mla),
/* Generic coprocessor instructions. */
- {"cdp", 0xee000000, 3, ARM_EXT_V2, do_cdp},
- {"ldc", 0xec100000, 3, ARM_EXT_V2, do_lstc},
- {"ldcl", 0xec500000, 3, ARM_EXT_V2, do_lstc},
- {"stc", 0xec000000, 3, ARM_EXT_V2, do_lstc},
- {"stcl", 0xec400000, 3, ARM_EXT_V2, do_lstc},
- {"mcr", 0xee000010, 3, ARM_EXT_V2, do_co_reg},
- {"mrc", 0xee100010, 3, ARM_EXT_V2, do_co_reg},
+ CE(cdp, e000000, cdp),
+ CE(ldc, c100000, lstc),
+ CM(ldc,l, c500000, lstc),
+ CE(stc, c000000, lstc),
+ CM(stc,l, c400000, lstc),
+ CE(mcr, e000010, co_reg),
+ CE(mrc, e100010, co_reg),
- /* ARM 3 - swp instructions. */
- {"swp", 0xe1000090, 3, ARM_EXT_V2S, do_swap},
- {"swpb", 0xe1400090, 3, ARM_EXT_V2S, do_swap},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
+ CE(swp, 1000090, swap),
+ CM(swp,b, 1400090, swap),
- /* ARM 6 Status register instructions. */
- {"mrs", 0xe10f0000, 3, ARM_EXT_V3, do_mrs},
- {"msr", 0xe120f000, 3, ARM_EXT_V3, do_msr},
- /* ScottB: our code uses 0xe128f000 for msr.
- NickC: but this is wrong because the bits 16 through 19 are
- handled by the PSR_xxx defines above. */
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
+ CE(mrs, 10f0000, mrs),
+ CE(msr, 120f000, msr),
- /* ARM 7M long multiplies. */
- {"smull", 0xe0c00090, 5, ARM_EXT_V3M, do_mull},
- {"smulls", 0xe0d00090, 5, ARM_EXT_V3M, do_mull},
- {"umull", 0xe0800090, 5, ARM_EXT_V3M, do_mull},
- {"umulls", 0xe0900090, 5, ARM_EXT_V3M, do_mull},
- {"smlal", 0xe0e00090, 5, ARM_EXT_V3M, do_mull},
- {"smlals", 0xe0f00090, 5, ARM_EXT_V3M, do_mull},
- {"umlal", 0xe0a00090, 5, ARM_EXT_V3M, do_mull},
- {"umlals", 0xe0b00090, 5, ARM_EXT_V3M, do_mull},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
+ CE(smull, 0c00090, mull),
+ CM(smull,s, 0d00090, mull),
+ CE(umull, 0800090, mull),
+ CM(umull,s, 0900090, mull),
+ CE(smlal, 0e00090, mull),
+ CM(smlal,s, 0f00090, mull),
+ CE(umlal, 0a00090, mull),
+ CM(umlal,s, 0b00090, mull),
- /* ARM Architecture 4. */
- {"ldrh", 0xe01000b0, 3, ARM_EXT_V4, do_ldstv4},
- {"ldrsh", 0xe01000f0, 3, ARM_EXT_V4, do_ldstv4},
- {"ldrsb", 0xe01000d0, 3, ARM_EXT_V4, do_ldstv4},
- {"strh", 0xe00000b0, 3, ARM_EXT_V4, do_ldstv4},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
+ CM(ldr,h, 01000b0, ldstv4),
+ CM(ldr,sh, 01000f0, ldstv4),
+ CM(ldr,sb, 01000d0, ldstv4),
+ CM(str,h, 00000b0, ldstv4),
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
/* ARM Architecture 4T. */
/* Note: bx (and blx) are required on V5, even if the processor does
not support Thumb. */
- {"bx", 0xe12fff10, 2, ARM_EXT_V4T | ARM_EXT_V5, do_bx},
+ CE(bx, 12fff10, bx),
- /* ARM Architecture 5T. */
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
/* Note: blx has 2 variants; the .value coded here is for
BLX(2). Only this variant has conditional execution. */
- {"blx", 0xe12fff30, 3, ARM_EXT_V5, do_blx},
- {"clz", 0xe16f0f10, 3, ARM_EXT_V5, do_clz},
- {"bkpt", 0xe1200070, 0, ARM_EXT_V5, do_bkpt},
- {"ldc2", 0xfc100000, 0, ARM_EXT_V5, do_lstc},
- {"ldc2l", 0xfc500000, 0, ARM_EXT_V5, do_lstc},
- {"stc2", 0xfc000000, 0, ARM_EXT_V5, do_lstc},
- {"stc2l", 0xfc400000, 0, ARM_EXT_V5, do_lstc},
- {"cdp2", 0xfe000000, 0, ARM_EXT_V5, do_cdp},
- {"mcr2", 0xfe000010, 0, ARM_EXT_V5, do_co_reg},
- {"mrc2", 0xfe100010, 0, ARM_EXT_V5, do_co_reg},
+ CE(blx, 12fff30, blx),
+ CE(clz, 16f0f10, clz),
+ UE(bkpt, 1200070, bkpt),
+ UF(ldc2, c100000, lstc),
+ UF(ldc2l, c500000, lstc),
+ UF(stc2, c000000, lstc),
+ UF(stc2l, c400000, lstc),
+ UF(cdp2, e000000, cdp),
+ UF(mcr2, e000010, co_reg),
+ UF(mrc2, e100010, co_reg),
- /* ARM Architecture 5TExP. */
- {"smlabb", 0xe1000080, 6, ARM_EXT_V5ExP, do_smla},
- {"smlatb", 0xe10000a0, 6, ARM_EXT_V5ExP, do_smla},
- {"smlabt", 0xe10000c0, 6, ARM_EXT_V5ExP, do_smla},
- {"smlatt", 0xe10000e0, 6, ARM_EXT_V5ExP, do_smla},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
+ CE(smlabb, 1000080, smla),
+ CE(smlatb, 10000a0, smla),
+ CE(smlabt, 10000c0, smla),
+ CE(smlatt, 10000e0, smla),
- {"smlawb", 0xe1200080, 6, ARM_EXT_V5ExP, do_smla},
- {"smlawt", 0xe12000c0, 6, ARM_EXT_V5ExP, do_smla},
+ CE(smlawb, 1200080, smla),
+ CE(smlawt, 12000c0, smla),
- {"smlalbb", 0xe1400080, 7, ARM_EXT_V5ExP, do_smlal},
- {"smlaltb", 0xe14000a0, 7, ARM_EXT_V5ExP, do_smlal},
- {"smlalbt", 0xe14000c0, 7, ARM_EXT_V5ExP, do_smlal},
- {"smlaltt", 0xe14000e0, 7, ARM_EXT_V5ExP, do_smlal},
+ CE(smlalbb, 1400080, smlal),
+ CE(smlaltb, 14000a0, smlal),
+ CE(smlalbt, 14000c0, smlal),
+ CE(smlaltt, 14000e0, smlal),
- {"smulbb", 0xe1600080, 6, ARM_EXT_V5ExP, do_smul},
- {"smultb", 0xe16000a0, 6, ARM_EXT_V5ExP, do_smul},
- {"smulbt", 0xe16000c0, 6, ARM_EXT_V5ExP, do_smul},
- {"smultt", 0xe16000e0, 6, ARM_EXT_V5ExP, do_smul},
+ CE(smulbb, 1600080, smul),
+ CE(smultb, 16000a0, smul),
+ CE(smulbt, 16000c0, smul),
+ CE(smultt, 16000e0, smul),
- {"smulwb", 0xe12000a0, 6, ARM_EXT_V5ExP, do_smul},
- {"smulwt", 0xe12000e0, 6, ARM_EXT_V5ExP, do_smul},
+ CE(smulwb, 12000a0, smul),
+ CE(smulwt, 12000e0, smul),
- {"qadd", 0xe1000050, 4, ARM_EXT_V5ExP, do_qadd},
- {"qdadd", 0xe1400050, 5, ARM_EXT_V5ExP, do_qadd},
- {"qsub", 0xe1200050, 4, ARM_EXT_V5ExP, do_qadd},
- {"qdsub", 0xe1600050, 5, ARM_EXT_V5ExP, do_qadd},
+ CE(qadd, 1000050, qadd),
+ CE(qdadd, 1400050, qadd),
+ CE(qsub, 1200050, qadd),
+ CE(qdsub, 1600050, qadd),
- /* ARM Architecture 5TE. */
- {"pld", 0xf450f000, 0, ARM_EXT_V5E, do_pld},
- {"ldrd", 0xe00000d0, 3, ARM_EXT_V5E, do_ldrd},
- {"strd", 0xe00000f0, 3, ARM_EXT_V5E, do_ldrd},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
+ UF(pld, 450f000, pld),
+ CM(ldr,d, 00000d0, ldrd),
+ CM(str,d, 00000f0, ldrd),
- {"mcrr", 0xec400000, 4, ARM_EXT_V5E, do_co_reg2c},
- {"mrrc", 0xec500000, 4, ARM_EXT_V5E, do_co_reg2c},
+ CE(mcrr, c400000, co_reg2c),
+ CE(mrrc, c500000, co_reg2c),
- /* ARM Architecture 5TEJ. */
- {"bxj", 0xe12fff20, 3, ARM_EXT_V5J, do_bxj},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
+ CE(bxj, 12fff20, bxj),
- /* ARM V6. */
- { "cps", 0xf1020000, 0, ARM_EXT_V6, do_cps},
- { "cpsie", 0xf1080000, 0, ARM_EXT_V6, do_cpsi},
- { "cpsid", 0xf10C0000, 0, ARM_EXT_V6, do_cpsi},
- { "ldrex", 0xe1900f9f, 5, ARM_EXT_V6, do_ldrex},
- { "mcrr2", 0xfc400000, 0, ARM_EXT_V6, do_co_reg2c},
- { "mrrc2", 0xfc500000, 0, ARM_EXT_V6, do_co_reg2c},
- { "pkhbt", 0xe6800010, 5, ARM_EXT_V6, do_pkhbt},
- { "pkhtb", 0xe6800050, 5, ARM_EXT_V6, do_pkhtb},
- { "qadd16", 0xe6200f10, 6, ARM_EXT_V6, do_qadd16},
- { "qadd8", 0xe6200f90, 5, ARM_EXT_V6, do_qadd16},
- { "qaddsubx", 0xe6200f30, 8, ARM_EXT_V6, do_qadd16},
- { "qsub16", 0xe6200f70, 6, ARM_EXT_V6, do_qadd16},
- { "qsub8", 0xe6200ff0, 5, ARM_EXT_V6, do_qadd16},
- { "qsubaddx", 0xe6200f50, 8, ARM_EXT_V6, do_qadd16},
- { "sadd16", 0xe6100f10, 6, ARM_EXT_V6, do_qadd16},
- { "sadd8", 0xe6100f90, 5, ARM_EXT_V6, do_qadd16},
- { "saddsubx", 0xe6100f30, 8, ARM_EXT_V6, do_qadd16},
- { "shadd16", 0xe6300f10, 7, ARM_EXT_V6, do_qadd16},
- { "shadd8", 0xe6300f90, 6, ARM_EXT_V6, do_qadd16},
- { "shaddsubx", 0xe6300f30, 9, ARM_EXT_V6, do_qadd16},
- { "shsub16", 0xe6300f70, 7, ARM_EXT_V6, do_qadd16},
- { "shsub8", 0xe6300ff0, 6, ARM_EXT_V6, do_qadd16},
- { "shsubaddx", 0xe6300f50, 9, ARM_EXT_V6, do_qadd16},
- { "ssub16", 0xe6100f70, 6, ARM_EXT_V6, do_qadd16},
- { "ssub8", 0xe6100ff0, 5, ARM_EXT_V6, do_qadd16},
- { "ssubaddx", 0xe6100f50, 8, ARM_EXT_V6, do_qadd16},
- { "uadd16", 0xe6500f10, 6, ARM_EXT_V6, do_qadd16},
- { "uadd8", 0xe6500f90, 5, ARM_EXT_V6, do_qadd16},
- { "uaddsubx", 0xe6500f30, 8, ARM_EXT_V6, do_qadd16},
- { "uhadd16", 0xe6700f10, 7, ARM_EXT_V6, do_qadd16},
- { "uhadd8", 0xe6700f90, 6, ARM_EXT_V6, do_qadd16},
- { "uhaddsubx", 0xe6700f30, 9, ARM_EXT_V6, do_qadd16},
- { "uhsub16", 0xe6700f70, 7, ARM_EXT_V6, do_qadd16},
- { "uhsub8", 0xe6700ff0, 6, ARM_EXT_V6, do_qadd16},
- { "uhsubaddx", 0xe6700f50, 9, ARM_EXT_V6, do_qadd16},
- { "uqadd16", 0xe6600f10, 7, ARM_EXT_V6, do_qadd16},
- { "uqadd8", 0xe6600f90, 6, ARM_EXT_V6, do_qadd16},
- { "uqaddsubx", 0xe6600f30, 9, ARM_EXT_V6, do_qadd16},
- { "uqsub16", 0xe6600f70, 7, ARM_EXT_V6, do_qadd16},
- { "uqsub8", 0xe6600ff0, 6, ARM_EXT_V6, do_qadd16},
- { "uqsubaddx", 0xe6600f50, 9, ARM_EXT_V6, do_qadd16},
- { "usub16", 0xe6500f70, 6, ARM_EXT_V6, do_qadd16},
- { "usub8", 0xe6500ff0, 5, ARM_EXT_V6, do_qadd16},
- { "usubaddx", 0xe6500f50, 8, ARM_EXT_V6, do_qadd16},
- { "rev", 0xe6bf0f30, 3, ARM_EXT_V6, do_rev},
- { "rev16", 0xe6bf0fb0, 5, ARM_EXT_V6, do_rev},
- { "revsh", 0xe6ff0fb0, 5, ARM_EXT_V6, do_rev},
- { "rfeia", 0xf8900a00, 0, ARM_EXT_V6, do_rfe},
- { "rfeib", 0xf9900a00, 0, ARM_EXT_V6, do_rfe},
- { "rfeda", 0xf8100a00, 0, ARM_EXT_V6, do_rfe},
- { "rfedb", 0xf9100a00, 0, ARM_EXT_V6, do_rfe},
- { "rfefd", 0xf8900a00, 0, ARM_EXT_V6, do_rfe},
- { "rfefa", 0xf9900a00, 0, ARM_EXT_V6, do_rfe},
- { "rfeea", 0xf8100a00, 0, ARM_EXT_V6, do_rfe},
- { "rfeed", 0xf9100a00, 0, ARM_EXT_V6, do_rfe},
- { "sxtah", 0xe6b00070, 5, ARM_EXT_V6, do_sxtah},
- { "sxtab16", 0xe6800070, 7, ARM_EXT_V6, do_sxtah},
- { "sxtab", 0xe6a00070, 5, ARM_EXT_V6, do_sxtah},
- { "sxth", 0xe6bf0070, 4, ARM_EXT_V6, do_sxth},
- { "sxtb16", 0xe68f0070, 6, ARM_EXT_V6, do_sxth},
- { "sxtb", 0xe6af0070, 4, ARM_EXT_V6, do_sxth},
- { "uxtah", 0xe6f00070, 5, ARM_EXT_V6, do_sxtah},
- { "uxtab16", 0xe6c00070, 7, ARM_EXT_V6, do_sxtah},
- { "uxtab", 0xe6e00070, 5, ARM_EXT_V6, do_sxtah},
- { "uxth", 0xe6ff0070, 4, ARM_EXT_V6, do_sxth},
- { "uxtb16", 0xe6cf0070, 6, ARM_EXT_V6, do_sxth},
- { "uxtb", 0xe6ef0070, 4, ARM_EXT_V6, do_sxth},
- { "sel", 0xe68000b0, 3, ARM_EXT_V6, do_qadd16},
- { "setend", 0xf1010000, 0, ARM_EXT_V6, do_setend},
- { "smlad", 0xe7000010, 5, ARM_EXT_V6, do_smla},
- { "smladx", 0xe7000030, 6, ARM_EXT_V6, do_smla},
- { "smlald", 0xe7400010, 6, ARM_EXT_V6, do_smlal},
- { "smlaldx", 0xe7400030, 7, ARM_EXT_V6, do_smlal},
- { "smlsd", 0xe7000050, 5, ARM_EXT_V6, do_smla},
- { "smlsdx", 0xe7000070, 6, ARM_EXT_V6, do_smla},
- { "smlsld", 0xe7400050, 6, ARM_EXT_V6, do_smlal},
- { "smlsldx", 0xe7400070, 7, ARM_EXT_V6, do_smlal},
- { "smmla", 0xe7500010, 5, ARM_EXT_V6, do_smla},
- { "smmlar", 0xe7500030, 6, ARM_EXT_V6, do_smla},
- { "smmls", 0xe75000d0, 5, ARM_EXT_V6, do_smla},
- { "smmlsr", 0xe75000f0, 6, ARM_EXT_V6, do_smla},
- { "smmul", 0xe750f010, 5, ARM_EXT_V6, do_smul},
- { "smmulr", 0xe750f030, 6, ARM_EXT_V6, do_smul},
- { "smuad", 0xe700f010, 5, ARM_EXT_V6, do_smul},
- { "smuadx", 0xe700f030, 6, ARM_EXT_V6, do_smul},
- { "smusd", 0xe700f050, 5, ARM_EXT_V6, do_smul},
- { "smusdx", 0xe700f070, 6, ARM_EXT_V6, do_smul},
- { "srsia", 0xf8cd0500, 0, ARM_EXT_V6, do_srs},
- { "srsib", 0xf9cd0500, 0, ARM_EXT_V6, do_srs},
- { "srsda", 0xf84d0500, 0, ARM_EXT_V6, do_srs},
- { "srsdb", 0xf94d0500, 0, ARM_EXT_V6, do_srs},
- { "ssat", 0xe6a00010, 4, ARM_EXT_V6, do_ssat},
- { "ssat16", 0xe6a00f30, 6, ARM_EXT_V6, do_ssat16},
- { "strex", 0xe1800f90, 5, ARM_EXT_V6, do_strex},
- { "umaal", 0xe0400090, 5, ARM_EXT_V6, do_smlal},
- { "usad8", 0xe780f010, 5, ARM_EXT_V6, do_smul},
- { "usada8", 0xe7800010, 6, ARM_EXT_V6, do_smla},
- { "usat", 0xe6e00010, 4, ARM_EXT_V6, do_usat},
- { "usat16", 0xe6e00f30, 6, ARM_EXT_V6, do_usat16},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
+ UF(cps, 1020000, cps),
+ UF(cpsie, 1080000, cpsi),
+ UF(cpsid, 10c0000, cpsi),
+ CE(ldrex, 1900f9f, ldrex),
+ UF(mcrr2, c400000, co_reg2c),
+ UF(mrrc2, c500000, co_reg2c),
+ CE(pkhbt, 6800010, pkhbt),
+ CE(pkhtb, 6800050, pkhtb),
+ CE(qadd16, 6200f10, qadd16),
+ CE(qadd8, 6200f90, qadd16),
+ CE(qaddsubx, 6200f30, qadd16),
+ CE(qsub16, 6200f70, qadd16),
+ CE(qsub8, 6200ff0, qadd16),
+ CE(qsubaddx, 6200f50, qadd16),
+ CE(sadd16, 6100f10, qadd16),
+ CE(sadd8, 6100f90, qadd16),
+ CE(saddsubx, 6100f30, qadd16),
+ CE(shadd16, 6300f10, qadd16),
+ CE(shadd8, 6300f90, qadd16),
+ CE(shaddsubx, 6300f30, qadd16),
+ CE(shsub16, 6300f70, qadd16),
+ CE(shsub8, 6300ff0, qadd16),
+ CE(shsubaddx, 6300f50, qadd16),
+ CE(ssub16, 6100f70, qadd16),
+ CE(ssub8, 6100ff0, qadd16),
+ CE(ssubaddx, 6100f50, qadd16),
+ CE(uadd16, 6500f10, qadd16),
+ CE(uadd8, 6500f90, qadd16),
+ CE(uaddsubx, 6500f30, qadd16),
+ CE(uhadd16, 6700f10, qadd16),
+ CE(uhadd8, 6700f90, qadd16),
+ CE(uhaddsubx, 6700f30, qadd16),
+ CE(uhsub16, 6700f70, qadd16),
+ CE(uhsub8, 6700ff0, qadd16),
+ CE(uhsubaddx, 6700f50, qadd16),
+ CE(uqadd16, 6600f10, qadd16),
+ CE(uqadd8, 6600f90, qadd16),
+ CE(uqaddsubx, 6600f30, qadd16),
+ CE(uqsub16, 6600f70, qadd16),
+ CE(uqsub8, 6600ff0, qadd16),
+ CE(uqsubaddx, 6600f50, qadd16),
+ CE(usub16, 6500f70, qadd16),
+ CE(usub8, 6500ff0, qadd16),
+ CE(usubaddx, 6500f50, qadd16),
+ CE(rev, 6bf0f30, rev),
+ CE(rev16, 6bf0fb0, rev),
+ CE(revsh, 6ff0fb0, rev),
+ UF(rfeia, 8900a00, rfe),
+ UF(rfeib, 9900a00, rfe),
+ UF(rfeda, 8100a00, rfe),
+ UF(rfedb, 9100a00, rfe),
+ UF(rfefd, 8900a00, rfe),
+ UF(rfefa, 9900a00, rfe),
+ UF(rfeea, 8100a00, rfe),
+ UF(rfeed, 9100a00, rfe),
+ CE(sxtah, 6b00070, sxtah),
+ CE(sxtab16, 6800070, sxtah),
+ CE(sxtab, 6a00070, sxtah),
+ CE(sxth, 6bf0070, sxth),
+ CE(sxtb16, 68f0070, sxth),
+ CE(sxtb, 6af0070, sxth),
+ CE(uxtah, 6f00070, sxtah),
+ CE(uxtab16, 6c00070, sxtah),
+ CE(uxtab, 6e00070, sxtah),
+ CE(uxth, 6ff0070, sxth),
+ CE(uxtb16, 6cf0070, sxth),
+ CE(uxtb, 6ef0070, sxth),
+ CE(sel, 68000b0, qadd16),
+ UF(setend, 1010000, setend),
+ CE(smlad, 7000010, smla),
+ CE(smladx, 7000030, smla),
+ CE(smlald, 7400010, smlal),
+ CE(smlaldx, 7400030, smlal),
+ CE(smlsd, 7000050, smla),
+ CE(smlsdx, 7000070, smla),
+ CE(smlsld, 7400050, smlal),
+ CE(smlsldx, 7400070, smlal),
+ CE(smmla, 7500010, smla),
+ CE(smmlar, 7500030, smla),
+ CE(smmls, 75000d0, smla),
+ CE(smmlsr, 75000f0, smla),
+ CE(smmul, 750f010, smul),
+ CE(smmulr, 750f030, smul),
+ CE(smuad, 700f010, smul),
+ CE(smuadx, 700f030, smul),
+ CE(smusd, 700f050, smul),
+ CE(smusdx, 700f070, smul),
+ UF(srsia, 8cd0500, srs),
+ UF(srsib, 9cd0500, srs),
+ UF(srsda, 84d0500, srs),
+ UF(srsdb, 94d0500, srs),
+ CE(ssat, 6a00010, ssat),
+ CE(ssat16, 6a00f30, ssat16),
+ CE(strex, 1800f90, strex),
+ CE(umaal, 0400090, smlal),
+ CE(usad8, 780f010, smul),
+ CE(usada8, 7800010, smla),
+ CE(usat, 6e00010, usat),
+ CE(usat16, 6e00f30, usat16),
- /* ARM V6K. */
- { "clrex", 0xf57ff01f, 0, ARM_EXT_V6K, do_empty},
- { "ldrexb", 0xe1d00f9f, 6, ARM_EXT_V6K, do_ldrex},
- { "ldrexd", 0xe1b00f9f, 6, ARM_EXT_V6K, do_ldrex},
- { "ldrexh", 0xe1f00f9f, 6, ARM_EXT_V6K, do_ldrex},
- { "sev", 0xe320f004, 3, ARM_EXT_V6K, do_empty},
- { "strexb", 0xe1c00f90, 6, ARM_EXT_V6K, do_strex},
- { "strexd", 0xe1a00f90, 6, ARM_EXT_V6K, do_strex},
- { "strexh", 0xe1e00f90, 6, ARM_EXT_V6K, do_strex},
- { "wfe", 0xe320f002, 3, ARM_EXT_V6K, do_empty},
- { "wfi", 0xe320f003, 3, ARM_EXT_V6K, do_empty},
- { "yield", 0xe320f001, 5, ARM_EXT_V6K, do_empty},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V6K
+ UF(clrex, 57ff01f, empty),
+ CE(ldrexb, 1d00f9f, ldrex),
+ CE(ldrexd, 1b00f9f, ldrex),
+ CE(ldrexh, 1f00f9f, ldrex),
+ CE(sev, 320f004, empty),
+ CE(strexb, 1c00f90, strex),
+ CE(strexd, 1a00f90, strex),
+ CE(strexh, 1e00f90, strex),
+ CE(wfe, 320f002, empty),
+ CE(wfi, 320f003, empty),
+ CE(yield, 320f001, empty),
- /* ARM V6Z. */
- { "smi", 0xe1600070, 3, ARM_EXT_V6Z, do_smi},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V6Z
+ CE(smi, 1600070, smi),
- /* ARM V6T2. */
- { "bfc", 0xe7c0001f, 3, ARM_EXT_V6T2, do_bfc},
- { "bfi", 0xe7c00010, 3, ARM_EXT_V6T2, do_bfi},
- { "mls", 0xe0600090, 3, ARM_EXT_V6T2, do_mls},
- { "movw", 0xe3000000, 4, ARM_EXT_V6T2, do_mov16},
- { "movt", 0xe3400000, 4, ARM_EXT_V6T2, do_mov16},
- { "rbit", 0xe3ff0f30, 4, ARM_EXT_V6T2, do_rbit},
- { "sbfx", 0xe7a00050, 4, ARM_EXT_V6T2, do_bfx},
- { "ubfx", 0xe7e00050, 4, ARM_EXT_V6T2, do_bfx},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_EXT_V6T2
+ CE(bfc, 7c0001f, bfc),
+ CE(bfi, 7c00010, bfi),
+ CE(mls, 0600090, mls),
+ CE(movw, 3000000, mov16),
+ CE(movt, 3400000, mov16),
+ CE(rbit, 3ff0f30, rbit),
+ CE(sbfx, 7a00050, bfx),
+ CE(ubfx, 7e00050, bfx),
- { "ldrht", 0xe03000b0, 3, ARM_EXT_V6T2, do_ldsttv4},
- { "ldrsht", 0xe03000f0, 3, ARM_EXT_V6T2, do_ldsttv4},
- { "ldrsbt", 0xe03000d0, 3, ARM_EXT_V6T2, do_ldsttv4},
- { "strht", 0xe02000b0, 3, ARM_EXT_V6T2, do_ldsttv4},
+ CM(ldr,ht, 03000b0, ldsttv4),
+ CM(ldr,sht, 03000f0, ldsttv4),
+ CM(ldr,sbt, 03000d0, ldsttv4),
+ CM(str,ht, 02000b0, ldsttv4),
- /* Core FPA instruction set (V1). */
- {"wfs", 0xee200110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
- {"rfs", 0xee300110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
- {"wfc", 0xee400110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
- {"rfc", 0xee500110, 3, FPU_FPA_EXT_V1, do_fpa_ctrl},
+#undef ARM_VARIANT
+#define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
+ CE(wfs, e200110, fpa_ctrl),
+ CE(rfs, e300110, fpa_ctrl),
+ CE(wfc, e400110, fpa_ctrl),
+ CE(rfc, e500110, fpa_ctrl),
- {"ldfs", 0xec100100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
- {"ldfd", 0xec108100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
- {"ldfe", 0xec500100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
- {"ldfp", 0xec508100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
+ CM(ldf,s, c100100, fpa_ldst),
+ CM(ldf,d, c108100, fpa_ldst),
+ CM(ldf,e, c500100, fpa_ldst),
+ CM(ldf,p, c508100, fpa_ldst),
- {"stfs", 0xec000100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
- {"stfd", 0xec008100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
- {"stfe", 0xec400100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
- {"stfp", 0xec408100, 3, FPU_FPA_EXT_V1, do_fpa_ldst},
+ CM(stf,s, c000100, fpa_ldst),
+ CM(stf,d, c008100, fpa_ldst),
+ CM(stf,e, c400100, fpa_ldst),
+ CM(stf,p, c408100, fpa_ldst),
- {"mvfs", 0xee008100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfsp", 0xee008120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfsm", 0xee008140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfsz", 0xee008160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfd", 0xee008180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfdp", 0xee0081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfdm", 0xee0081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfdz", 0xee0081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfe", 0xee088100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfep", 0xee088120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfem", 0xee088140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mvfez", 0xee088160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(mvf,s, e008100, fpa_monadic),
+ CM(mvf,sp, e008120, fpa_monadic),
+ CM(mvf,sm, e008140, fpa_monadic),
+ CM(mvf,sz, e008160, fpa_monadic),
+ CM(mvf,d, e008180, fpa_monadic),
+ CM(mvf,dp, e0081a0, fpa_monadic),
+ CM(mvf,dm, e0081c0, fpa_monadic),
+ CM(mvf,dz, e0081e0, fpa_monadic),
+ CM(mvf,e, e088100, fpa_monadic),
+ CM(mvf,ep, e088120, fpa_monadic),
+ CM(mvf,em, e088140, fpa_monadic),
+ CM(mvf,ez, e088160, fpa_monadic),
- {"mnfs", 0xee108100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfsp", 0xee108120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfsm", 0xee108140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfsz", 0xee108160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfd", 0xee108180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfdp", 0xee1081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfdm", 0xee1081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfdz", 0xee1081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfe", 0xee188100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfep", 0xee188120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfem", 0xee188140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"mnfez", 0xee188160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(mnf,s, e108100, fpa_monadic),
+ CM(mnf,sp, e108120, fpa_monadic),
+ CM(mnf,sm, e108140, fpa_monadic),
+ CM(mnf,sz, e108160, fpa_monadic),
+ CM(mnf,d, e108180, fpa_monadic),
+ CM(mnf,dp, e1081a0, fpa_monadic),
+ CM(mnf,dm, e1081c0, fpa_monadic),
+ CM(mnf,dz, e1081e0, fpa_monadic),
+ CM(mnf,e, e188100, fpa_monadic),
+ CM(mnf,ep, e188120, fpa_monadic),
+ CM(mnf,em, e188140, fpa_monadic),
+ CM(mnf,ez, e188160, fpa_monadic),
- {"abss", 0xee208100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"abssp", 0xee208120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"abssm", 0xee208140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"abssz", 0xee208160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"absd", 0xee208180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"absdp", 0xee2081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"absdm", 0xee2081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"absdz", 0xee2081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"abse", 0xee288100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"absep", 0xee288120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"absem", 0xee288140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"absez", 0xee288160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(abs,s, e208100, fpa_monadic),
+ CM(abs,sp, e208120, fpa_monadic),
+ CM(abs,sm, e208140, fpa_monadic),
+ CM(abs,sz, e208160, fpa_monadic),
+ CM(abs,d, e208180, fpa_monadic),
+ CM(abs,dp, e2081a0, fpa_monadic),
+ CM(abs,dm, e2081c0, fpa_monadic),
+ CM(abs,dz, e2081e0, fpa_monadic),
+ CM(abs,e, e288100, fpa_monadic),
+ CM(abs,ep, e288120, fpa_monadic),
+ CM(abs,em, e288140, fpa_monadic),
+ CM(abs,ez, e288160, fpa_monadic),
- {"rnds", 0xee308100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rndsp", 0xee308120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rndsm", 0xee308140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rndsz", 0xee308160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rndd", 0xee308180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rnddp", 0xee3081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rnddm", 0xee3081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rnddz", 0xee3081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rnde", 0xee388100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rndep", 0xee388120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rndem", 0xee388140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"rndez", 0xee388160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(rnd,s, e308100, fpa_monadic),
+ CM(rnd,sp, e308120, fpa_monadic),
+ CM(rnd,sm, e308140, fpa_monadic),
+ CM(rnd,sz, e308160, fpa_monadic),
+ CM(rnd,d, e308180, fpa_monadic),
+ CM(rnd,dp, e3081a0, fpa_monadic),
+ CM(rnd,dm, e3081c0, fpa_monadic),
+ CM(rnd,dz, e3081e0, fpa_monadic),
+ CM(rnd,e, e388100, fpa_monadic),
+ CM(rnd,ep, e388120, fpa_monadic),
+ CM(rnd,em, e388140, fpa_monadic),
+ CM(rnd,ez, e388160, fpa_monadic),
- {"sqts", 0xee408100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtsp", 0xee408120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtsm", 0xee408140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtsz", 0xee408160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtd", 0xee408180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtdp", 0xee4081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtdm", 0xee4081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtdz", 0xee4081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqte", 0xee488100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtep", 0xee488120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtem", 0xee488140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sqtez", 0xee488160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(sqt,s, e408100, fpa_monadic),
+ CM(sqt,sp, e408120, fpa_monadic),
+ CM(sqt,sm, e408140, fpa_monadic),
+ CM(sqt,sz, e408160, fpa_monadic),
+ CM(sqt,d, e408180, fpa_monadic),
+ CM(sqt,dp, e4081a0, fpa_monadic),
+ CM(sqt,dm, e4081c0, fpa_monadic),
+ CM(sqt,dz, e4081e0, fpa_monadic),
+ CM(sqt,e, e488100, fpa_monadic),
+ CM(sqt,ep, e488120, fpa_monadic),
+ CM(sqt,em, e488140, fpa_monadic),
+ CM(sqt,ez, e488160, fpa_monadic),
- {"logs", 0xee508100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logsp", 0xee508120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logsm", 0xee508140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logsz", 0xee508160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logd", 0xee508180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logdp", 0xee5081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logdm", 0xee5081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logdz", 0xee5081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"loge", 0xee588100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logep", 0xee588120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logem", 0xee588140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"logez", 0xee588160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(log,s, e508100, fpa_monadic),
+ CM(log,sp, e508120, fpa_monadic),
+ CM(log,sm, e508140, fpa_monadic),
+ CM(log,sz, e508160, fpa_monadic),
+ CM(log,d, e508180, fpa_monadic),
+ CM(log,dp, e5081a0, fpa_monadic),
+ CM(log,dm, e5081c0, fpa_monadic),
+ CM(log,dz, e5081e0, fpa_monadic),
+ CM(log,e, e588100, fpa_monadic),
+ CM(log,ep, e588120, fpa_monadic),
+ CM(log,em, e588140, fpa_monadic),
+ CM(log,ez, e588160, fpa_monadic),
- {"lgns", 0xee608100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgnsp", 0xee608120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgnsm", 0xee608140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgnsz", 0xee608160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgnd", 0xee608180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgndp", 0xee6081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgndm", 0xee6081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgndz", 0xee6081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgne", 0xee688100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgnep", 0xee688120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgnem", 0xee688140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"lgnez", 0xee688160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(lgn,s, e608100, fpa_monadic),
+ CM(lgn,sp, e608120, fpa_monadic),
+ CM(lgn,sm, e608140, fpa_monadic),
+ CM(lgn,sz, e608160, fpa_monadic),
+ CM(lgn,d, e608180, fpa_monadic),
+ CM(lgn,dp, e6081a0, fpa_monadic),
+ CM(lgn,dm, e6081c0, fpa_monadic),
+ CM(lgn,dz, e6081e0, fpa_monadic),
+ CM(lgn,e, e688100, fpa_monadic),
+ CM(lgn,ep, e688120, fpa_monadic),
+ CM(lgn,em, e688140, fpa_monadic),
+ CM(lgn,ez, e688160, fpa_monadic),
- {"exps", 0xee708100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expsp", 0xee708120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expsm", 0xee708140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expsz", 0xee708160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expd", 0xee708180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expdp", 0xee7081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expdm", 0xee7081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expdz", 0xee7081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expe", 0xee788100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expep", 0xee788120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expem", 0xee788140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"expdz", 0xee788160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(exp,s, e708100, fpa_monadic),
+ CM(exp,sp, e708120, fpa_monadic),
+ CM(exp,sm, e708140, fpa_monadic),
+ CM(exp,sz, e708160, fpa_monadic),
+ CM(exp,d, e708180, fpa_monadic),
+ CM(exp,dp, e7081a0, fpa_monadic),
+ CM(exp,dm, e7081c0, fpa_monadic),
+ CM(exp,dz, e7081e0, fpa_monadic),
+ CM(exp,e, e788100, fpa_monadic),
+ CM(exp,ep, e788120, fpa_monadic),
+ CM(exp,em, e788140, fpa_monadic),
+ CM(exp,dz, e788160, fpa_monadic),
- {"sins", 0xee808100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sinsp", 0xee808120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sinsm", 0xee808140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sinsz", 0xee808160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sind", 0xee808180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sindp", 0xee8081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sindm", 0xee8081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sindz", 0xee8081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sine", 0xee888100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sinep", 0xee888120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sinem", 0xee888140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"sinez", 0xee888160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(sin,s, e808100, fpa_monadic),
+ CM(sin,sp, e808120, fpa_monadic),
+ CM(sin,sm, e808140, fpa_monadic),
+ CM(sin,sz, e808160, fpa_monadic),
+ CM(sin,d, e808180, fpa_monadic),
+ CM(sin,dp, e8081a0, fpa_monadic),
+ CM(sin,dm, e8081c0, fpa_monadic),
+ CM(sin,dz, e8081e0, fpa_monadic),
+ CM(sin,e, e888100, fpa_monadic),
+ CM(sin,ep, e888120, fpa_monadic),
+ CM(sin,em, e888140, fpa_monadic),
+ CM(sin,ez, e888160, fpa_monadic),
- {"coss", 0xee908100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cossp", 0xee908120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cossm", 0xee908140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cossz", 0xee908160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cosd", 0xee908180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cosdp", 0xee9081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cosdm", 0xee9081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cosdz", 0xee9081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cose", 0xee988100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cosep", 0xee988120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cosem", 0xee988140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"cosez", 0xee988160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(cos,s, e908100, fpa_monadic),
+ CM(cos,sp, e908120, fpa_monadic),
+ CM(cos,sm, e908140, fpa_monadic),
+ CM(cos,sz, e908160, fpa_monadic),
+ CM(cos,d, e908180, fpa_monadic),
+ CM(cos,dp, e9081a0, fpa_monadic),
+ CM(cos,dm, e9081c0, fpa_monadic),
+ CM(cos,dz, e9081e0, fpa_monadic),
+ CM(cos,e, e988100, fpa_monadic),
+ CM(cos,ep, e988120, fpa_monadic),
+ CM(cos,em, e988140, fpa_monadic),
+ CM(cos,ez, e988160, fpa_monadic),
- {"tans", 0xeea08100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tansp", 0xeea08120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tansm", 0xeea08140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tansz", 0xeea08160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tand", 0xeea08180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tandp", 0xeea081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tandm", 0xeea081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tandz", 0xeea081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tane", 0xeea88100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tanep", 0xeea88120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tanem", 0xeea88140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"tanez", 0xeea88160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(tan,s, ea08100, fpa_monadic),
+ CM(tan,sp, ea08120, fpa_monadic),
+ CM(tan,sm, ea08140, fpa_monadic),
+ CM(tan,sz, ea08160, fpa_monadic),
+ CM(tan,d, ea08180, fpa_monadic),
+ CM(tan,dp, ea081a0, fpa_monadic),
+ CM(tan,dm, ea081c0, fpa_monadic),
+ CM(tan,dz, ea081e0, fpa_monadic),
+ CM(tan,e, ea88100, fpa_monadic),
+ CM(tan,ep, ea88120, fpa_monadic),
+ CM(tan,em, ea88140, fpa_monadic),
+ CM(tan,ez, ea88160, fpa_monadic),
- {"asns", 0xeeb08100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asnsp", 0xeeb08120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asnsm", 0xeeb08140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asnsz", 0xeeb08160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asnd", 0xeeb08180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asndp", 0xeeb081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asndm", 0xeeb081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asndz", 0xeeb081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asne", 0xeeb88100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asnep", 0xeeb88120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asnem", 0xeeb88140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"asnez", 0xeeb88160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(asn,s, eb08100, fpa_monadic),
+ CM(asn,sp, eb08120, fpa_monadic),
+ CM(asn,sm, eb08140, fpa_monadic),
+ CM(asn,sz, eb08160, fpa_monadic),
+ CM(asn,d, eb08180, fpa_monadic),
+ CM(asn,dp, eb081a0, fpa_monadic),
+ CM(asn,dm, eb081c0, fpa_monadic),
+ CM(asn,dz, eb081e0, fpa_monadic),
+ CM(asn,e, eb88100, fpa_monadic),
+ CM(asn,ep, eb88120, fpa_monadic),
+ CM(asn,em, eb88140, fpa_monadic),
+ CM(asn,ez, eb88160, fpa_monadic),
- {"acss", 0xeec08100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acssp", 0xeec08120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acssm", 0xeec08140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acssz", 0xeec08160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acsd", 0xeec08180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acsdp", 0xeec081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acsdm", 0xeec081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acsdz", 0xeec081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acse", 0xeec88100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acsep", 0xeec88120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acsem", 0xeec88140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"acsez", 0xeec88160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(acs,s, ec08100, fpa_monadic),
+ CM(acs,sp, ec08120, fpa_monadic),
+ CM(acs,sm, ec08140, fpa_monadic),
+ CM(acs,sz, ec08160, fpa_monadic),
+ CM(acs,d, ec08180, fpa_monadic),
+ CM(acs,dp, ec081a0, fpa_monadic),
+ CM(acs,dm, ec081c0, fpa_monadic),
+ CM(acs,dz, ec081e0, fpa_monadic),
+ CM(acs,e, ec88100, fpa_monadic),
+ CM(acs,ep, ec88120, fpa_monadic),
+ CM(acs,em, ec88140, fpa_monadic),
+ CM(acs,ez, ec88160, fpa_monadic),
- {"atns", 0xeed08100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atnsp", 0xeed08120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atnsm", 0xeed08140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atnsz", 0xeed08160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atnd", 0xeed08180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atndp", 0xeed081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atndm", 0xeed081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atndz", 0xeed081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atne", 0xeed88100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atnep", 0xeed88120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atnem", 0xeed88140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"atnez", 0xeed88160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(atn,s, ed08100, fpa_monadic),
+ CM(atn,sp, ed08120, fpa_monadic),
+ CM(atn,sm, ed08140, fpa_monadic),
+ CM(atn,sz, ed08160, fpa_monadic),
+ CM(atn,d, ed08180, fpa_monadic),
+ CM(atn,dp, ed081a0, fpa_monadic),
+ CM(atn,dm, ed081c0, fpa_monadic),
+ CM(atn,dz, ed081e0, fpa_monadic),
+ CM(atn,e, ed88100, fpa_monadic),
+ CM(atn,ep, ed88120, fpa_monadic),
+ CM(atn,em, ed88140, fpa_monadic),
+ CM(atn,ez, ed88160, fpa_monadic),
- {"urds", 0xeee08100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urdsp", 0xeee08120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urdsm", 0xeee08140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urdsz", 0xeee08160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urdd", 0xeee08180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urddp", 0xeee081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urddm", 0xeee081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urddz", 0xeee081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urde", 0xeee88100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urdep", 0xeee88120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urdem", 0xeee88140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"urdez", 0xeee88160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(urd,s, ee08100, fpa_monadic),
+ CM(urd,sp, ee08120, fpa_monadic),
+ CM(urd,sm, ee08140, fpa_monadic),
+ CM(urd,sz, ee08160, fpa_monadic),
+ CM(urd,d, ee08180, fpa_monadic),
+ CM(urd,dp, ee081a0, fpa_monadic),
+ CM(urd,dm, ee081c0, fpa_monadic),
+ CM(urd,dz, ee081e0, fpa_monadic),
+ CM(urd,e, ee88100, fpa_monadic),
+ CM(urd,ep, ee88120, fpa_monadic),
+ CM(urd,em, ee88140, fpa_monadic),
+ CM(urd,ez, ee88160, fpa_monadic),
- {"nrms", 0xeef08100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmsp", 0xeef08120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmsm", 0xeef08140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmsz", 0xeef08160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmd", 0xeef08180, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmdp", 0xeef081a0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmdm", 0xeef081c0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmdz", 0xeef081e0, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrme", 0xeef88100, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmep", 0xeef88120, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmem", 0xeef88140, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
- {"nrmez", 0xeef88160, 3, FPU_FPA_EXT_V1, do_fpa_monadic},
+ CM(nrm,s, ef08100, fpa_monadic),
+ CM(nrm,sp, ef08120, fpa_monadic),
+ CM(nrm,sm, ef08140, fpa_monadic),
+ CM(nrm,sz, ef08160, fpa_monadic),
+ CM(nrm,d, ef08180, fpa_monadic),
+ CM(nrm,dp, ef081a0, fpa_monadic),
+ CM(nrm,dm, ef081c0, fpa_monadic),
+ CM(nrm,dz, ef081e0, fpa_monadic),
+ CM(nrm,e, ef88100, fpa_monadic),
+ CM(nrm,ep, ef88120, fpa_monadic),
+ CM(nrm,em, ef88140, fpa_monadic),
+ CM(nrm,ez, ef88160, fpa_monadic),
- {"adfs", 0xee000100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfsp", 0xee000120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfsm", 0xee000140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfsz", 0xee000160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfd", 0xee000180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfdp", 0xee0001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfdm", 0xee0001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfdz", 0xee0001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfe", 0xee080100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfep", 0xee080120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfem", 0xee080140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"adfez", 0xee080160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(adf,s, e000100, fpa_dyadic),
+ CM(adf,sp, e000120, fpa_dyadic),
+ CM(adf,sm, e000140, fpa_dyadic),
+ CM(adf,sz, e000160, fpa_dyadic),
+ CM(adf,d, e000180, fpa_dyadic),
+ CM(adf,dp, e0001a0, fpa_dyadic),
+ CM(adf,dm, e0001c0, fpa_dyadic),
+ CM(adf,dz, e0001e0, fpa_dyadic),
+ CM(adf,e, e080100, fpa_dyadic),
+ CM(adf,ep, e080120, fpa_dyadic),
+ CM(adf,em, e080140, fpa_dyadic),
+ CM(adf,ez, e080160, fpa_dyadic),
- {"sufs", 0xee200100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufsp", 0xee200120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufsm", 0xee200140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufsz", 0xee200160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufd", 0xee200180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufdp", 0xee2001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufdm", 0xee2001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufdz", 0xee2001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufe", 0xee280100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufep", 0xee280120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufem", 0xee280140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"sufez", 0xee280160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(suf,s, e200100, fpa_dyadic),
+ CM(suf,sp, e200120, fpa_dyadic),
+ CM(suf,sm, e200140, fpa_dyadic),
+ CM(suf,sz, e200160, fpa_dyadic),
+ CM(suf,d, e200180, fpa_dyadic),
+ CM(suf,dp, e2001a0, fpa_dyadic),
+ CM(suf,dm, e2001c0, fpa_dyadic),
+ CM(suf,dz, e2001e0, fpa_dyadic),
+ CM(suf,e, e280100, fpa_dyadic),
+ CM(suf,ep, e280120, fpa_dyadic),
+ CM(suf,em, e280140, fpa_dyadic),
+ CM(suf,ez, e280160, fpa_dyadic),
- {"rsfs", 0xee300100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfsp", 0xee300120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfsm", 0xee300140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfsz", 0xee300160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfd", 0xee300180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfdp", 0xee3001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfdm", 0xee3001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfdz", 0xee3001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfe", 0xee380100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfep", 0xee380120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfem", 0xee380140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rsfez", 0xee380160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(rsf,s, e300100, fpa_dyadic),
+ CM(rsf,sp, e300120, fpa_dyadic),
+ CM(rsf,sm, e300140, fpa_dyadic),
+ CM(rsf,sz, e300160, fpa_dyadic),
+ CM(rsf,d, e300180, fpa_dyadic),
+ CM(rsf,dp, e3001a0, fpa_dyadic),
+ CM(rsf,dm, e3001c0, fpa_dyadic),
+ CM(rsf,dz, e3001e0, fpa_dyadic),
+ CM(rsf,e, e380100, fpa_dyadic),
+ CM(rsf,ep, e380120, fpa_dyadic),
+ CM(rsf,em, e380140, fpa_dyadic),
+ CM(rsf,ez, e380160, fpa_dyadic),
- {"mufs", 0xee100100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufsp", 0xee100120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufsm", 0xee100140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufsz", 0xee100160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufd", 0xee100180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufdp", 0xee1001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufdm", 0xee1001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufdz", 0xee1001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufe", 0xee180100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufep", 0xee180120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufem", 0xee180140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"mufez", 0xee180160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(muf,s, e100100, fpa_dyadic),
+ CM(muf,sp, e100120, fpa_dyadic),
+ CM(muf,sm, e100140, fpa_dyadic),
+ CM(muf,sz, e100160, fpa_dyadic),
+ CM(muf,d, e100180, fpa_dyadic),
+ CM(muf,dp, e1001a0, fpa_dyadic),
+ CM(muf,dm, e1001c0, fpa_dyadic),
+ CM(muf,dz, e1001e0, fpa_dyadic),
+ CM(muf,e, e180100, fpa_dyadic),
+ CM(muf,ep, e180120, fpa_dyadic),
+ CM(muf,em, e180140, fpa_dyadic),
+ CM(muf,ez, e180160, fpa_dyadic),
- {"dvfs", 0xee400100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfsp", 0xee400120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfsm", 0xee400140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfsz", 0xee400160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfd", 0xee400180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfdp", 0xee4001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfdm", 0xee4001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfdz", 0xee4001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfe", 0xee480100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfep", 0xee480120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfem", 0xee480140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"dvfez", 0xee480160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(dvf,s, e400100, fpa_dyadic),
+ CM(dvf,sp, e400120, fpa_dyadic),
+ CM(dvf,sm, e400140, fpa_dyadic),
+ CM(dvf,sz, e400160, fpa_dyadic),
+ CM(dvf,d, e400180, fpa_dyadic),
+ CM(dvf,dp, e4001a0, fpa_dyadic),
+ CM(dvf,dm, e4001c0, fpa_dyadic),
+ CM(dvf,dz, e4001e0, fpa_dyadic),
+ CM(dvf,e, e480100, fpa_dyadic),
+ CM(dvf,ep, e480120, fpa_dyadic),
+ CM(dvf,em, e480140, fpa_dyadic),
+ CM(dvf,ez, e480160, fpa_dyadic),
- {"rdfs", 0xee500100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfsp", 0xee500120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfsm", 0xee500140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfsz", 0xee500160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfd", 0xee500180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfdp", 0xee5001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfdm", 0xee5001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfdz", 0xee5001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfe", 0xee580100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfep", 0xee580120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfem", 0xee580140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rdfez", 0xee580160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(rdf,s, e500100, fpa_dyadic),
+ CM(rdf,sp, e500120, fpa_dyadic),
+ CM(rdf,sm, e500140, fpa_dyadic),
+ CM(rdf,sz, e500160, fpa_dyadic),
+ CM(rdf,d, e500180, fpa_dyadic),
+ CM(rdf,dp, e5001a0, fpa_dyadic),
+ CM(rdf,dm, e5001c0, fpa_dyadic),
+ CM(rdf,dz, e5001e0, fpa_dyadic),
+ CM(rdf,e, e580100, fpa_dyadic),
+ CM(rdf,ep, e580120, fpa_dyadic),
+ CM(rdf,em, e580140, fpa_dyadic),
+ CM(rdf,ez, e580160, fpa_dyadic),
- {"pows", 0xee600100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powsp", 0xee600120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powsm", 0xee600140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powsz", 0xee600160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powd", 0xee600180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powdp", 0xee6001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powdm", 0xee6001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powdz", 0xee6001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powe", 0xee680100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powep", 0xee680120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powem", 0xee680140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"powez", 0xee680160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(pow,s, e600100, fpa_dyadic),
+ CM(pow,sp, e600120, fpa_dyadic),
+ CM(pow,sm, e600140, fpa_dyadic),
+ CM(pow,sz, e600160, fpa_dyadic),
+ CM(pow,d, e600180, fpa_dyadic),
+ CM(pow,dp, e6001a0, fpa_dyadic),
+ CM(pow,dm, e6001c0, fpa_dyadic),
+ CM(pow,dz, e6001e0, fpa_dyadic),
+ CM(pow,e, e680100, fpa_dyadic),
+ CM(pow,ep, e680120, fpa_dyadic),
+ CM(pow,em, e680140, fpa_dyadic),
+ CM(pow,ez, e680160, fpa_dyadic),
- {"rpws", 0xee700100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwsp", 0xee700120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwsm", 0xee700140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwsz", 0xee700160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwd", 0xee700180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwdp", 0xee7001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwdm", 0xee7001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwdz", 0xee7001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwe", 0xee780100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwep", 0xee780120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwem", 0xee780140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rpwez", 0xee780160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(rpw,s, e700100, fpa_dyadic),
+ CM(rpw,sp, e700120, fpa_dyadic),
+ CM(rpw,sm, e700140, fpa_dyadic),
+ CM(rpw,sz, e700160, fpa_dyadic),
+ CM(rpw,d, e700180, fpa_dyadic),
+ CM(rpw,dp, e7001a0, fpa_dyadic),
+ CM(rpw,dm, e7001c0, fpa_dyadic),
+ CM(rpw,dz, e7001e0, fpa_dyadic),
+ CM(rpw,e, e780100, fpa_dyadic),
+ CM(rpw,ep, e780120, fpa_dyadic),
+ CM(rpw,em, e780140, fpa_dyadic),
+ CM(rpw,ez, e780160, fpa_dyadic),
- {"rmfs", 0xee800100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfsp", 0xee800120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfsm", 0xee800140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfsz", 0xee800160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfd", 0xee800180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfdp", 0xee8001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfdm", 0xee8001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfdz", 0xee8001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfe", 0xee880100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfep", 0xee880120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfem", 0xee880140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"rmfez", 0xee880160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(rmf,s, e800100, fpa_dyadic),
+ CM(rmf,sp, e800120, fpa_dyadic),
+ CM(rmf,sm, e800140, fpa_dyadic),
+ CM(rmf,sz, e800160, fpa_dyadic),
+ CM(rmf,d, e800180, fpa_dyadic),
+ CM(rmf,dp, e8001a0, fpa_dyadic),
+ CM(rmf,dm, e8001c0, fpa_dyadic),
+ CM(rmf,dz, e8001e0, fpa_dyadic),
+ CM(rmf,e, e880100, fpa_dyadic),
+ CM(rmf,ep, e880120, fpa_dyadic),
+ CM(rmf,em, e880140, fpa_dyadic),
+ CM(rmf,ez, e880160, fpa_dyadic),
- {"fmls", 0xee900100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmlsp", 0xee900120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmlsm", 0xee900140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmlsz", 0xee900160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmld", 0xee900180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmldp", 0xee9001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmldm", 0xee9001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmldz", 0xee9001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmle", 0xee980100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmlep", 0xee980120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmlem", 0xee980140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fmlez", 0xee980160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(fml,s, e900100, fpa_dyadic),
+ CM(fml,sp, e900120, fpa_dyadic),
+ CM(fml,sm, e900140, fpa_dyadic),
+ CM(fml,sz, e900160, fpa_dyadic),
+ CM(fml,d, e900180, fpa_dyadic),
+ CM(fml,dp, e9001a0, fpa_dyadic),
+ CM(fml,dm, e9001c0, fpa_dyadic),
+ CM(fml,dz, e9001e0, fpa_dyadic),
+ CM(fml,e, e980100, fpa_dyadic),
+ CM(fml,ep, e980120, fpa_dyadic),
+ CM(fml,em, e980140, fpa_dyadic),
+ CM(fml,ez, e980160, fpa_dyadic),
- {"fdvs", 0xeea00100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvsp", 0xeea00120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvsm", 0xeea00140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvsz", 0xeea00160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvd", 0xeea00180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvdp", 0xeea001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvdm", 0xeea001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvdz", 0xeea001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdve", 0xeea80100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvep", 0xeea80120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvem", 0xeea80140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"fdvez", 0xeea80160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(fdv,s, ea00100, fpa_dyadic),
+ CM(fdv,sp, ea00120, fpa_dyadic),
+ CM(fdv,sm, ea00140, fpa_dyadic),
+ CM(fdv,sz, ea00160, fpa_dyadic),
+ CM(fdv,d, ea00180, fpa_dyadic),
+ CM(fdv,dp, ea001a0, fpa_dyadic),
+ CM(fdv,dm, ea001c0, fpa_dyadic),
+ CM(fdv,dz, ea001e0, fpa_dyadic),
+ CM(fdv,e, ea80100, fpa_dyadic),
+ CM(fdv,ep, ea80120, fpa_dyadic),
+ CM(fdv,em, ea80140, fpa_dyadic),
+ CM(fdv,ez, ea80160, fpa_dyadic),
- {"frds", 0xeeb00100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frdsp", 0xeeb00120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frdsm", 0xeeb00140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frdsz", 0xeeb00160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frdd", 0xeeb00180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frddp", 0xeeb001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frddm", 0xeeb001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frddz", 0xeeb001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frde", 0xeeb80100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frdep", 0xeeb80120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frdem", 0xeeb80140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"frdez", 0xeeb80160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(frd,s, eb00100, fpa_dyadic),
+ CM(frd,sp, eb00120, fpa_dyadic),
+ CM(frd,sm, eb00140, fpa_dyadic),
+ CM(frd,sz, eb00160, fpa_dyadic),
+ CM(frd,d, eb00180, fpa_dyadic),
+ CM(frd,dp, eb001a0, fpa_dyadic),
+ CM(frd,dm, eb001c0, fpa_dyadic),
+ CM(frd,dz, eb001e0, fpa_dyadic),
+ CM(frd,e, eb80100, fpa_dyadic),
+ CM(frd,ep, eb80120, fpa_dyadic),
+ CM(frd,em, eb80140, fpa_dyadic),
+ CM(frd,ez, eb80160, fpa_dyadic),
- {"pols", 0xeec00100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"polsp", 0xeec00120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"polsm", 0xeec00140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"polsz", 0xeec00160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"pold", 0xeec00180, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"poldp", 0xeec001a0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"poldm", 0xeec001c0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"poldz", 0xeec001e0, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"pole", 0xeec80100, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"polep", 0xeec80120, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"polem", 0xeec80140, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
- {"polez", 0xeec80160, 3, FPU_FPA_EXT_V1, do_fpa_dyadic},
+ CM(pol,s, ec00100, fpa_dyadic),
+ CM(pol,sp, ec00120, fpa_dyadic),
+ CM(pol,sm, ec00140, fpa_dyadic),
+ CM(pol,sz, ec00160, fpa_dyadic),
+ CM(pol,d, ec00180, fpa_dyadic),
+ CM(pol,dp, ec001a0, fpa_dyadic),
+ CM(pol,dm, ec001c0, fpa_dyadic),
+ CM(pol,dz, ec001e0, fpa_dyadic),
+ CM(pol,e, ec80100, fpa_dyadic),
+ CM(pol,ep, ec80120, fpa_dyadic),
+ CM(pol,em, ec80140, fpa_dyadic),
+ CM(pol,ez, ec80160, fpa_dyadic),
- {"cmf", 0xee90f110, 3, FPU_FPA_EXT_V1, do_fpa_cmp},
- {"cmfe", 0xeed0f110, 3, FPU_FPA_EXT_V1, do_fpa_cmp},
- {"cnf", 0xeeb0f110, 3, FPU_FPA_EXT_V1, do_fpa_cmp},
- {"cnfe", 0xeef0f110, 3, FPU_FPA_EXT_V1, do_fpa_cmp},
+ CE(cmf, e90f110, fpa_cmp),
+ CM(cmf,e, ed0f110, fpa_cmp),
+ CE(cnf, eb0f110, fpa_cmp),
+ CM(cnf,e, ef0f110, fpa_cmp),
/* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should
not be an optional suffix, but part of the instruction. To be
compatible, we accept either. */
- {"cmfe", 0xeed0f110, 4, FPU_FPA_EXT_V1, do_fpa_cmp},
- {"cnfe", 0xeef0f110, 4, FPU_FPA_EXT_V1, do_fpa_cmp},
+ CE(cmfe, ed0f110, fpa_cmp),
+ CE(cnfe, ef0f110, fpa_cmp),
- {"flts", 0xee000110, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltsp", 0xee000130, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltsm", 0xee000150, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltsz", 0xee000170, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltd", 0xee000190, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltdp", 0xee0001b0, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltdm", 0xee0001d0, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltdz", 0xee0001f0, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"flte", 0xee080110, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltep", 0xee080130, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltem", 0xee080150, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
- {"fltez", 0xee080170, 3, FPU_FPA_EXT_V1, do_fpa_from_reg},
+ CM(flt,s, e000110, fpa_from_reg),
+ CM(flt,sp, e000130, fpa_from_reg),
+ CM(flt,sm, e000150, fpa_from_reg),
+ CM(flt,sz, e000170, fpa_from_reg),
+ CM(flt,d, e000190, fpa_from_reg),
+ CM(flt,dp, e0001b0, fpa_from_reg),
+ CM(flt,dm, e0001d0, fpa_from_reg),
+ CM(flt,dz, e0001f0, fpa_from_reg),
+ CM(flt,e, e080110, fpa_from_reg),
+ CM(flt,ep, e080130, fpa_from_reg),
+ CM(flt,em, e080150, fpa_from_reg),
+ CM(flt,ez, e080170, fpa_from_reg),
/* The implementation of the FIX instruction is broken on some
assemblers, in that it accepts a precision specifier as well as a
rounding specifier, despite the fact that this is meaningless.
To be more compatible, we accept it as well, though of course it
does not set any bits. */
- {"fix", 0xee100110, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixp", 0xee100130, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixm", 0xee100150, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixz", 0xee100170, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixsp", 0xee100130, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixsm", 0xee100150, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixsz", 0xee100170, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixdp", 0xee100130, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixdm", 0xee100150, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixdz", 0xee100170, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixep", 0xee100130, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixem", 0xee100150, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
- {"fixez", 0xee100170, 3, FPU_FPA_EXT_V1, do_fpa_to_reg},
+ CE(fix, e100110, fpa_to_reg),
+ CM(fix,p, e100130, fpa_to_reg),
+ CM(fix,m, e100150, fpa_to_reg),
+ CM(fix,z, e100170, fpa_to_reg),
+ CM(fix,sp, e100130, fpa_to_reg),
+ CM(fix,sm, e100150, fpa_to_reg),
+ CM(fix,sz, e100170, fpa_to_reg),
+ CM(fix,dp, e100130, fpa_to_reg),
+ CM(fix,dm, e100150, fpa_to_reg),
+ CM(fix,dz, e100170, fpa_to_reg),
+ CM(fix,ep, e100130, fpa_to_reg),
+ CM(fix,em, e100150, fpa_to_reg),
+ CM(fix,ez, e100170, fpa_to_reg),
/* Instructions that were new with the real FPA, call them V2. */
- {"lfm", 0xec100200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
- {"lfmfd", 0xec900200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
- {"lfmea", 0xed100200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
- {"sfm", 0xec000200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
- {"sfmfd", 0xed000200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
- {"sfmea", 0xec800200, 3, FPU_FPA_EXT_V2, do_fpa_ldmstm},
+#undef ARM_VARIANT
+#define ARM_VARIANT FPU_FPA_EXT_V2
+ CE(lfm, c100200, fpa_ldmstm),
+ CM(lfm,fd, c900200, fpa_ldmstm),
+ CM(lfm,ea, d100200, fpa_ldmstm),
+ CE(sfm, c000200, fpa_ldmstm),
+ CM(sfm,fd, d000200, fpa_ldmstm),
+ CM(sfm,ea, c800200, fpa_ldmstm),
- /* VFP V1xD (single precision). */
+#undef ARM_VARIANT
+#define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
/* Moves and type conversions. */
- {"fcpys", 0xeeb00a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"fmrs", 0xee100a10, 4, FPU_VFP_EXT_V1xD, do_vfp_reg_from_sp},
- {"fmsr", 0xee000a10, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_from_reg},
- {"fmstat", 0xeef1fa10, 6, FPU_VFP_EXT_V1xD, do_empty},
- {"fsitos", 0xeeb80ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"fuitos", 0xeeb80a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"ftosis", 0xeebd0a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"ftosizs", 0xeebd0ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"ftouis", 0xeebc0a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"ftouizs", 0xeebc0ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"fmrx", 0xeef00a10, 4, FPU_VFP_EXT_V1xD, do_vfp_reg_from_ctrl},
- {"fmxr", 0xeee00a10, 4, FPU_VFP_EXT_V1xD, do_vfp_ctrl_from_reg},
+ CE(fcpys, eb00a40, vfp_sp_monadic),
+ CE(fmrs, e100a10, vfp_reg_from_sp),
+ CE(fmsr, e000a10, vfp_sp_from_reg),
+ CE(fmstat, ef1fa10, empty),
+ CE(fsitos, eb80ac0, vfp_sp_monadic),
+ CE(fuitos, eb80a40, vfp_sp_monadic),
+ CE(ftosis, ebd0a40, vfp_sp_monadic),
+ CE(ftosizs, ebd0ac0, vfp_sp_monadic),
+ CE(ftouis, ebc0a40, vfp_sp_monadic),
+ CE(ftouizs, ebc0ac0, vfp_sp_monadic),
+ CE(fmrx, ef00a10, vfp_reg_from_ctrl),
+ CE(fmxr, ee00a10, vfp_ctrl_from_reg),
/* Memory operations. */
- {"flds", 0xed100a00, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_ldst},
- {"fsts", 0xed000a00, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_ldst},
- {"fldmias", 0xec900a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
- {"fldmfds", 0xec900a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
- {"fldmdbs", 0xed300a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
- {"fldmeas", 0xed300a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
- {"fldmiax", 0xec900b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
- {"fldmfdx", 0xec900b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
- {"fldmdbx", 0xed300b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
- {"fldmeax", 0xed300b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
- {"fstmias", 0xec800a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
- {"fstmeas", 0xec800a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
- {"fstmdbs", 0xed200a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
- {"fstmfds", 0xed200a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
- {"fstmiax", 0xec800b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
- {"fstmeax", 0xec800b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
- {"fstmdbx", 0xed200b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
- {"fstmfdx", 0xed200b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
+ CE(flds, d100a00, vfp_sp_ldst),
+ CE(fsts, d000a00, vfp_sp_ldst),
+ CE(fldmias, c900a00, vfp_sp_ldstmia),
+ CE(fldmfds, c900a00, vfp_sp_ldstmia),
+ CE(fldmdbs, d300a00, vfp_sp_ldstmdb),
+ CE(fldmeas, d300a00, vfp_sp_ldstmdb),
+ CE(fldmiax, c900b00, vfp_xp_ldstmia),
+ CE(fldmfdx, c900b00, vfp_xp_ldstmia),
+ CE(fldmdbx, d300b00, vfp_xp_ldstmdb),
+ CE(fldmeax, d300b00, vfp_xp_ldstmdb),
+ CE(fstmias, c800a00, vfp_sp_ldstmia),
+ CE(fstmeas, c800a00, vfp_sp_ldstmia),
+ CE(fstmdbs, d200a00, vfp_sp_ldstmdb),
+ CE(fstmfds, d200a00, vfp_sp_ldstmdb),
+ CE(fstmiax, c800b00, vfp_xp_ldstmia),
+ CE(fstmeax, c800b00, vfp_xp_ldstmia),
+ CE(fstmdbx, d200b00, vfp_xp_ldstmdb),
+ CE(fstmfdx, d200b00, vfp_xp_ldstmdb),
/* Monadic operations. */
- {"fabss", 0xeeb00ac0, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"fnegs", 0xeeb10a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"fsqrts", 0xeeb10ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
+ CE(fabss, eb00ac0, vfp_sp_monadic),
+ CE(fnegs, eb10a40, vfp_sp_monadic),
+ CE(fsqrts, eb10ac0, vfp_sp_monadic),
/* Dyadic operations. */
- {"fadds", 0xee300a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fsubs", 0xee300a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fmuls", 0xee200a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fdivs", 0xee800a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fmacs", 0xee000a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fmscs", 0xee100a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fnmuls", 0xee200a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fnmacs", 0xee000a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
- {"fnmscs", 0xee100a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+ CE(fadds, e300a00, vfp_sp_dyadic),
+ CE(fsubs, e300a40, vfp_sp_dyadic),
+ CE(fmuls, e200a00, vfp_sp_dyadic),
+ CE(fdivs, e800a00, vfp_sp_dyadic),
+ CE(fmacs, e000a00, vfp_sp_dyadic),
+ CE(fmscs, e100a00, vfp_sp_dyadic),
+ CE(fnmuls, e200a40, vfp_sp_dyadic),
+ CE(fnmacs, e000a40, vfp_sp_dyadic),
+ CE(fnmscs, e100a40, vfp_sp_dyadic),
/* Comparisons. */
- {"fcmps", 0xeeb40a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"fcmpzs", 0xeeb50a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_compare_z},
- {"fcmpes", 0xeeb40ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
- {"fcmpezs", 0xeeb50ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_compare_z},
+ CE(fcmps, eb40a40, vfp_sp_monadic),
+ CE(fcmpzs, eb50a40, vfp_sp_compare_z),
+ CE(fcmpes, eb40ac0, vfp_sp_monadic),
+ CE(fcmpezs, eb50ac0, vfp_sp_compare_z),
- /* VFP V1 (Double precision). */
+#undef ARM_VARIANT
+#define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
/* Moves and type conversions. */
- {"fcpyd", 0xeeb00b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
- {"fcvtds", 0xeeb70ac0, 6, FPU_VFP_EXT_V1, do_vfp_dp_sp_cvt},
- {"fcvtsd", 0xeeb70bc0, 6, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
- {"fmdhr", 0xee200b10, 5, FPU_VFP_EXT_V1, do_vfp_dp_from_reg},
- {"fmdlr", 0xee000b10, 5, FPU_VFP_EXT_V1, do_vfp_dp_from_reg},
- {"fmrdh", 0xee300b10, 5, FPU_VFP_EXT_V1, do_vfp_reg_from_dp},
- {"fmrdl", 0xee100b10, 5, FPU_VFP_EXT_V1, do_vfp_reg_from_dp},
- {"fsitod", 0xeeb80bc0, 6, FPU_VFP_EXT_V1, do_vfp_dp_sp_cvt},
- {"fuitod", 0xeeb80b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_sp_cvt},
- {"ftosid", 0xeebd0b40, 6, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
- {"ftosizd", 0xeebd0bc0, 7, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
- {"ftouid", 0xeebc0b40, 6, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
- {"ftouizd", 0xeebc0bc0, 7, FPU_VFP_EXT_V1, do_vfp_sp_dp_cvt},
+ CE(fcpyd, eb00b40, vfp_dp_monadic),
+ CE(fcvtds, eb70ac0, vfp_dp_sp_cvt),
+ CE(fcvtsd, eb70bc0, vfp_sp_dp_cvt),
+ CE(fmdhr, e200b10, vfp_dp_from_reg),
+ CE(fmdlr, e000b10, vfp_dp_from_reg),
+ CE(fmrdh, e300b10, vfp_reg_from_dp),
+ CE(fmrdl, e100b10, vfp_reg_from_dp),
+ CE(fsitod, eb80bc0, vfp_dp_sp_cvt),
+ CE(fuitod, eb80b40, vfp_dp_sp_cvt),
+ CE(ftosid, ebd0b40, vfp_sp_dp_cvt),
+ CE(ftosizd, ebd0bc0, vfp_sp_dp_cvt),
+ CE(ftouid, ebc0b40, vfp_sp_dp_cvt),
+ CE(ftouizd, ebc0bc0, vfp_sp_dp_cvt),
/* Memory operations. */
- {"fldd", 0xed100b00, 4, FPU_VFP_EXT_V1, do_vfp_dp_ldst},
- {"fstd", 0xed000b00, 4, FPU_VFP_EXT_V1, do_vfp_dp_ldst},
- {"fldmiad", 0xec900b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
- {"fldmfdd", 0xec900b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
- {"fldmdbd", 0xed300b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
- {"fldmead", 0xed300b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
- {"fstmiad", 0xec800b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
- {"fstmead", 0xec800b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmia},
- {"fstmdbd", 0xed200b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
- {"fstmfdd", 0xed200b00, 7, FPU_VFP_EXT_V1, do_vfp_dp_ldstmdb},
+ CE(fldd, d100b00, vfp_dp_ldst),
+ CE(fstd, d000b00, vfp_dp_ldst),
+ CE(fldmiad, c900b00, vfp_dp_ldstmia),
+ CE(fldmfdd, c900b00, vfp_dp_ldstmia),
+ CE(fldmdbd, d300b00, vfp_dp_ldstmdb),
+ CE(fldmead, d300b00, vfp_dp_ldstmdb),
+ CE(fstmiad, c800b00, vfp_dp_ldstmia),
+ CE(fstmead, c800b00, vfp_dp_ldstmia),
+ CE(fstmdbd, d200b00, vfp_dp_ldstmdb),
+ CE(fstmfdd, d200b00, vfp_dp_ldstmdb),
/* Monadic operations. */
- {"fabsd", 0xeeb00bc0, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
- {"fnegd", 0xeeb10b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
- {"fsqrtd", 0xeeb10bc0, 6, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
+ CE(fabsd, eb00bc0, vfp_dp_monadic),
+ CE(fnegd, eb10b40, vfp_dp_monadic),
+ CE(fsqrtd, eb10bc0, vfp_dp_monadic),
/* Dyadic operations. */
- {"faddd", 0xee300b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fsubd", 0xee300b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fmuld", 0xee200b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fdivd", 0xee800b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fmacd", 0xee000b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fmscd", 0xee100b00, 5, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fnmuld", 0xee200b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fnmacd", 0xee000b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
- {"fnmscd", 0xee100b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_dyadic},
+ CE(faddd, e300b00, vfp_dp_dyadic),
+ CE(fsubd, e300b40, vfp_dp_dyadic),
+ CE(fmuld, e200b00, vfp_dp_dyadic),
+ CE(fdivd, e800b00, vfp_dp_dyadic),
+ CE(fmacd, e000b00, vfp_dp_dyadic),
+ CE(fmscd, e100b00, vfp_dp_dyadic),
+ CE(fnmuld, e200b40, vfp_dp_dyadic),
+ CE(fnmacd, e000b40, vfp_dp_dyadic),
+ CE(fnmscd, e100b40, vfp_dp_dyadic),
/* Comparisons. */
- {"fcmpd", 0xeeb40b40, 5, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
- {"fcmpzd", 0xeeb50b40, 6, FPU_VFP_EXT_V1, do_vfp_dp_compare_z},
- {"fcmped", 0xeeb40bc0, 6, FPU_VFP_EXT_V1, do_vfp_dp_monadic},
- {"fcmpezd", 0xeeb50bc0, 7, FPU_VFP_EXT_V1, do_vfp_dp_compare_z},
+ CE(fcmpd, eb40b40, vfp_dp_monadic),
+ CE(fcmpzd, eb50b40, vfp_dp_compare_z),
+ CE(fcmped, eb40bc0, vfp_dp_monadic),
+ CE(fcmpezd, eb50bc0, vfp_dp_compare_z),
- /* VFP V2. */
- {"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp2_from_reg2},
- {"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_sp2},
- {"fmdrr", 0xec400b10, 5, FPU_VFP_EXT_V2, do_vfp_dp_from_reg2},
- {"fmrrd", 0xec500b10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_dp},
+#undef ARM_VARIANT
+#define ARM_VARIANT FPU_VFP_EXT_V2
+ CE(fmsrr, c400a10, vfp_sp2_from_reg2),
+ CE(fmrrs, c500a10, vfp_reg2_from_sp2),
+ CE(fmdrr, c400b10, vfp_dp_from_reg2),
+ CE(fmrrd, c500b10, vfp_reg2_from_dp),
- /* Intel XScale extensions to ARM V5 ISA. (All use CP0). */
- {"mia", 0xee200010, 3, ARM_CEXT_XSCALE, do_xsc_mia},
- {"miaph", 0xee280010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
- {"miabb", 0xee2c0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
- {"miabt", 0xee2d0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
- {"miatb", 0xee2e0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
- {"miatt", 0xee2f0010, 5, ARM_CEXT_XSCALE, do_xsc_mia},
- {"mar", 0xec400000, 3, ARM_CEXT_XSCALE, do_xsc_mar},
- {"mra", 0xec500000, 3, ARM_CEXT_XSCALE, do_xsc_mra},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
+ CE(mia, e200010, xsc_mia),
+ CE(miaph, e280010, xsc_mia),
+ CE(miabb, e2c0010, xsc_mia),
+ CE(miabt, e2d0010, xsc_mia),
+ CE(miatb, e2e0010, xsc_mia),
+ CE(miatt, e2f0010, xsc_mia),
+ CE(mar, c400000, xsc_mar),
+ CE(mra, c500000, xsc_mra),
- /* Intel Wireless MMX technology instructions. */
- {"tandcb", 0xee130130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandorc},
- {"tandch", 0xee530130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandorc},
- {"tandcw", 0xee930130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandorc},
- {"tbcstb", 0xee400010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
- {"tbcsth", 0xee400050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
- {"tbcstw", 0xee400090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
- {"textrcb", 0xee130170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
- {"textrch", 0xee530170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
- {"textrcw", 0xee930170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
- {"textrmub", 0xee100070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
- {"textrmuh", 0xee500070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
- {"textrmuw", 0xee900070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
- {"textrmsb", 0xee100078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
- {"textrmsh", 0xee500078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
- {"textrmsw", 0xee900078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
- {"tinsrb", 0xee600010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
- {"tinsrh", 0xee600050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
- {"tinsrw", 0xee600090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
- {"tmcr", 0xee000110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmcr},
- {"tmcrr", 0xec400000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmcrr},
- {"tmia", 0xee200010, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
- {"tmiaph", 0xee280010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
- {"tmiabb", 0xee2c0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
- {"tmiabt", 0xee2d0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
- {"tmiatb", 0xee2e0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
- {"tmiatt", 0xee2f0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
- {"tmovmskb", 0xee100030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
- {"tmovmskh", 0xee500030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
- {"tmovmskw", 0xee900030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
- {"tmrc", 0xee100110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmrc},
- {"tmrrc", 0xec500000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmrrc},
- {"torcb", 0xee130150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tandorc},
- {"torch", 0xee530150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tandorc},
- {"torcw", 0xee930150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tandorc},
- {"waccb", 0xee0001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wacch", 0xee4001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"waccw", 0xee8001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"waddbss", 0xee300180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddb", 0xee000180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddbus", 0xee100180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddhss", 0xee700180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddh", 0xee400180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddhus", 0xee500180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddwss", 0xeeb00180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddw", 0xee800180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waddwus", 0xee900180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"waligni", 0xee000020, 7, ARM_CEXT_IWMMXT, do_iwmmxt_waligni},
- {"walignr0", 0xee800020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"walignr1", 0xee900020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"walignr2", 0xeea00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"walignr3", 0xeeb00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wand", 0xee200000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wandn", 0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wavg2b", 0xee800000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wavg2br", 0xee900000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wavg2h", 0xeec00000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wavg2hr", 0xeed00000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpeqb", 0xee000060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpeqh", 0xee400060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpeqw", 0xee800060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpgtub", 0xee100060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpgtuh", 0xee500060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpgtuw", 0xee900060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpgtsb", 0xee300060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpgtsh", 0xee700060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wcmpgtsw", 0xeeb00060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wldrb", 0xec100000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldst},
- {"wldrh", 0xec500000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldst},
- {"wldrw", 0xec100100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldstw},
- {"wldrd", 0xec500100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldst},
- {"wmacs", 0xee600100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmacsz", 0xee700100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmacu", 0xee400100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmacuz", 0xee500100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmadds", 0xeea00100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmaddu", 0xee800100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmaxsb", 0xee200160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmaxsh", 0xee600160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmaxsw", 0xeea00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmaxub", 0xee000160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmaxuh", 0xee400160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmaxuw", 0xee800160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wminsb", 0xee300160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wminsh", 0xee700160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wminsw", 0xeeb00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wminub", 0xee100160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wminuh", 0xee500160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wminuw", 0xee900160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmov", 0xee000000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wmov},
- {"wmulsm", 0xee300100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmulsl", 0xee200100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmulum", 0xee100100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wmulul", 0xee000100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wor", 0xee000000, 3, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wpackhss", 0xee700080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wpackhus", 0xee500080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wpackwss", 0xeeb00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wpackwus", 0xee900080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wpackdss", 0xeef00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wpackdus", 0xeed00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wrorh", 0xee700040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wrorhg", 0xee700148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wrorw", 0xeeb00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wrorwg", 0xeeb00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wrord", 0xeef00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wrordg", 0xeef00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsadb", 0xee000120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsadbz", 0xee100120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsadh", 0xee400120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsadhz", 0xee500120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wshufh", 0xee0001e0, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wshufh},
- {"wsllh", 0xee500040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsllhg", 0xee500148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsllw", 0xee900040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsllwg", 0xee900148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wslld", 0xeed00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wslldg", 0xeed00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsrah", 0xee400040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsrahg", 0xee400148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsraw", 0xee800040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsrawg", 0xee800148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsrad", 0xeec00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsradg", 0xeec00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsrlh", 0xee600040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsrlhg", 0xee600148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsrlw", 0xeea00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsrlwg", 0xeea00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wsrld", 0xeee00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsrldg", 0xeee00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
- {"wstrb", 0xec000000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldst},
- {"wstrh", 0xec400000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldst},
- {"wstrw", 0xec000100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldstw},
- {"wstrd", 0xec400100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wldst},
- {"wsubbss", 0xee3001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubb", 0xee0001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubbus", 0xee1001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubhss", 0xee7001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubh", 0xee4001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubhus", 0xee5001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubwss", 0xeeb001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubw", 0xee8001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wsubwus", 0xee9001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wunpckehub", 0xee0000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckehuh", 0xee4000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckehuw", 0xee8000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckehsb", 0xee2000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckehsh", 0xee6000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckehsw", 0xeea000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckihb", 0xee1000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wunpckihh", 0xee5000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wunpckihw", 0xee9000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wunpckelub", 0xee0000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckeluh", 0xee4000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckeluw", 0xee8000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckelsb", 0xee2000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckelsh", 0xee6000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckelsw", 0xeea000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
- {"wunpckilb", 0xee1000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wunpckilh", 0xee5000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wunpckilw", 0xee9000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wxor", 0xee100000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
- {"wzero", 0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wzero},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
+ CE(tandcb, e130130, iwmmxt_tandorc),
+ CE(tandch, e530130, iwmmxt_tandorc),
+ CE(tandcw, e930130, iwmmxt_tandorc),
+ CE(tbcstb, e400010, iwmmxt_tbcst),
+ CE(tbcsth, e400050, iwmmxt_tbcst),
+ CE(tbcstw, e400090, iwmmxt_tbcst),
+ CE(textrcb, e130170, iwmmxt_textrc),
+ CE(textrch, e530170, iwmmxt_textrc),
+ CE(textrcw, e930170, iwmmxt_textrc),
+ CE(textrmub, e100070, iwmmxt_textrm),
+ CE(textrmuh, e500070, iwmmxt_textrm),
+ CE(textrmuw, e900070, iwmmxt_textrm),
+ CE(textrmsb, e100078, iwmmxt_textrm),
+ CE(textrmsh, e500078, iwmmxt_textrm),
+ CE(textrmsw, e900078, iwmmxt_textrm),
+ CE(tinsrb, e600010, iwmmxt_tinsr),
+ CE(tinsrh, e600050, iwmmxt_tinsr),
+ CE(tinsrw, e600090, iwmmxt_tinsr),
+ CE(tmcr, e000110, iwmmxt_tmcr),
+ CE(tmcrr, c400000, iwmmxt_tmcrr),
+ CE(tmia, e200010, iwmmxt_tmia),
+ CE(tmiaph, e280010, iwmmxt_tmia),
+ CE(tmiabb, e2c0010, iwmmxt_tmia),
+ CE(tmiabt, e2d0010, iwmmxt_tmia),
+ CE(tmiatb, e2e0010, iwmmxt_tmia),
+ CE(tmiatt, e2f0010, iwmmxt_tmia),
+ CE(tmovmskb, e100030, iwmmxt_tmovmsk),
+ CE(tmovmskh, e500030, iwmmxt_tmovmsk),
+ CE(tmovmskw, e900030, iwmmxt_tmovmsk),
+ CE(tmrc, e100110, iwmmxt_tmrc),
+ CE(tmrrc, c500000, iwmmxt_tmrrc),
+ CE(torcb, e130150, iwmmxt_tandorc),
+ CE(torch, e530150, iwmmxt_tandorc),
+ CE(torcw, e930150, iwmmxt_tandorc),
+ CE(waccb, e0001c0, iwmmxt_wrwr),
+ CE(wacch, e4001c0, iwmmxt_wrwr),
+ CE(waccw, e8001c0, iwmmxt_wrwr),
+ CE(waddbss, e300180, iwmmxt_wrwrwr),
+ CE(waddb, e000180, iwmmxt_wrwrwr),
+ CE(waddbus, e100180, iwmmxt_wrwrwr),
+ CE(waddhss, e700180, iwmmxt_wrwrwr),
+ CE(waddh, e400180, iwmmxt_wrwrwr),
+ CE(waddhus, e500180, iwmmxt_wrwrwr),
+ CE(waddwss, eb00180, iwmmxt_wrwrwr),
+ CE(waddw, e800180, iwmmxt_wrwrwr),
+ CE(waddwus, e900180, iwmmxt_wrwrwr),
+ CE(waligni, e000020, iwmmxt_waligni),
+ CE(walignr0, e800020, iwmmxt_wrwrwr),
+ CE(walignr1, e900020, iwmmxt_wrwrwr),
+ CE(walignr2, ea00020, iwmmxt_wrwrwr),
+ CE(walignr3, eb00020, iwmmxt_wrwrwr),
+ CE(wand, e200000, iwmmxt_wrwrwr),
+ CE(wandn, e300000, iwmmxt_wrwrwr),
+ CE(wavg2b, e800000, iwmmxt_wrwrwr),
+ CE(wavg2br, e900000, iwmmxt_wrwrwr),
+ CE(wavg2h, ec00000, iwmmxt_wrwrwr),
+ CE(wavg2hr, ed00000, iwmmxt_wrwrwr),
+ CE(wcmpeqb, e000060, iwmmxt_wrwrwr),
+ CE(wcmpeqh, e400060, iwmmxt_wrwrwr),
+ CE(wcmpeqw, e800060, iwmmxt_wrwrwr),
+ CE(wcmpgtub, e100060, iwmmxt_wrwrwr),
+ CE(wcmpgtuh, e500060, iwmmxt_wrwrwr),
+ CE(wcmpgtuw, e900060, iwmmxt_wrwrwr),
+ CE(wcmpgtsb, e300060, iwmmxt_wrwrwr),
+ CE(wcmpgtsh, e700060, iwmmxt_wrwrwr),
+ CE(wcmpgtsw, eb00060, iwmmxt_wrwrwr),
+ CE(wldrb, c100000, iwmmxt_wldst),
+ CE(wldrh, c500000, iwmmxt_wldst),
+ CE(wldrw, c100100, iwmmxt_wldstw),
+ CE(wldrd, c500100, iwmmxt_wldst),
+ CE(wmacs, e600100, iwmmxt_wrwrwr),
+ CE(wmacsz, e700100, iwmmxt_wrwrwr),
+ CE(wmacu, e400100, iwmmxt_wrwrwr),
+ CE(wmacuz, e500100, iwmmxt_wrwrwr),
+ CE(wmadds, ea00100, iwmmxt_wrwrwr),
+ CE(wmaddu, e800100, iwmmxt_wrwrwr),
+ CE(wmaxsb, e200160, iwmmxt_wrwrwr),
+ CE(wmaxsh, e600160, iwmmxt_wrwrwr),
+ CE(wmaxsw, ea00160, iwmmxt_wrwrwr),
+ CE(wmaxub, e000160, iwmmxt_wrwrwr),
+ CE(wmaxuh, e400160, iwmmxt_wrwrwr),
+ CE(wmaxuw, e800160, iwmmxt_wrwrwr),
+ CE(wminsb, e300160, iwmmxt_wrwrwr),
+ CE(wminsh, e700160, iwmmxt_wrwrwr),
+ CE(wminsw, eb00160, iwmmxt_wrwrwr),
+ CE(wminub, e100160, iwmmxt_wrwrwr),
+ CE(wminuh, e500160, iwmmxt_wrwrwr),
+ CE(wminuw, e900160, iwmmxt_wrwrwr),
+ CE(wmov, e000000, iwmmxt_wmov),
+ CE(wmulsm, e300100, iwmmxt_wrwrwr),
+ CE(wmulsl, e200100, iwmmxt_wrwrwr),
+ CE(wmulum, e100100, iwmmxt_wrwrwr),
+ CE(wmulul, e000100, iwmmxt_wrwrwr),
+ CE(wor, e000000, iwmmxt_wrwrwr),
+ CE(wpackhss, e700080, iwmmxt_wrwrwr),
+ CE(wpackhus, e500080, iwmmxt_wrwrwr),
+ CE(wpackwss, eb00080, iwmmxt_wrwrwr),
+ CE(wpackwus, e900080, iwmmxt_wrwrwr),
+ CE(wpackdss, ef00080, iwmmxt_wrwrwr),
+ CE(wpackdus, ed00080, iwmmxt_wrwrwr),
+ CE(wrorh, e700040, iwmmxt_wrwrwr),
+ CE(wrorhg, e700148, iwmmxt_wrwrwcg),
+ CE(wrorw, eb00040, iwmmxt_wrwrwr),
+ CE(wrorwg, eb00148, iwmmxt_wrwrwcg),
+ CE(wrord, ef00040, iwmmxt_wrwrwr),
+ CE(wrordg, ef00148, iwmmxt_wrwrwcg),
+ CE(wsadb, e000120, iwmmxt_wrwrwr),
+ CE(wsadbz, e100120, iwmmxt_wrwrwr),
+ CE(wsadh, e400120, iwmmxt_wrwrwr),
+ CE(wsadhz, e500120, iwmmxt_wrwrwr),
+ CE(wshufh, e0001e0, iwmmxt_wshufh),
+ CE(wsllh, e500040, iwmmxt_wrwrwr),
+ CE(wsllhg, e500148, iwmmxt_wrwrwcg),
+ CE(wsllw, e900040, iwmmxt_wrwrwr),
+ CE(wsllwg, e900148, iwmmxt_wrwrwcg),
+ CE(wslld, ed00040, iwmmxt_wrwrwr),
+ CE(wslldg, ed00148, iwmmxt_wrwrwcg),
+ CE(wsrah, e400040, iwmmxt_wrwrwr),
+ CE(wsrahg, e400148, iwmmxt_wrwrwcg),
+ CE(wsraw, e800040, iwmmxt_wrwrwr),
+ CE(wsrawg, e800148, iwmmxt_wrwrwcg),
+ CE(wsrad, ec00040, iwmmxt_wrwrwr),
+ CE(wsradg, ec00148, iwmmxt_wrwrwcg),
+ CE(wsrlh, e600040, iwmmxt_wrwrwr),
+ CE(wsrlhg, e600148, iwmmxt_wrwrwcg),
+ CE(wsrlw, ea00040, iwmmxt_wrwrwr),
+ CE(wsrlwg, ea00148, iwmmxt_wrwrwcg),
+ CE(wsrld, ee00040, iwmmxt_wrwrwr),
+ CE(wsrldg, ee00148, iwmmxt_wrwrwcg),
+ CE(wstrb, c000000, iwmmxt_wldst),
+ CE(wstrh, c400000, iwmmxt_wldst),
+ CE(wstrw, c000100, iwmmxt_wldstw),
+ CE(wstrd, c400100, iwmmxt_wldst),
+ CE(wsubbss, e3001a0, iwmmxt_wrwrwr),
+ CE(wsubb, e0001a0, iwmmxt_wrwrwr),
+ CE(wsubbus, e1001a0, iwmmxt_wrwrwr),
+ CE(wsubhss, e7001a0, iwmmxt_wrwrwr),
+ CE(wsubh, e4001a0, iwmmxt_wrwrwr),
+ CE(wsubhus, e5001a0, iwmmxt_wrwrwr),
+ CE(wsubwss, eb001a0, iwmmxt_wrwrwr),
+ CE(wsubw, e8001a0, iwmmxt_wrwrwr),
+ CE(wsubwus, e9001a0, iwmmxt_wrwrwr),
+ CE(wunpckehub,e0000c0, iwmmxt_wrwr),
+ CE(wunpckehuh,e4000c0, iwmmxt_wrwr),
+ CE(wunpckehuw,e8000c0, iwmmxt_wrwr),
+ CE(wunpckehsb,e2000c0, iwmmxt_wrwr),
+ CE(wunpckehsh,e6000c0, iwmmxt_wrwr),
+ CE(wunpckehsw,ea000c0, iwmmxt_wrwr),
+ CE(wunpckihb, e1000c0, iwmmxt_wrwrwr),
+ CE(wunpckihh, e5000c0, iwmmxt_wrwrwr),
+ CE(wunpckihw, e9000c0, iwmmxt_wrwrwr),
+ CE(wunpckelub,e0000e0, iwmmxt_wrwr),
+ CE(wunpckeluh,e4000e0, iwmmxt_wrwr),
+ CE(wunpckeluw,e8000e0, iwmmxt_wrwr),
+ CE(wunpckelsb,e2000e0, iwmmxt_wrwr),
+ CE(wunpckelsh,e6000e0, iwmmxt_wrwr),
+ CE(wunpckelsw,ea000e0, iwmmxt_wrwr),
+ CE(wunpckilb, e1000e0, iwmmxt_wrwrwr),
+ CE(wunpckilh, e5000e0, iwmmxt_wrwrwr),
+ CE(wunpckilw, e9000e0, iwmmxt_wrwrwr),
+ CE(wxor, e100000, iwmmxt_wrwrwr),
+ CE(wzero, e300000, iwmmxt_wzero),
- /* Cirrus Maverick instructions. */
- {"cfldrs", 0xec100400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_1},
- {"cfldrd", 0xec500400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_2},
- {"cfldr32", 0xec100500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_3},
- {"cfldr64", 0xec500500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_4},
- {"cfstrs", 0xec000400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_1},
- {"cfstrd", 0xec400400, 6, ARM_CEXT_MAVERICK, do_mav_ldst_2},
- {"cfstr32", 0xec000500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_3},
- {"cfstr64", 0xec400500, 7, ARM_CEXT_MAVERICK, do_mav_ldst_4},
- {"cfmvsr", 0xee000450, 6, ARM_CEXT_MAVERICK, do_mav_binops_2a},
- {"cfmvrs", 0xee100450, 6, ARM_CEXT_MAVERICK, do_mav_binops_1a},
- {"cfmvdlr", 0xee000410, 7, ARM_CEXT_MAVERICK, do_mav_binops_2b},
- {"cfmvrdl", 0xee100410, 7, ARM_CEXT_MAVERICK, do_mav_binops_1b},
- {"cfmvdhr", 0xee000430, 7, ARM_CEXT_MAVERICK, do_mav_binops_2b},
- {"cfmvrdh", 0xee100430, 7, ARM_CEXT_MAVERICK, do_mav_binops_1b},
- {"cfmv64lr", 0xee000510, 8, ARM_CEXT_MAVERICK, do_mav_binops_2c},
- {"cfmvr64l", 0xee100510, 8, ARM_CEXT_MAVERICK, do_mav_binops_1c},
- {"cfmv64hr", 0xee000530, 8, ARM_CEXT_MAVERICK, do_mav_binops_2c},
- {"cfmvr64h", 0xee100530, 8, ARM_CEXT_MAVERICK, do_mav_binops_1c},
- {"cfmval32", 0xee200440, 8, ARM_CEXT_MAVERICK, do_mav_binops_3a},
- {"cfmv32al", 0xee100440, 8, ARM_CEXT_MAVERICK, do_mav_binops_3b},
- {"cfmvam32", 0xee200460, 8, ARM_CEXT_MAVERICK, do_mav_binops_3a},
- {"cfmv32am", 0xee100460, 8, ARM_CEXT_MAVERICK, do_mav_binops_3b},
- {"cfmvah32", 0xee200480, 8, ARM_CEXT_MAVERICK, do_mav_binops_3a},
- {"cfmv32ah", 0xee100480, 8, ARM_CEXT_MAVERICK, do_mav_binops_3b},
- {"cfmva32", 0xee2004a0, 7, ARM_CEXT_MAVERICK, do_mav_binops_3a},
- {"cfmv32a", 0xee1004a0, 7, ARM_CEXT_MAVERICK, do_mav_binops_3b},
- {"cfmva64", 0xee2004c0, 7, ARM_CEXT_MAVERICK, do_mav_binops_3c},
- {"cfmv64a", 0xee1004c0, 7, ARM_CEXT_MAVERICK, do_mav_binops_3d},
- {"cfmvsc32", 0xee2004e0, 8, ARM_CEXT_MAVERICK, do_mav_dspsc_1},
- {"cfmv32sc", 0xee1004e0, 8, ARM_CEXT_MAVERICK, do_mav_dspsc_2},
- {"cfcpys", 0xee000400, 6, ARM_CEXT_MAVERICK, do_mav_binops_1d},
- {"cfcpyd", 0xee000420, 6, ARM_CEXT_MAVERICK, do_mav_binops_1e},
- {"cfcvtsd", 0xee000460, 7, ARM_CEXT_MAVERICK, do_mav_binops_1f},
- {"cfcvtds", 0xee000440, 7, ARM_CEXT_MAVERICK, do_mav_binops_1g},
- {"cfcvt32s", 0xee000480, 8, ARM_CEXT_MAVERICK, do_mav_binops_1h},
- {"cfcvt32d", 0xee0004a0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1i},
- {"cfcvt64s", 0xee0004c0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1j},
- {"cfcvt64d", 0xee0004e0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1k},
- {"cfcvts32", 0xee100580, 8, ARM_CEXT_MAVERICK, do_mav_binops_1l},
- {"cfcvtd32", 0xee1005a0, 8, ARM_CEXT_MAVERICK, do_mav_binops_1m},
- {"cftruncs32", 0xee1005c0, 10, ARM_CEXT_MAVERICK, do_mav_binops_1l},
- {"cftruncd32", 0xee1005e0, 10, ARM_CEXT_MAVERICK, do_mav_binops_1m},
- {"cfrshl32", 0xee000550, 8, ARM_CEXT_MAVERICK, do_mav_triple_4a},
- {"cfrshl64", 0xee000570, 8, ARM_CEXT_MAVERICK, do_mav_triple_4b},
- {"cfsh32", 0xee000500, 6, ARM_CEXT_MAVERICK, do_mav_shift_1},
- {"cfsh64", 0xee200500, 6, ARM_CEXT_MAVERICK, do_mav_shift_2},
- {"cfcmps", 0xee100490, 6, ARM_CEXT_MAVERICK, do_mav_triple_5a},
- {"cfcmpd", 0xee1004b0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5b},
- {"cfcmp32", 0xee100590, 7, ARM_CEXT_MAVERICK, do_mav_triple_5c},
- {"cfcmp64", 0xee1005b0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5d},
- {"cfabss", 0xee300400, 6, ARM_CEXT_MAVERICK, do_mav_binops_1d},
- {"cfabsd", 0xee300420, 6, ARM_CEXT_MAVERICK, do_mav_binops_1e},
- {"cfnegs", 0xee300440, 6, ARM_CEXT_MAVERICK, do_mav_binops_1d},
- {"cfnegd", 0xee300460, 6, ARM_CEXT_MAVERICK, do_mav_binops_1e},
- {"cfadds", 0xee300480, 6, ARM_CEXT_MAVERICK, do_mav_triple_5e},
- {"cfaddd", 0xee3004a0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5f},
- {"cfsubs", 0xee3004c0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5e},
- {"cfsubd", 0xee3004e0, 6, ARM_CEXT_MAVERICK, do_mav_triple_5f},
- {"cfmuls", 0xee100400, 6, ARM_CEXT_MAVERICK, do_mav_triple_5e},
- {"cfmuld", 0xee100420, 6, ARM_CEXT_MAVERICK, do_mav_triple_5f},
- {"cfabs32", 0xee300500, 7, ARM_CEXT_MAVERICK, do_mav_binops_1n},
- {"cfabs64", 0xee300520, 7, ARM_CEXT_MAVERICK, do_mav_binops_1o},
- {"cfneg32", 0xee300540, 7, ARM_CEXT_MAVERICK, do_mav_binops_1n},
- {"cfneg64", 0xee300560, 7, ARM_CEXT_MAVERICK, do_mav_binops_1o},
- {"cfadd32", 0xee300580, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
- {"cfadd64", 0xee3005a0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5h},
- {"cfsub32", 0xee3005c0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
- {"cfsub64", 0xee3005e0, 7, ARM_CEXT_MAVERICK, do_mav_triple_5h},
- {"cfmul32", 0xee100500, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
- {"cfmul64", 0xee100520, 7, ARM_CEXT_MAVERICK, do_mav_triple_5h},
- {"cfmac32", 0xee100540, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
- {"cfmsc32", 0xee100560, 7, ARM_CEXT_MAVERICK, do_mav_triple_5g},
- {"cfmadd32", 0xee000600, 8, ARM_CEXT_MAVERICK, do_mav_quad_6a},
- {"cfmsub32", 0xee100600, 8, ARM_CEXT_MAVERICK, do_mav_quad_6a},
- {"cfmadda32", 0xee200600, 9, ARM_CEXT_MAVERICK, do_mav_quad_6b},
- {"cfmsuba32", 0xee300600, 9, ARM_CEXT_MAVERICK, do_mav_quad_6b},
+#undef ARM_VARIANT
+#define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
+ CE(cfldrs, c100400, mav_ldst_1),
+ CE(cfldrd, c500400, mav_ldst_2),
+ CE(cfldr32, c100500, mav_ldst_3),
+ CE(cfldr64, c500500, mav_ldst_4),
+ CE(cfstrs, c000400, mav_ldst_1),
+ CE(cfstrd, c400400, mav_ldst_2),
+ CE(cfstr32, c000500, mav_ldst_3),
+ CE(cfstr64, c400500, mav_ldst_4),
+ CE(cfmvsr, e000450, mav_binops_2a),
+ CE(cfmvrs, e100450, mav_binops_1a),
+ CE(cfmvdlr, e000410, mav_binops_2b),
+ CE(cfmvrdl, e100410, mav_binops_1b),
+ CE(cfmvdhr, e000430, mav_binops_2b),
+ CE(cfmvrdh, e100430, mav_binops_1b),
+ CE(cfmv64lr, e000510, mav_binops_2c),
+ CE(cfmvr64l, e100510, mav_binops_1c),
+ CE(cfmv64hr, e000530, mav_binops_2c),
+ CE(cfmvr64h, e100530, mav_binops_1c),
+ CE(cfmval32, e200440, mav_binops_3a),
+ CE(cfmv32al, e100440, mav_binops_3b),
+ CE(cfmvam32, e200460, mav_binops_3a),
+ CE(cfmv32am, e100460, mav_binops_3b),
+ CE(cfmvah32, e200480, mav_binops_3a),
+ CE(cfmv32ah, e100480, mav_binops_3b),
+ CE(cfmva32, e2004a0, mav_binops_3a),
+ CE(cfmv32a, e1004a0, mav_binops_3b),
+ CE(cfmva64, e2004c0, mav_binops_3c),
+ CE(cfmv64a, e1004c0, mav_binops_3d),
+ CE(cfmvsc32, e2004e0, mav_dspsc_1),
+ CE(cfmv32sc, e1004e0, mav_dspsc_2),
+ CE(cfcpys, e000400, mav_binops_1d),
+ CE(cfcpyd, e000420, mav_binops_1e),
+ CE(cfcvtsd, e000460, mav_binops_1f),
+ CE(cfcvtds, e000440, mav_binops_1g),
+ CE(cfcvt32s, e000480, mav_binops_1h),
+ CE(cfcvt32d, e0004a0, mav_binops_1i),
+ CE(cfcvt64s, e0004c0, mav_binops_1j),
+ CE(cfcvt64d, e0004e0, mav_binops_1k),
+ CE(cfcvts32, e100580, mav_binops_1l),
+ CE(cfcvtd32, e1005a0, mav_binops_1m),
+ CE(cftruncs32,e1005c0, mav_binops_1l),
+ CE(cftruncd32,e1005e0, mav_binops_1m),
+ CE(cfrshl32, e000550, mav_triple_4a),
+ CE(cfrshl64, e000570, mav_triple_4b),
+ CE(cfsh32, e000500, mav_shift_1),
+ CE(cfsh64, e200500, mav_shift_2),
+ CE(cfcmps, e100490, mav_triple_5a),
+ CE(cfcmpd, e1004b0, mav_triple_5b),
+ CE(cfcmp32, e100590, mav_triple_5c),
+ CE(cfcmp64, e1005b0, mav_triple_5d),
+ CE(cfabss, e300400, mav_binops_1d),
+ CE(cfabsd, e300420, mav_binops_1e),
+ CE(cfnegs, e300440, mav_binops_1d),
+ CE(cfnegd, e300460, mav_binops_1e),
+ CE(cfadds, e300480, mav_triple_5e),
+ CE(cfaddd, e3004a0, mav_triple_5f),
+ CE(cfsubs, e3004c0, mav_triple_5e),
+ CE(cfsubd, e3004e0, mav_triple_5f),
+ CE(cfmuls, e100400, mav_triple_5e),
+ CE(cfmuld, e100420, mav_triple_5f),
+ CE(cfabs32, e300500, mav_binops_1n),
+ CE(cfabs64, e300520, mav_binops_1o),
+ CE(cfneg32, e300540, mav_binops_1n),
+ CE(cfneg64, e300560, mav_binops_1o),
+ CE(cfadd32, e300580, mav_triple_5g),
+ CE(cfadd64, e3005a0, mav_triple_5h),
+ CE(cfsub32, e3005c0, mav_triple_5g),
+ CE(cfsub64, e3005e0, mav_triple_5h),
+ CE(cfmul32, e100500, mav_triple_5g),
+ CE(cfmul64, e100520, mav_triple_5h),
+ CE(cfmac32, e100540, mav_triple_5g),
+ CE(cfmsc32, e100560, mav_triple_5g),
+ CE(cfmadd32, e000600, mav_quad_6a),
+ CE(cfmsub32, e100600, mav_quad_6a),
+ CE(cfmadda32, e200600, mav_quad_6b),
+ CE(cfmsuba32, e300600, mav_quad_6b),
};
+#undef ARM_VARIANT
+#undef CE
+#undef CM
+#undef UE
+#undef UF
-static const struct thumb_opcode tinsns[] =
+/* Thumb instructions are substantially simpler, there being no conditional
+ suffix or infix. */
+#define TI(mnem, opcode, tenc) \
+ { #mnem, 0x ## opcode, THUMB_VARIANT, do_ ## tenc }
+
+static const struct asm_opcode tinsns[] =
{
- /* Thumb v1 (ARMv4T). */
- {"adc", 0x4140, 2, ARM_EXT_V4T, do_t_arit},
- {"add", 0x0000, 2, ARM_EXT_V4T, do_t_add_sub},
- {"and", 0x4000, 2, ARM_EXT_V4T, do_t_arit},
- {"asr", 0x4100, 2, ARM_EXT_V4T, do_t_shift},
- {"b", T_OPCODE_BRANCH, 2, ARM_EXT_V4T, do_t_branch12},
- {"beq", 0xd0fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bne", 0xd1fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bcs", 0xd2fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bhs", 0xd2fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bcc", 0xd3fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bul", 0xd3fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"blo", 0xd3fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bmi", 0xd4fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bpl", 0xd5fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bvs", 0xd6fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bvc", 0xd7fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bhi", 0xd8fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bls", 0xd9fe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bge", 0xdafe, 2, ARM_EXT_V4T, do_t_branch9},
- {"blt", 0xdbfe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bgt", 0xdcfe, 2, ARM_EXT_V4T, do_t_branch9},
- {"ble", 0xddfe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bal", 0xdefe, 2, ARM_EXT_V4T, do_t_branch9},
- {"bic", 0x4380, 2, ARM_EXT_V4T, do_t_arit},
- {"bl", 0xf7fffffe, 4, ARM_EXT_V4T, do_t_branch23},
- {"bx", 0x4700, 2, ARM_EXT_V4T, do_t_bx},
- {"cmn", T_OPCODE_CMN, 2, ARM_EXT_V4T, do_t_arit},
- {"cmp", T_OPCODE_CMP_HR,2, ARM_EXT_V4T, do_t_mov_cmp},
- {"eor", 0x4040, 2, ARM_EXT_V4T, do_t_arit},
- {"ldmia", 0xc800, 2, ARM_EXT_V4T, do_t_ldmstm},
- {"ldr", T_OPCODE_LDR_RW,2, ARM_EXT_V4T, do_t_ldst},
- {"ldrb", T_OPCODE_LDR_RB,2, ARM_EXT_V4T, do_t_ldst},
- {"ldrh", T_OPCODE_LDR_RH,2, ARM_EXT_V4T, do_t_ldst},
- {"ldrsb", 0x5600, 2, ARM_EXT_V4T, do_t_lds},
- {"ldrsh", 0x5e00, 2, ARM_EXT_V4T, do_t_lds},
- {"ldsb", 0x5600, 2, ARM_EXT_V4T, do_t_lds},
- {"ldsh", 0x5e00, 2, ARM_EXT_V4T, do_t_lds},
- {"lsl", 0x4080, 2, ARM_EXT_V4T, do_t_shift},
- {"lsr", 0x40c0, 2, ARM_EXT_V4T, do_t_shift},
- {"mov", T_OPCODE_MOV_HR,2, ARM_EXT_V4T, do_t_mov_cmp},
- {"mul", T_OPCODE_MUL, 2, ARM_EXT_V4T, do_t_arit},
- {"mvn", T_OPCODE_MVN, 2, ARM_EXT_V4T, do_t_arit},
- {"neg", T_OPCODE_NEG, 2, ARM_EXT_V4T, do_t_arit},
- {"orr", 0x4300, 2, ARM_EXT_V4T, do_t_arit},
- {"pop", 0xbc00, 2, ARM_EXT_V4T, do_t_push_pop},
- {"push", 0xb400, 2, ARM_EXT_V4T, do_t_push_pop},
- {"ror", 0x41c0, 2, ARM_EXT_V4T, do_t_arit},
- {"sbc", 0x4180, 2, ARM_EXT_V4T, do_t_arit},
- {"stmia", 0xc000, 2, ARM_EXT_V4T, do_t_ldmstm},
- {"str", T_OPCODE_STR_RW,2, ARM_EXT_V4T, do_t_ldst},
- {"strb", T_OPCODE_STR_RB,2, ARM_EXT_V4T, do_t_ldst},
- {"strh", T_OPCODE_STR_RH,2, ARM_EXT_V4T, do_t_ldst},
- {"swi", 0xdf00, 2, ARM_EXT_V4T, do_t_swi},
- {"sub", 0x8000, 2, ARM_EXT_V4T, do_t_add_sub},
- {"tst", T_OPCODE_TST, 2, ARM_EXT_V4T, do_t_arit},
+#define THUMB_VARIANT ARM_EXT_V4T /* Thumb v1 (ARMv4T). */
+ TI(adc, 4140, t_arit),
+ TI(add, 0000, t_add_sub),
+ TI(and, 4000, t_arit),
+ TI(asr, 4100, t_shift),
+ TI(b, e7fe, t_branch12),
+ TI(beq, d0fe, t_branch9),
+ TI(bne, d1fe, t_branch9),
+ TI(bcs, d2fe, t_branch9),
+ TI(bhs, d2fe, t_branch9),
+ TI(bcc, d3fe, t_branch9),
+ TI(bul, d3fe, t_branch9),
+ TI(blo, d3fe, t_branch9),
+ TI(bmi, d4fe, t_branch9),
+ TI(bpl, d5fe, t_branch9),
+ TI(bvs, d6fe, t_branch9),
+ TI(bvc, d7fe, t_branch9),
+ TI(bhi, d8fe, t_branch9),
+ TI(bls, d9fe, t_branch9),
+ TI(bge, dafe, t_branch9),
+ TI(blt, dbfe, t_branch9),
+ TI(bgt, dcfe, t_branch9),
+ TI(ble, ddfe, t_branch9),
+ TI(bal, defe, t_branch9),
+ TI(bic, 4380, t_arit),
+ TI(bl, f7fffffe, t_branch23),
+ TI(bx, 4700, t_bx),
+ TI(cmn, 42c0, t_arit),
+ TI(cmp, 4280, t_mov_cmp),
+ TI(eor, 4040, t_arit),
+ TI(ldmia, c800, t_ldmstm),
+ TI(ldr, 5800, t_ldst),
+ TI(ldrb, 5c00, t_ldst),
+ TI(ldrh, 5a00, t_ldst),
+ TI(ldrsb, 5600, t_lds),
+ TI(ldrsh, 5e00, t_lds),
+ TI(ldsb, 5600, t_lds),
+ TI(ldsh, 5e00, t_lds),
+ TI(lsl, 4080, t_shift),
+ TI(lsr, 40c0, t_shift),
+ TI(mov, 4600, t_mov_cmp),
+ TI(mul, 4340, t_arit),
+ TI(mvn, 43c0, t_arit),
+ TI(neg, 4240, t_arit),
+ TI(orr, 4300, t_arit),
+ TI(pop, bc00, t_push_pop),
+ TI(push, b400, t_push_pop),
+ TI(ror, 41c0, t_arit),
+ TI(sbc, 4180, t_arit),
+ TI(stmia, c000, t_ldmstm),
+ TI(str, 5000, t_ldst),
+ TI(strb, 5400, t_ldst),
+ TI(strh, 5200, t_ldst),
+ TI(swi, df00, t_swi),
+ TI(sub, 8000, t_add_sub),
+ TI(tst, 4200, t_arit),
/* Pseudo ops: */
- {"adr", 0x000f, 2, ARM_EXT_V4T, do_t_adr},
- {"nop", 0x46C0, 2, ARM_EXT_V4T, do_empty}, /* mov r8,r8 */
- /* Thumb v2 (ARMv5T). */
- {"blx", 0x4780, 2, ARM_EXT_V5T, do_t_blx},
- {"bkpt", 0xbe00, 2, ARM_EXT_V5T, do_t_bkpt},
+ TI(adr, 000f, t_adr),
+ TI(nop, 46c0, empty), /* mov r8,r8 */
- /* ARM V6. */
- {"cpsie", 0xb660, 2, ARM_EXT_V6, do_t_cps},
- {"cpsid", 0xb670, 2, ARM_EXT_V6, do_t_cps},
- {"cpy", 0x4600, 2, ARM_EXT_V6, do_t_cpy},
- {"rev", 0xba00, 2, ARM_EXT_V6, do_t_arit},
- {"rev16", 0xba40, 2, ARM_EXT_V6, do_t_arit},
- {"revsh", 0xbac0, 2, ARM_EXT_V6, do_t_arit},
- {"setend", 0xb650, 2, ARM_EXT_V6, do_t_setend},
- {"sxth", 0xb200, 2, ARM_EXT_V6, do_t_arit},
- {"sxtb", 0xb240, 2, ARM_EXT_V6, do_t_arit},
- {"uxth", 0xb280, 2, ARM_EXT_V6, do_t_arit},
- {"uxtb", 0xb2c0, 2, ARM_EXT_V6, do_t_arit},
+#undef THUMB_VARIANT
+#define THUMB_VARIANT ARM_EXT_V5T /* Thumb v2 (ARMv5T). */
+ TI(blx, 4780, t_blx),
+ TI(bkpt, be00, t_bkpt),
- /* ARM V6K. */
- {"sev", 0xbf40, 2, ARM_EXT_V6K, do_empty},
- {"wfe", 0xbf20, 2, ARM_EXT_V6K, do_empty},
- {"wfi", 0xbf30, 2, ARM_EXT_V6K, do_empty},
- {"yield", 0xbf10, 2, ARM_EXT_V6K, do_empty},
+#undef THUMB_VARIANT
+#define THUMB_VARIANT ARM_EXT_V6
+ TI(cpsie, b660, t_cps),
+ TI(cpsid, b670, t_cps),
+ TI(cpy, 4600, t_cpy),
+ TI(rev, ba00, t_arit),
+ TI(rev16, ba40, t_arit),
+ TI(revsh, bac0, t_arit),
+ TI(setend, b650, t_setend),
+ TI(sxth, b200, t_arit),
+ TI(sxtb, b240, t_arit),
+ TI(uxth, b280, t_arit),
+ TI(uxtb, b2c0, t_arit),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT ARM_EXT_V6K
+ TI(sev, bf40, empty),
+ TI(wfe, bf20, empty),
+ TI(wfi, bf30, empty),
+ TI(yield, bf10, empty),
};
+#undef THUMB_VARIANT
+#undef TI
/* MD interface: bits in the object file. */
@@ -10543,55 +10608,6 @@
abort ();
}
-/* Iterate over the base tables to create the instruction patterns. */
-
-static void
-build_arm_ops_hsh (void)
-{
- unsigned int i;
- unsigned int j;
- static struct obstack insn_obstack;
-
- obstack_begin (&insn_obstack, 4000);
-
- for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
- {
- const struct asm_opcode *insn = insns + i;
-
- if (insn->cond_offset != 0)
- {
- /* Insn supports conditional execution. Build the varaints
- and insert them in the hash table. */
- for (j = 0; j < sizeof (conds) / sizeof (struct asm_cond); j++)
- {
- unsigned len = strlen (insn->template);
- struct asm_opcode *new;
- char *template;
-
- new = obstack_alloc (&insn_obstack, sizeof (struct asm_opcode));
- /* All condition codes are two characters. */
- template = obstack_alloc (&insn_obstack, len + 3);
-
- strncpy (template, insn->template, insn->cond_offset);
- strcpy (template + insn->cond_offset, conds[j].template);
- if (len > insn->cond_offset)
- strcpy (template + insn->cond_offset + 2,
- insn->template + insn->cond_offset);
- new->template = template;
- new->cond_offset = 0;
- new->variant = insn->variant;
- new->parms = insn->parms;
- new->value = (insn->value & ~COND_MASK) | conds[j].value;
-
- hash_insert (arm_ops_hsh, new->template, (PTR) new);
- }
- }
- /* Finally, insert the unconditional insn in the table directly;
- no need to build a copy. */
- hash_insert (arm_ops_hsh, insn->template, (PTR) insn);
- }
-}
-
void
md_begin (void)
{
@@ -10607,8 +10623,9 @@
|| (arm_reloc_hsh = hash_new ()) == NULL)
as_fatal (_("virtual memory exhausted"));
- build_arm_ops_hsh ();
- for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
+ for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
+ hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
+ for (i = 0; i < sizeof (tinsns) / sizeof (struct asm_opcode); i++)
hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));