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Thumb32 assembler (41/69)


I'm not sure why I added .postind at this point; it's not used yet.
(It will be used later.)  The meat of this patch is converting the
Maverick load/store encoder to use of cp_address_required_here.  This
means that use of the PC in these instructions (which is invalid) is
now diagnosed, requiring adjustments to the Maverick test case, which
was sloppy.

zw

	* config/tc-arm.c (struct arm_it): Add 'postind' field to operands.
	(mav_parse_offset): Delete.
	(do_mav_ldst): Use cp_address_required_here.
	* testsuite/gas/arm/maverick.s: Do not use PC as base register in
	load/store operations.
	* testsuite/gas/arm/maverick.d: Update to match.

===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c	(revision 43)
+++ gas/config/tc-arm.c	(revision 44)
@@ -199,6 +199,7 @@
     int isreg	   : 1;  /* operand was a register */
     int writeback  : 1;  /* operand has trailing ! */
     int hasreloc   : 1;  /* operand has relocation suffix */
+    int postind    : 1;  /* operand is post-indexed */
   } operands[6];
 };
 
@@ -2486,28 +2487,6 @@
   return val;
 }
 
-static int
-mav_parse_offset (char ** str, int * negative)
-{
-  int offset;
-
-  *negative = 0;
-
-  if (immediate_required_here (str, &offset, -0x3fc, 0x3fc, TRUE) == FAIL)
-    return 0;
-
-  if (offset < 0)
-    *negative = 1;
-
-  if (offset & 0x3)
-    {
-      inst.error = _("offset not a multiple of 4");
-      return 0;
-    }
-
-  return offset;
-}
-
 /* Parse an endian specifier ("BE" or "LE", case insensitive);
    returns 0 for big-endian, 1 for little-endian, FAIL for an error.  */
 
@@ -7909,52 +7888,11 @@
 static void
 do_mav_ldst (char * str, enum arm_reg_type reg0)
 {
-  int offset, negative;
-
   reg_or_fail (&str, 12, reg0);
   comma_or_fail (&str);
 
-  char_or_fail (&str, '[');
-  reg_or_fail (&str, 16, REG_TYPE_RN);
-
-  if (skip_past_comma (&str) == SUCCESS)
-    {
-      /* You are here: "<offset>]{!}".  */
-      inst.instruction |= PRE_INDEX;
-
-      offset = mav_parse_offset (&str, &negative);
-
-      if (inst.error)
-	return;
-
-      char_or_fail (&str, ']');
-
-      if (*str == '!')
-	{
-	  inst.instruction |= WRITE_BACK;
-	  ++str;
-	}
-    }
-  else
-    {
-      /* You are here: "], <offset>".  */
-      char_or_fail (&str, ']');
-      comma_or_fail (&str);
-
-      offset = mav_parse_offset (&str, &negative);
-      if (inst.error)
-	return;
-
-      inst.instruction |= CP_T_WB; /* Post indexed, set bit W.  */
-    }
+  cp_address_required_here (&str, TRUE);
   end_of_line (str);
-
-  if (negative)
-    offset = -offset;
-  else
-    inst.instruction |= CP_T_UD; /* Positive, so set bit U.  */
-
-  inst.instruction |= offset >> 2;
 }
 
 static void
===================================================================
Index: gas/testsuite/gas/arm/maverick.d
--- gas/testsuite/gas/arm/maverick.d	(revision 43)
+++ gas/testsuite/gas/arm/maverick.d	(revision 44)
@@ -13,121 +13,121 @@
 0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? *	cfldrsvc	mvf2, ?\[ip, #-956\]
 0*c <load_store\+0xc> bd ?1a ?04 ?ff ? *	cfldrslt	mvf0, ?\[sl, #-1020\]
 0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? *	cfldrscc	mvf12, ?\[r1, #-156\]
-0*14 <load_store\+0x14> ed ?bf ?d4 ?68 ? *	cfldrs	mvf13, ?\[pc, #416\]!
+0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? *	cfldrs	mvf13, ?\[r9, #416\]!
 0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? *	cfldrscs	mvf9, ?\[r0, #-1020\]!
 0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? *	cfldrsls	mvf4, ?\[r1, #-156\]!
-0*20 <load_store\+0x20> dd ?bf ?74 ?68 ? *	cfldrsle	mvf7, ?\[pc, #416\]!
+0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? *	cfldrsle	mvf7, ?\[r9, #416\]!
 0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? *	cfldrsvs	mvf11, ?\[r0, #-1020\]!
 0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? *	cfldrscc	mvf12, ?\[r1\], #-156
-0*2c <load_store\+0x2c> ec ?bf ?d4 ?68 ? *	cfldrs	mvf13, ?\[pc\], #416
+0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? *	cfldrs	mvf13, ?\[r9\], #416
 0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? *	cfldrscs	mvf9, ?\[r0\], #-1020
 0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? *	cfldrsls	mvf4, ?\[r1\], #-156
-0*38 <load_store\+0x38> dc ?bf ?74 ?68 ? *	cfldrsle	mvf7, ?\[pc\], #416
+0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? *	cfldrsle	mvf7, ?\[r9\], #416
 0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? *	cfldrdvs	mvd11, ?\[r0, #-1020\]
 0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? *	cfldrdcc	mvd12, ?\[r1, #-156\]
-0*44 <load_store\+0x44> ed ?df ?d4 ?68 ? *	cfldrd	mvd13, ?\[pc, #416\]
+0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? *	cfldrd	mvd13, ?\[r9, #416\]
 0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? *	cfldrdcs	mvd9, ?\[r0, #-1020\]
 0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? *	cfldrdls	mvd4, ?\[r1, #-156\]
-0*50 <load_store\+0x50> dd ?ff ?74 ?68 ? *	cfldrdle	mvd7, ?\[pc, #416\]!
+0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? *	cfldrdle	mvd7, ?\[r9, #416\]!
 0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? *	cfldrdvs	mvd11, ?\[r0, #-1020\]!
 0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? *	cfldrdcc	mvd12, ?\[r1, #-156\]!
-0*5c <load_store\+0x5c> ed ?ff ?d4 ?68 ? *	cfldrd	mvd13, ?\[pc, #416\]!
+0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? *	cfldrd	mvd13, ?\[r9, #416\]!
 0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? *	cfldrdcs	mvd9, ?\[r0, #-1020\]!
 0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? *	cfldrdls	mvd4, ?\[r1\], #-156
-0*68 <load_store\+0x68> dc ?ff ?74 ?68 ? *	cfldrdle	mvd7, ?\[pc\], #416
+0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? *	cfldrdle	mvd7, ?\[r9\], #416
 0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? *	cfldrdvs	mvd11, ?\[r0\], #-1020
 0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? *	cfldrdcc	mvd12, ?\[r1\], #-156
-0*74 <load_store\+0x74> ec ?ff ?d4 ?68 ? *	cfldrd	mvd13, ?\[pc\], #416
+0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? *	cfldrd	mvd13, ?\[r9\], #416
 0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? *	cfldr32cs	mvfx9, ?\[r0, #-1020\]
 0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? *	cfldr32ls	mvfx4, ?\[r1, #-156\]
-0*80 <load_store\+0x80> dd ?9f ?75 ?68 ? *	cfldr32le	mvfx7, ?\[pc, #416\]
+0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? *	cfldr32le	mvfx7, ?\[r9, #416\]
 0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? *	cfldr32vs	mvfx11, ?\[r0, #-1020\]
 0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? *	cfldr32cc	mvfx12, ?\[r1, #-156\]
-0*8c <load_store\+0x8c> ed ?bf ?d5 ?68 ? *	cfldr32	mvfx13, ?\[pc, #416\]!
+0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? *	cfldr32	mvfx13, ?\[r9, #416\]!
 0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? *	cfldr32cs	mvfx9, ?\[r0, #-1020\]!
 0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? *	cfldr32ls	mvfx4, ?\[r1, #-156\]!
-0*98 <load_store\+0x98> dd ?bf ?75 ?68 ? *	cfldr32le	mvfx7, ?\[pc, #416\]!
+0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? *	cfldr32le	mvfx7, ?\[r9, #416\]!
 0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? *	cfldr32vs	mvfx11, ?\[r0, #-1020\]!
 0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? *	cfldr32cc	mvfx12, ?\[r1\], #-156
-0*a4 <load_store\+0xa4> ec ?bf ?d5 ?68 ? *	cfldr32	mvfx13, ?\[pc\], #416
+0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? *	cfldr32	mvfx13, ?\[r9\], #416
 0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? *	cfldr32cs	mvfx9, ?\[r0\], #-1020
 0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? *	cfldr32ls	mvfx4, ?\[r1\], #-156
-0*b0 <load_store\+0xb0> dc ?bf ?75 ?68 ? *	cfldr32le	mvfx7, ?\[pc\], #416
+0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? *	cfldr32le	mvfx7, ?\[r9\], #416
 0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? *	cfldr64vs	mvdx11, ?\[r0, #-1020\]
 0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? *	cfldr64cc	mvdx12, ?\[r1, #-156\]
-0*bc <load_store\+0xbc> ed ?df ?d5 ?68 ? *	cfldr64	mvdx13, ?\[pc, #416\]
+0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? *	cfldr64	mvdx13, ?\[r9, #416\]
 0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? *	cfldr64cs	mvdx9, ?\[r0, #-1020\]
 0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? *	cfldr64ls	mvdx4, ?\[r1, #-156\]
-0*c8 <load_store\+0xc8> dd ?ff ?75 ?68 ? *	cfldr64le	mvdx7, ?\[pc, #416\]!
+0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? *	cfldr64le	mvdx7, ?\[r9, #416\]!
 0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? *	cfldr64vs	mvdx11, ?\[r0, #-1020\]!
 0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? *	cfldr64cc	mvdx12, ?\[r1, #-156\]!
-0*d4 <load_store\+0xd4> ed ?ff ?d5 ?68 ? *	cfldr64	mvdx13, ?\[pc, #416\]!
+0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? *	cfldr64	mvdx13, ?\[r9, #416\]!
 0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? *	cfldr64cs	mvdx9, ?\[r0, #-1020\]!
 0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? *	cfldr64ls	mvdx4, ?\[r1\], #-156
-0*e0 <load_store\+0xe0> dc ?ff ?75 ?68 ? *	cfldr64le	mvdx7, ?\[pc\], #416
+0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? *	cfldr64le	mvdx7, ?\[r9\], #416
 0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? *	cfldr64vs	mvdx11, ?\[r0\], #-1020
 0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? *	cfldr64cc	mvdx12, ?\[r1\], #-156
-0*ec <load_store\+0xec> ec ?ff ?d5 ?68 ? *	cfldr64	mvdx13, ?\[pc\], #416
+0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? *	cfldr64	mvdx13, ?\[r9\], #416
 0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? *	cfstrscs	mvf9, ?\[r0, #-1020\]
 0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? *	cfstrsls	mvf4, ?\[r1, #-156\]
-0*f8 <load_store\+0xf8> dd ?8f ?74 ?68 ? *	cfstrsle	mvf7, ?\[pc, #416\]
+0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? *	cfstrsle	mvf7, ?\[r9, #416\]
 0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? *	cfstrsvs	mvf11, ?\[r0, #-1020\]
 0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? *	cfstrscc	mvf12, ?\[r1, #-156\]
-0*104 <load_store\+0x104> ed ?af ?d4 ?68 ? *	cfstrs	mvf13, ?\[pc, #416\]!
+0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? *	cfstrs	mvf13, ?\[r9, #416\]!
 0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? *	cfstrscs	mvf9, ?\[r0, #-1020\]!
 0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? *	cfstrsls	mvf4, ?\[r1, #-156\]!
-0*110 <load_store\+0x110> dd ?af ?74 ?68 ? *	cfstrsle	mvf7, ?\[pc, #416\]!
+0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? *	cfstrsle	mvf7, ?\[r9, #416\]!
 0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? *	cfstrsvs	mvf11, ?\[r0, #-1020\]!
 0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? *	cfstrscc	mvf12, ?\[r1\], #-156
-0*11c <load_store\+0x11c> ec ?af ?d4 ?68 ? *	cfstrs	mvf13, ?\[pc\], #416
+0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? *	cfstrs	mvf13, ?\[r9\], #416
 0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? *	cfstrscs	mvf9, ?\[r0\], #-1020
 0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? *	cfstrsls	mvf4, ?\[r1\], #-156
-0*128 <load_store\+0x128> dc ?af ?74 ?68 ? *	cfstrsle	mvf7, ?\[pc\], #416
+0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? *	cfstrsle	mvf7, ?\[r9\], #416
 0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? *	cfstrdvs	mvd11, ?\[r0, #-1020\]
 0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? *	cfstrdcc	mvd12, ?\[r1, #-156\]
-0*134 <load_store\+0x134> ed ?cf ?d4 ?68 ? *	cfstrd	mvd13, ?\[pc, #416\]
+0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? *	cfstrd	mvd13, ?\[r9, #416\]
 0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? *	cfstrdcs	mvd9, ?\[r0, #-1020\]
 0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? *	cfstrdls	mvd4, ?\[r1, #-156\]
-0*140 <load_store\+0x140> dd ?ef ?74 ?68 ? *	cfstrdle	mvd7, ?\[pc, #416\]!
+0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? *	cfstrdle	mvd7, ?\[r9, #416\]!
 0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? *	cfstrdvs	mvd11, ?\[r0, #-1020\]!
 0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? *	cfstrdcc	mvd12, ?\[r1, #-156\]!
-0*14c <load_store\+0x14c> ed ?ef ?d4 ?68 ? *	cfstrd	mvd13, ?\[pc, #416\]!
+0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? *	cfstrd	mvd13, ?\[r9, #416\]!
 0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? *	cfstrdcs	mvd9, ?\[r0, #-1020\]!
 0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? *	cfstrdls	mvd4, ?\[r1\], #-156
-0*158 <load_store\+0x158> dc ?ef ?74 ?68 ? *	cfstrdle	mvd7, ?\[pc\], #416
+0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? *	cfstrdle	mvd7, ?\[r9\], #416
 0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? *	cfstrdvs	mvd11, ?\[r0\], #-1020
 0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? *	cfstrdcc	mvd12, ?\[r1\], #-156
-0*164 <load_store\+0x164> ec ?ef ?d4 ?68 ? *	cfstrd	mvd13, ?\[pc\], #416
+0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? *	cfstrd	mvd13, ?\[r9\], #416
 0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? *	cfstr32cs	mvfx9, ?\[r0, #-1020\]
 0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? *	cfstr32ls	mvfx4, ?\[r1, #-156\]
-0*170 <load_store\+0x170> dd ?8f ?75 ?68 ? *	cfstr32le	mvfx7, ?\[pc, #416\]
+0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? *	cfstr32le	mvfx7, ?\[r9, #416\]
 0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? *	cfstr32vs	mvfx11, ?\[r0, #-1020\]
 0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? *	cfstr32cc	mvfx12, ?\[r1, #-156\]
-0*17c <load_store\+0x17c> ed ?af ?d5 ?68 ? *	cfstr32	mvfx13, ?\[pc, #416\]!
+0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? *	cfstr32	mvfx13, ?\[r9, #416\]!
 0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? *	cfstr32cs	mvfx9, ?\[r0, #-1020\]!
 0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? *	cfstr32ls	mvfx4, ?\[r1, #-156\]!
-0*188 <load_store\+0x188> dd ?af ?75 ?68 ? *	cfstr32le	mvfx7, ?\[pc, #416\]!
+0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? *	cfstr32le	mvfx7, ?\[r9, #416\]!
 0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? *	cfstr32vs	mvfx11, ?\[r0, #-1020\]!
 0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? *	cfstr32cc	mvfx12, ?\[r1\], #-156
-0*194 <load_store\+0x194> ec ?af ?d5 ?68 ? *	cfstr32	mvfx13, ?\[pc\], #416
+0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? *	cfstr32	mvfx13, ?\[r9\], #416
 0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? *	cfstr32cs	mvfx9, ?\[r0\], #-1020
 0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? *	cfstr32ls	mvfx4, ?\[r1\], #-156
-0*1a0 <load_store\+0x1a0> dc ?af ?75 ?68 ? *	cfstr32le	mvfx7, ?\[pc\], #416
+0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? *	cfstr32le	mvfx7, ?\[r9\], #416
 0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? *	cfstr64vs	mvdx11, ?\[r0, #-1020\]
 0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? *	cfstr64cc	mvdx12, ?\[r1, #-156\]
-0*1ac <load_store\+0x1ac> ed ?cf ?d5 ?68 ? *	cfstr64	mvdx13, ?\[pc, #416\]
+0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? *	cfstr64	mvdx13, ?\[r9, #416\]
 0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? *	cfstr64cs	mvdx9, ?\[r0, #-1020\]
 0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? *	cfstr64ls	mvdx4, ?\[r1, #-156\]
-0*1b8 <load_store\+0x1b8> dd ?ef ?75 ?68 ? *	cfstr64le	mvdx7, ?\[pc, #416\]!
+0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? *	cfstr64le	mvdx7, ?\[r9, #416\]!
 0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? *	cfstr64vs	mvdx11, ?\[r0, #-1020\]!
 0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? *	cfstr64cc	mvdx12, ?\[r1, #-156\]!
-0*1c4 <load_store\+0x1c4> ed ?ef ?d5 ?68 ? *	cfstr64	mvdx13, ?\[pc, #416\]!
+0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? *	cfstr64	mvdx13, ?\[r9, #416\]!
 0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? *	cfstr64cs	mvdx9, ?\[r0, #-1020\]!
 0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? *	cfstr64ls	mvdx4, ?\[r1\], #-156
-0*1d0 <load_store\+0x1d0> dc ?ef ?75 ?68 ? *	cfstr64le	mvdx7, ?\[pc\], #416
+0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? *	cfstr64le	mvdx7, ?\[r9\], #416
 0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? *	cfstr64vs	mvdx11, ?\[r0\], #-1020
 0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? *	cfstr64cc	mvdx12, ?\[r1\], #-156
-0*1dc <load_store\+0x1dc> ec ?ef ?d5 ?68 ? *	cfstr64	mvdx13, ?\[pc\], #416
+0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? *	cfstr64	mvdx13, ?\[r9\], #416
 # move:
 0*1e0 <move> 2e ?09 ?04 ?50 ? *	cfmvsrcs	mvf9, ?r0
 0*1e4 <move\+0x4> 5e ?0f ?74 ?50 ? *	cfmvsrpl	mvf15, ?r7
===================================================================
Index: gas/testsuite/gas/arm/maverick.s
--- gas/testsuite/gas/arm/maverick.s	(revision 43)
+++ gas/testsuite/gas/arm/maverick.s	(revision 44)
@@ -6,121 +6,121 @@
 	cfldrsvc	mvf2, [r12, #-956]
 	cfldrslt	mvf0, [sl, #-1020]
 	cfldrscc	mvf12, [r1, #-156]
-	cfldrs	mvf13, [r15, #416]!
+	cfldrs	mvf13, [r9, #416]!
 	cfldrscs	mvf9, [r0, #-1020]!
 	cfldrsls	mvf4, [r1, #-156]!
-	cfldrsle	mvf7, [pc, #416]!
+	cfldrsle	mvf7, [r9, #416]!
 	cfldrsvs	mvf11, [r0, #-1020]!
 	cfldrscc	mvf12, [r1], #-156
-	cfldrs	mvf13, [r15], #416
+	cfldrs	mvf13, [r9], #416
 	cfldrscs	mvf9, [r0], #-1020
 	cfldrsls	mvf4, [r1], #-156
-	cfldrsle	mvf7, [pc], #416
+	cfldrsle	mvf7, [r9], #416
 	cfldrdvs	mvd11, [r0, #-1020]
 	cfldrdcc	mvd12, [r1, #-156]
-	cfldrd	mvd13, [r15, #416]
+	cfldrd	mvd13, [r9, #416]
 	cfldrdcs	mvd9, [r0, #-1020]
 	cfldrdls	mvd4, [r1, #-156]
-	cfldrdle	mvd7, [pc, #416]!
+	cfldrdle	mvd7, [r9, #416]!
 	cfldrdvs	mvd11, [r0, #-1020]!
 	cfldrdcc	mvd12, [r1, #-156]!
-	cfldrd	mvd13, [r15, #416]!
+	cfldrd	mvd13, [r9, #416]!
 	cfldrdcs	mvd9, [r0, #-1020]!
 	cfldrdls	mvd4, [r1], #-156
-	cfldrdle	mvd7, [pc], #416
+	cfldrdle	mvd7, [r9], #416
 	cfldrdvs	mvd11, [r0], #-1020
 	cfldrdcc	mvd12, [r1], #-156
-	cfldrd	mvd13, [r15], #416
+	cfldrd	mvd13, [r9], #416
 	cfldr32cs	mvfx9, [r0, #-1020]
 	cfldr32ls	mvfx4, [r1, #-156]
-	cfldr32le	mvfx7, [pc, #416]
+	cfldr32le	mvfx7, [r9, #416]
 	cfldr32vs	mvfx11, [r0, #-1020]
 	cfldr32cc	mvfx12, [r1, #-156]
-	cfldr32	mvfx13, [r15, #416]!
+	cfldr32	mvfx13, [r9, #416]!
 	cfldr32cs	mvfx9, [r0, #-1020]!
 	cfldr32ls	mvfx4, [r1, #-156]!
-	cfldr32le	mvfx7, [pc, #416]!
+	cfldr32le	mvfx7, [r9, #416]!
 	cfldr32vs	mvfx11, [r0, #-1020]!
 	cfldr32cc	mvfx12, [r1], #-156
-	cfldr32	mvfx13, [r15], #416
+	cfldr32	mvfx13, [r9], #416
 	cfldr32cs	mvfx9, [r0], #-1020
 	cfldr32ls	mvfx4, [r1], #-156
-	cfldr32le	mvfx7, [pc], #416
+	cfldr32le	mvfx7, [r9], #416
 	cfldr64vs	mvdx11, [r0, #-1020]
 	cfldr64cc	mvdx12, [r1, #-156]
-	cfldr64	mvdx13, [r15, #416]
+	cfldr64	mvdx13, [r9, #416]
 	cfldr64cs	mvdx9, [r0, #-1020]
 	cfldr64ls	mvdx4, [r1, #-156]
-	cfldr64le	mvdx7, [pc, #416]!
+	cfldr64le	mvdx7, [r9, #416]!
 	cfldr64vs	mvdx11, [r0, #-1020]!
 	cfldr64cc	mvdx12, [r1, #-156]!
-	cfldr64	mvdx13, [r15, #416]!
+	cfldr64	mvdx13, [r9, #416]!
 	cfldr64cs	mvdx9, [r0, #-1020]!
 	cfldr64ls	mvdx4, [r1], #-156
-	cfldr64le	mvdx7, [pc], #416
+	cfldr64le	mvdx7, [r9], #416
 	cfldr64vs	mvdx11, [r0], #-1020
 	cfldr64cc	mvdx12, [r1], #-156
-	cfldr64	mvdx13, [r15], #416
+	cfldr64	mvdx13, [r9], #416
 	cfstrscs	mvf9, [r0, #-1020]
 	cfstrsls	mvf4, [r1, #-156]
-	cfstrsle	mvf7, [pc, #416]
+	cfstrsle	mvf7, [r9, #416]
 	cfstrsvs	mvf11, [r0, #-1020]
 	cfstrscc	mvf12, [r1, #-156]
-	cfstrs	mvf13, [r15, #416]!
+	cfstrs	mvf13, [r9, #416]!
 	cfstrscs	mvf9, [r0, #-1020]!
 	cfstrsls	mvf4, [r1, #-156]!
-	cfstrsle	mvf7, [pc, #416]!
+	cfstrsle	mvf7, [r9, #416]!
 	cfstrsvs	mvf11, [r0, #-1020]!
 	cfstrscc	mvf12, [r1], #-156
-	cfstrs	mvf13, [r15], #416
+	cfstrs	mvf13, [r9], #416
 	cfstrscs	mvf9, [r0], #-1020
 	cfstrsls	mvf4, [r1], #-156
-	cfstrsle	mvf7, [pc], #416
+	cfstrsle	mvf7, [r9], #416
 	cfstrdvs	mvd11, [r0, #-1020]
 	cfstrdcc	mvd12, [r1, #-156]
-	cfstrd	mvd13, [r15, #416]
+	cfstrd	mvd13, [r9, #416]
 	cfstrdcs	mvd9, [r0, #-1020]
 	cfstrdls	mvd4, [r1, #-156]
-	cfstrdle	mvd7, [pc, #416]!
+	cfstrdle	mvd7, [r9, #416]!
 	cfstrdvs	mvd11, [r0, #-1020]!
 	cfstrdcc	mvd12, [r1, #-156]!
-	cfstrd	mvd13, [r15, #416]!
+	cfstrd	mvd13, [r9, #416]!
 	cfstrdcs	mvd9, [r0, #-1020]!
 	cfstrdls	mvd4, [r1], #-156
-	cfstrdle	mvd7, [pc], #416
+	cfstrdle	mvd7, [r9], #416
 	cfstrdvs	mvd11, [r0], #-1020
 	cfstrdcc	mvd12, [r1], #-156
-	cfstrd	mvd13, [r15], #416
+	cfstrd	mvd13, [r9], #416
 	cfstr32cs	mvfx9, [r0, #-1020]
 	cfstr32ls	mvfx4, [r1, #-156]
-	cfstr32le	mvfx7, [pc, #416]
+	cfstr32le	mvfx7, [r9, #416]
 	cfstr32vs	mvfx11, [r0, #-1020]
 	cfstr32cc	mvfx12, [r1, #-156]
-	cfstr32	mvfx13, [r15, #416]!
+	cfstr32	mvfx13, [r9, #416]!
 	cfstr32cs	mvfx9, [r0, #-1020]!
 	cfstr32ls	mvfx4, [r1, #-156]!
-	cfstr32le	mvfx7, [pc, #416]!
+	cfstr32le	mvfx7, [r9, #416]!
 	cfstr32vs	mvfx11, [r0, #-1020]!
 	cfstr32cc	mvfx12, [r1], #-156
-	cfstr32	mvfx13, [r15], #416
+	cfstr32	mvfx13, [r9], #416
 	cfstr32cs	mvfx9, [r0], #-1020
 	cfstr32ls	mvfx4, [r1], #-156
-	cfstr32le	mvfx7, [pc], #416
+	cfstr32le	mvfx7, [r9], #416
 	cfstr64vs	mvdx11, [r0, #-1020]
 	cfstr64cc	mvdx12, [r1, #-156]
-	cfstr64	mvdx13, [r15, #416]
+	cfstr64	mvdx13, [r9, #416]
 	cfstr64cs	mvdx9, [r0, #-1020]
 	cfstr64ls	mvdx4, [r1, #-156]
-	cfstr64le	mvdx7, [pc, #416]!
+	cfstr64le	mvdx7, [r9, #416]!
 	cfstr64vs	mvdx11, [r0, #-1020]!
 	cfstr64cc	mvdx12, [r1, #-156]!
-	cfstr64	mvdx13, [r15, #416]!
+	cfstr64	mvdx13, [r9, #416]!
 	cfstr64cs	mvdx9, [r0, #-1020]!
 	cfstr64ls	mvdx4, [r1], #-156
-	cfstr64le	mvdx7, [pc], #416
+	cfstr64le	mvdx7, [r9], #416
 	cfstr64vs	mvdx11, [r0], #-1020
 	cfstr64cc	mvdx12, [r1], #-156
-	cfstr64	mvdx13, [r15], #416
+	cfstr64	mvdx13, [r9], #416
 move:
 	cfmvsrcs	mvf9, r0
 	cfmvsrpl	mvf15, r7

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