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[patch] libopcodes: Reorder cop2 instructions for VR5400
- From: "Maciej W. Rozycki" <macro at linux-mips dot org>
- To: binutils at sources dot redhat dot com
- Date: Mon, 19 Jul 2004 16:47:52 +0200 (CEST)
- Subject: [patch] libopcodes: Reorder cop2 instructions for VR5400
Hello,
I've noticed at least one of the VR5400-specific instructions ("racm.ob")
is disassembled incorrectly due to its overlap with a cop2 one. As a
whole number of these instructions uses the cop2 range, I've decided the
safe approach is to move cop2 instructions instruction to the bottom of
the opcode table, so that VR5400 ones take precedence if disassembling
with "-m mips:5400". Here is a patch that implements it. No new
regressions and the VR5400 gas test is now "fixed".
opcodes/:
2004-07-19 Maciej W. Rozycki <macro@linux-mips.org>
* mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
move/branch operations to the bottom so that VR5400 multimedia
instructions take precedence in disassembly.
gas/testsuite/:
2004-07-19 Maciej W. Rozycki <macro@linux-mips.org>
* gas/mips/vr5400.d: Update for a correct disassembly of
"racm.ob".
OK to apply?
Maciej
binutils-2.15.91-20040715-mips-cop2.patch
diff -up --recursive --new-file binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/vr5400.d binutils-2.15.91-20040715/gas/testsuite/gas/mips/vr5400.d
--- binutils-2.15.91-20040715.macro/gas/testsuite/gas/mips/vr5400.d 2003-05-20 03:25:29.000000000 +0000
+++ binutils-2.15.91-20040715/gas/testsuite/gas/mips/vr5400.d 2004-07-18 22:24:52.000000000 +0000
@@ -119,7 +119,7 @@ Disassembly of section \.text:
0+01bc <stuff\+0x1bc> rzu\.ob \$f2,0xd
0+01c0 <stuff\+0x1c0> rach\.ob \$f2
0+01c4 <stuff\+0x1c4> racl\.ob \$f2
-0+01c8 <stuff\+0x1c8> bc2f 0+04c8 <stuff\+0x4c8>
+0+01c8 <stuff\+0x1c8> racm\.ob \$f2
0+01cc <stuff\+0x1cc> wach\.ob \$f2
0+01d0 <stuff\+0x1d0> wacl\.ob \$f2,\$f4
0+01d4 <stuff\+0x1d4> rorv a0,a1,a2
diff -up --recursive --new-file binutils-2.15.91-20040715.macro/opcodes/mips-opc.c binutils-2.15.91-20040715/opcodes/mips-opc.c
--- binutils-2.15.91-20040715.macro/opcodes/mips-opc.c 2003-11-19 04:25:23.000000000 +0000
+++ binutils-2.15.91-20040715/opcodes/mips-opc.c 2004-07-18 22:13:32.000000000 +0000
@@ -209,10 +209,7 @@ const struct mips_opcode mips_builtin_op
{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
-{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
-{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
-{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
-{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
+/* bc2* are at the bottom of the table. */
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
@@ -444,14 +441,14 @@ const struct mips_opcode mips_builtin_op
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
-{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
+/* cfc2 is at the bottom of the table. */
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
-{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
+/* ctc2 is at the bottom of the table. */
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
@@ -540,10 +537,8 @@ const struct mips_opcode mips_builtin_op
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
-{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 },
-{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 },
-{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 },
-{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 },
+/* dmfc2 is at the bottom of the table. */
+/* dmtc2 is at the bottom of the table. */
{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 },
{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 },
{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 },
@@ -741,9 +736,8 @@ const struct mips_opcode mips_builtin_op
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
-{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
-{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
-{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 },
+/* mfc2 is at the bottom of the table. */
+/* mfhc2 is at the bottom of the table. */
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, N5 },
@@ -805,9 +799,8 @@ const struct mips_opcode mips_builtin_op
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
-{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
-{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
-{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 },
+/* mtc2 is at the bottom of the table. */
+/* mthc2 is at the bottom of the table. */
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, N5 },
@@ -1187,6 +1180,25 @@ const struct mips_opcode mips_builtin_op
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
+/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
+ instructions so they are here for the latters to take precedence. */
+{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
+{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
+{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
+{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
+{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
+{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
+{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 },
+{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 },
+{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 },
+{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 },
+{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
+{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
+{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 },
+{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
+{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
+{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 },
+
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the