Re: newbie problem with sparc64 architecture

[Jim Wilson <wilson at specifixinc dot com>]

On Wed, 2004-04-28 at 09:29, Dan Kegel wrote:
> Nobody replied to that, so maybe I'll have to learn
> enough sparc64 assembly myself to decide whether this is
> a binutils problem (overeager check) or a glibc coding error.

I believe it is a glibc coding error, though I do not have a sparc
manual to double check.  Sparc instructions have a 5-bit field for
specifying registers, which means it ranges from 0 to 31.  FP
instructions which use 64-bit register pairs must use an even numbered
register.  In SPARC v9, the FP register set was extended by noticing
that since the low register bit is always zero for 64-bit FP insns, we
can use that bit to access another 16 register-pairs.  These became regs
32-63, but they can only be accessed as register pairs (or
register-quads).

So fqtoi can take %f52 as input because this is accessed as a
register-quad, but not %f60 as output.  Also, st can not take %f60 as
register input.

In the gcc sparc.md file, this is the distinction between 'e' (extended
register-pairs or quads) and 'f' (original 32 FP regs).  Note that fqtoi
takes 'e' as input and 'f' as output.
-- 
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com