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m68k (elf) gas dwarf problem
- From: "Joel Sherrill <joel at OARcorp dot com>" <joel dot sherrill at OARcorp dot com>
- To: Ralf Corsepius <corsepiu at faw dot uni-ulm dot de>, binutils at sources dot redhat dot com
- Date: Fri, 16 Apr 2004 12:48:13 -0500
- Subject: m68k (elf) gas dwarf problem
- Organization: OAR Corporation
- Reply-to: joel dot sherrill at OARcorp dot com
Hi,
Ralf and I have been trying to track down a problem which I have
tracked down enough to now beg for help. It might be a bug in
gas or in the source file but is at least not well reported
by gas since it only reports the last number in the file. :(
Attached is s1.s which is the complete preprocessed output of the
startup code for a MC68340 based board. s2.s is a cutdown to
4 lines which seems to be giving the same error.
I am using binutils 2.14 but I am pretty sure Ralf is using a 2.15-ish
binutils and getting the same problem. Anyone with an m68k/enf
target should be able to duplicate this with the attached files.
$ m68k-rtems4.7-as -mcpu32 s1.s
$ m68k-rtems4.7-as --gdwarf2 -mcpu32 s1.s
s1.s: Assembler messages:
s1.s:926: Error: unaligned opcodes detected in executable segment
So adding the --gdwarf2 results in the unaligned error.
Is this a bug or is something wrong with the assembly code?
Thanks.
--
Joel Sherrill, Ph.D. Director of Research & Development
joel@OARcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
| -- SIM equates --
.equ BASE_REG, 0x3FF00
.equ BASE_SIM, 0xEFFFF000 | pour correction du bug 68349 sur IACK
.equ SIM_MCR, 0x000 | module configuration register
.equ SIM_IDR, 0x002 | processor identification register
.equ SIM_SYNCR, 0x004 | clock synthesizer control register
.equ SIM_AVR, 0x006 | autovector register
.equ SIM_RSR, 0x007 | reset status register
| -- Port A
.equ SIM_PORTA, 0x011 | port A data
.equ SIM_DDRA, 0x013 | port A direction data
.equ SIM_PPRA1, 0x015 | Port A pin assignement 1
.equ SIM_PPRA2, 0x017 | Port A pin assignement 2
| -- Port B
.equ SIM_PORTB, 0x019 | port B data
.equ SIM_PORTB1, 0x01B | port B data auxiliary
.equ SIM_DDRB, 0x01D | port B direction data
.equ SIM_PPRB, 0x01F | Port B pin assignement
.equ SIM_SWIV, 0x020 | SW interrupt vector
.equ SIM_SYPCR, 0x021 | System protection control register
.equ SIM_PICR, 0x022 | Periodic interrupt control register
.equ SIM_PITR, 0x024 | Periodic interrupt timing register
.equ SIM_SWSR, 0x027 | Sofware service
| -- Chip select
.equ SIM_MASKH0, 0x040 | mask register CS0
.equ SIM_MASKL0, 0x042 | mask register CS0
.equ SIM_ADDRH0, 0x044 | base address CS0
.equ SIM_ADDRL0, 0x046 | base address CS0
.equ SIM_MASKH1, 0x048 | mask register CS1
.equ SIM_MASKL1, 0x04A | mask register CS1
.equ SIM_ADDRH1, 0x04C | base address CS1
.equ SIM_ADDRL1, 0x04E | base address CS1
.equ SIM_MASKH2, 0x050 | mask register CS2
.equ SIM_MASKL2, 0x052 | mask register CS2
.equ SIM_ADDRH2, 0x054 | base address CS2
.equ SIM_ADDRL2, 0x056 | base address CS2
.equ SIM_MASKH3, 0x058 | mask register CS3
.equ SIM_MASKL3, 0x05A | mask register CS3
.equ SIM_ADDRH3, 0x05C | base address CS3
.equ SIM_ADDRL3, 0x05E | base address CS3
| -- TIMERS equates --
| __ TIMER 0
.equ TIM_MCR0, 0x600 | Module configuration register
.equ TIM_IR0, 0x604 | interrupt register
.equ TIM_CR0, 0x606 | controle register
.equ TIM_SR0, 0x608 | Status/prescaler register
.equ TIM_CNTR0, 0x60A | counter register
.equ TIM_PREL10, 0x60C | Preload register 1
.equ TIM_PREL20, 0x60E | Preload register 2
.equ TIM_COM0, 0x610 | Compare register
| __ TIMER 1
.equ TIM_MCR1, 0x640 | Module configuration register
.equ TIM_IR1, 0x644 | interrupt register
.equ TIM_CR1, 0x646 | controle register
.equ TIM_SR1, 0x648 | Status/prescaler register
.equ TIM_CNTR1, 0x64A | counter register
.equ TIM_PREL11, 0x64C | Preload register 1
.equ TIM_PREL21, 0x64E | Preload register 2
.equ TIM_COM1, 0x650 | Compare register
| -- U.A.R.T. equates --
.equ UA_MCRH, 0x700 | module configuration register
.equ UA_MCRL, 0x701 | module configuration register
.equ UA_ILR, 0x704 | Interrupt level
.equ UA_IVR, 0x705 | Interrupt vector
.equ UA_MR1A, 0x710 | Mode register 1 A
.equ UA_MR2A, 0x720 | Mode register 2 A
.equ UA_CSRA, 0x711 | Clock_select regiter A
.equ UA_SRA, 0x711 | status register A
.equ UA_CRA, 0x712 | command register A
.equ UA_RBA, 0x713 | receive buffer A
.equ UA_TBA, 0x713 | transmit buffer A
.equ UA_IPCR, 0x714 | input port change register
.equ UA_ACR, 0x714 | auxiliary control register
.equ UA_ISR, 0x715 | interrupt status register
.equ UA_IER, 0x715 | interrupt enable register
.equ UA_MR1B, 0x718 | Mode register 1 B
.equ UA_MR2B, 0x721 | Mode register 2 B
.equ UA_CSRB, 0x719 | Clock_select regiter B
.equ UA_SRB, 0x719 | status register B
.equ UA_CRB, 0x71A | command register A
.equ UA_RBB, 0x71B | receive buffer A
.equ UA_TBB, 0x71B | transmit buffer A
.equ UA_IP, 0x71D | Input port register
.equ UA_OPCR, 0x71D | output port control register
.equ UA_OPS, 0x71E | output port bit set
.equ UA_OPR, 0x71F | output port bit reset
.equ TX_A_EN, 0x01 | Tx A irq enable
.equ TX_B_EN, 0x10 | Tx B irq enable
.equ TX_A_DIS, 0xFE | Tx A irq enable
.equ TX_B_DIS, 0xEF | Tx B irq enable
.equ TX_AB_DIS, 0x22
| -- DMA equates
.equ DMA_MCR0, 0x780 | module configuration register
.equ DMA_IR0, 0x784 | Interrupt register
.equ DMA_CCR0, 0x788 | Channel control register
.equ DMA_CSR0, 0x78A | Channel status register
.equ DMA_FCR0, 0x78B | Function code register
.equ DMA_SARH0, 0x78C | Source adresse register
.equ DMA_SARL0, 0x78E | Source adresse register
.equ DMA_DARH0, 0x790 | destination adresse register
.equ DMA_DARL0, 0x792 | destination adresse register
.equ DMA_BTCH0, 0x794 | byte transfer register
.equ DMA_BTCL0, 0x796 | byte transfer register
.equ DMA_MCR1, 0x7A0 | module configuration register
.equ DMA_IR1, 0x7A4 | Interrupt register
.equ DMA_CCR1, 0x7A8 | Channel control register
.equ DMA_CSR1, 0x7AA | Channel status register
.equ DMA_FCR1, 0x7AB | Function code register
.equ DMA_SARH1, 0x7AC | Source adresse register
.equ DMA_SARL1, 0x7AE | Source adresse register
.equ DMA_DARH1, 0x7B0 | destination adresse register
.equ DMA_DARL1, 0x7B2 | destination adresse register
.equ DMA_BTCH1, 0x7B4 | byte transfer register
.equ DMA_BTCL1, 0x7B6 | byte transfer register
| -- cache equates
.equ CACHE_MCR, 0xFC0 | cache config reg. (long)
| -- quad data memory module (QDMM) equates
.equ QDMM_MCR, 0xC00 | QDMM config reg (long)
.equ QDMM_QBAR0, 0xC10 | QDMM base 0 (long)
.equ QDMM_QBAR1, 0xC14 | QDMM base 1 (long)
.equ QDMM_QBAR2, 0xC18 | QDMM base 2 (long)
.equ QDMM_QBAR3, 0xC1C | QDMM base 3 (long)
|-----------------------------------------------------
| AST68349 internal registers
|-----------------------------------------------------
.equ EPLD_SPACE, 3 | "reserved user" space
.equ CPU_SPACE, 7 | "CPU" space
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| GLUE EPLD
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
.equ GLUE_EPLD, 0xB0000000
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of /CS0 :
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena|val|wid| ws|b31|b30|b29|b28|
| +---+---+---+---+---+---+---+---+
|
| b[31..28] : base address for decoding /CS[3..0]
| the decoding is as follow :
|
| +----------+------------+------+
| | a[31..28] | a[27..26] | /CS |
| +-----------+-----------+------+
| | b[31..28] | 00 | /CS0 | each /CS decodes 64 Mbytes
| | b[31..28] | 01 | /CS1 |
| | b[31..28] | 10 | /CS2 |
| | b[31..28] | 11 | /CS3 |
| +-----------------------+------+
|
| after /RESET, /CS0 is validated for every cycle, until programmed
|
| ws : number of wait-states : 0 => 0 ws
| 1 => external /dsackx
| wid : width of chip-select : 0 => 16 bits
| 1 => 32 bits
| ena : enable chip-select : 0 => disabled
| 1 => enabled
|
| val : automatic validation. set after reset
| cleared when /CS0 is configured
|
.equ REG_CS0, 0
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of /CS1 to /CS3:
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x |wid| ws| x | x | x | x |
| +---+---+---+---+---+---+---+---+
|
| ws : number of wait-states : 0 => 0 ws
| 1 => external /dsackx
| wid : width of chip-select : 0 => 16 bits
| 1 => 32 bits
| ena : enable chip-select : 0 => disabled
| 1 => enabled
.equ REG_CS1, 1
.equ REG_CS2, 2
.equ REG_CS3, 3
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| I2C register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+----+
| | x | x | x | x | x | x |clk|data|
| +---+---+---+---+---+---+---+----+
| bidirecionnal pin, open drain output.
| set bit to 1 to read external state of pin
|
.equ REG_I2C, 4
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| PDCS register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |s12|s11|s14|pd5|pd4|pd3|pd2|pd1|
| +---+---+---+---+---+---+---+---+
| pd[5..1] : value read on the DRAM module
| S12, S11 and S14 : "user reserved" configuration switch
|
.equ REG_PDCS, 5
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| timer1 register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x | x | x | x | x | %d1| %d0|
| +---+---+---+---+---+---+---+---+
|
| the timer clock is the 1000Hz clock of the ASTECC platform
| the timer is reloaded on each write to the register, or if the input
| TIN1 is set to 0.
| on overflow, the open drain output TOUT1 is set to 0
| the timer must be disabled to return TOUT1 to the inactive state
|
.equ REG_TIMER1, 6
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| timer2 register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x | x | x | x | x | %d1| %d0|
| +---+---+---+---+---+---+---+---+
| the timer clock is the 1000Hz clock of the ASTECC platform
| the timer is reloaded on each write to the register, or if the input
| TIN2 is set to 0.
| on overflow, the open drain output TOUT2 is set to 0
| the timer must be disabled to return TOUT2 to the inactive state
|
.equ REG_TIMER2, 7
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| baudrate generator register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x | %d2| %d1| %d0|
| +---+---+---+---+---+---+---+---+
|
| d[2..0] : divider of a 3.6864 Mhz clock
|
| d[2..0] : 0 1 2 3 4 5 6 7
| divides by : 2 4 6 8 10 12 14 16
| SCLK (Mhz) : 1.8432 0.9216 0.6144 0.4608 x 0.3072 x 0.2304
| baudrate : 115200 57600 38400 28800 x 19200 x 14400
|
.equ REG_BAUDRATE, 8
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| IO register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x |io4|io3|io2|io1|io0|
| +---+---+---+---+---+---+---+---+
|
| io[4..0] : data written to port
|
| maximum current load is about 5 mA per pin
|
.equ REG_IO, 9
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| IO port
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x |io4|io3|io2|io1|io0|
| +---+---+---+---+---+---+---+---+
|
| io[4..0] : data read from port
|
.equ REG_IO_PORT, 10
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| IO direction register
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x |dr2|dr1|dr0|
| +---+---+---+---+---+---+---+---+
|
| dr0 : 0 => io port 0 is configured as input (default after /RESET)
| 1 => io port 0 is configured as output
|
| dr1 : 0 => io port 1 is configured as input (default after /RESET)
| 1 => io port 1 is configured as output
|
| dr2 : 0 => io ports 2 to 4 are configured as input (default after /RESET)
| 1 => io ports 2 to 4 are configured as output
|
.equ REG_DIR_IO, 11
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DRAM EPLD
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
.equ DRAM_EPLD, 0xA0000000
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| number of wait-state for DRAM
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x | x |ws1|ws0|
| +---+---+---+---+---+---+---+---+
|
| ws[1..0] : 0 1 2 3
| wait states : 0 1 2 3
|
.equ REG_WS, 0
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of refresh for DRAM
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |ena| x | x | x | x | x |rf1|rf0|
| +---+---+---+---+---+---+---+---+
|
| rf[1..0] : 0 1 2 3
| refresh : 5µs 10µs 15µs 20µs
|
| ena == 0 : refresh disabled
| ena == 1 : refresh enabled
|
.equ REG_REFRESH, 1
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| configuration of DRAM module size
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| | x | x | x | x | x |sz2|sz1|sz0|
| +---+---+---+---+---+---+---+---+
|
| sz[2..0] : 0 1 2 3 4 5 6 7
| size (Mbytes): 4 8 16 32 64 128 0 0
|
.equ REG_CONFIG, 2
|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| bus width of /CS0 during reset bw[1..0] : 0 1 2 3
| bus width : 32 16 8 ext. /dsackx
|
| state of CS_SWITCH : sel == 0 => CPU chip_selects (/CS[3..0])
| : sel == 1 => EPLD chip_selects (/CS[3..0])
|
| 7 6 5 4 3 2 1 0
| +---+---+---+---+---+---+---+---+
| |bw1|bw0| x | x | x | x | x |sel|
| +---+---+---+---+---+---+---+---+
|
.equ REG_BUSWIDTH, 3
.text
Entry:
.long m340+1024 | 0: Initial SSP
.long start | 1: Initial PC
.long _uhoh | 2: Bus error
.long _uhoh | 3: Address error
.long _uhoh | 4: Illegal instruction
.long _uhoh | 5: Zero division
.long _uhoh | 6: CHK, CHK2 instruction
.long _uhoh | 7: TRAPcc, TRAPV instructions
.long _uhoh | 8: Privilege violation
.long _uhoh | 9: Trace
.long _uhoh | 10: Line 1010 emulator
.long _uhoh | 11: Line 1111 emulator
.long _uhoh | 12: Hardware breakpoint
.long _uhoh | 13: Reserved for coprocessor violation
.long _uhoh | 14: Format error
.long _uhoh | 15: Uninitialized interrupt
.long _uhoh | 16: Unassigned, reserved
.long _uhoh | 17:
.long _uhoh | 18:
.long _uhoh | 19:
.long _uhoh | 20:
.long _uhoh | 21:
.long _uhoh | 22:
.long _uhoh | 23:
.long _spuriousInterrupt | 24: Spurious interrupt
.long _uhoh | 25: Level 1 interrupt autovector
.long _uhoh | 26: Level 2 interrupt autovector
.long _uhoh | 27: Level 3 interrupt autovector
.long _uhoh | 28: Level 4 interrupt autovector
.long _uhoh | 29: Level 5 interrupt autovector
.long _uhoh | 30: Level 6 interrupt autovector
.long _uhoh | 31: Level 7 interrupt autovector
.long _uhoh | 32: Trap instruction (0-15)
.long _uhoh | 33:
.long _uhoh | 34:
.long _uhoh | 35:
.long _uhoh | 36:
.long _uhoh | 37:
.long _uhoh | 38:
.long _uhoh | 39:
.long _uhoh | 40:
.long _uhoh | 41:
.long _uhoh | 42:
.long _uhoh | 43:
.long _uhoh | 44:
.long _uhoh | 45:
.long _uhoh | 46:
.long _uhoh | 47:
.long _uhoh | 48: Reserved for coprocessor
.long _uhoh | 49:
.long _uhoh | 50:
.long _uhoh | 51:
.long _uhoh | 52:
.long _uhoh | 53:
.long _uhoh | 54:
.long _uhoh | 55:
.long _uhoh | 56:
.long _uhoh | 57:
.long _uhoh | 58:
.long _uhoh | 59: Unassigned, reserved
.long _uhoh | 60:
.long _uhoh | 61:
.long _uhoh | 62:
.long _uhoh | 63:
.long _uhoh | 64: User defined vectors (192)
.long _uhoh | 65:
.long _uhoh | 66:
.long _uhoh | 67:
.long _uhoh | 68:
.long _uhoh | 69:
.long _uhoh | 70:
.long _uhoh | 71:
.long _uhoh | 72:
.long _uhoh | 73:
.long _uhoh | 74:
.long _uhoh | 75:
.long _uhoh | 76:
.long _uhoh | 77:
.long _uhoh | 78:
.long _uhoh | 79:
.long _uhoh | 80:
.long _uhoh | 81:
.long _uhoh | 82:
.long _uhoh | 83:
.long _uhoh | 84:
.long _uhoh | 85:
.long _uhoh | 86:
.long _uhoh | 87:
.long _uhoh | 88:
.long _uhoh | 89:
.long _uhoh | 90:
.long _uhoh | 91:
.long _uhoh | 92:
.long _uhoh | 93:
.long _uhoh | 94:
.long _uhoh | 95:
.long _uhoh | 96:
.long _uhoh | 97:
.long _uhoh | 98:
.long _uhoh | 99:
.long _uhoh | 100:
.long _uhoh | 101:
.long _uhoh | 102:
.long _uhoh | 103:
.long _uhoh | 104:
.long _uhoh | 105:
.long _uhoh | 106:
.long _uhoh | 107:
.long _uhoh | 108:
.long _uhoh | 109:
.long _uhoh | 110:
.long _uhoh | 111:
.long _uhoh | 112:
.long _uhoh | 113:
.long _uhoh | 114:
.long _uhoh | 115:
.long _uhoh | 116:
.long _uhoh | 117:
.long _uhoh | 118:
.long _uhoh | 119:
.long _uhoh | 120:
.long _uhoh | 121:
.long _uhoh | 122:
.long _uhoh | 123:
.long _uhoh | 124:
.long _uhoh | 125:
.long _uhoh | 126:
.long _uhoh | 127:
.long _uhoh | 128:
.long _uhoh | 129:
.long _uhoh | 130:
.long _uhoh | 131:
.long _uhoh | 132:
.long _uhoh | 133:
.long _uhoh | 134:
.long _uhoh | 135:
.long _uhoh | 136:
.long _uhoh | 137:
.long _uhoh | 138:
.long _uhoh | 139:
.long _uhoh | 140:
.long _uhoh | 141:
.long _uhoh | 142:
.long _uhoh | 143:
.long _uhoh | 144:
.long _uhoh | 145:
.long _uhoh | 146:
.long _uhoh | 147:
.long _uhoh | 148:
.long _uhoh | 149:
.long _uhoh | 150:
.long _uhoh | 151:
.long _uhoh | 152:
.long _uhoh | 153:
.long _uhoh | 154:
.long _uhoh | 155:
.long _uhoh | 156:
.long _uhoh | 157:
.long _uhoh | 158:
.long _uhoh | 159:
.long _uhoh | 160:
.long _uhoh | 161:
.long _uhoh | 162:
.long _uhoh | 163:
.long _uhoh | 164:
.long _uhoh | 165:
.long _uhoh | 166:
.long _uhoh | 167:
.long _uhoh | 168:
.long _uhoh | 169:
.long _uhoh | 170:
.long _uhoh | 171:
.long _uhoh | 172:
.long _uhoh | 173:
.long _uhoh | 174:
.long _uhoh | 175:
.long _uhoh | 176:
.long _uhoh | 177:
.long _uhoh | 178:
.long _uhoh | 179:
.long _uhoh | 180:
.long _uhoh | 181:
.long _uhoh | 182:
.long _uhoh | 183:
.long _uhoh | 184:
.long _uhoh | 185:
.long _uhoh | 186:
.long _uhoh | 187:
.long _uhoh | 188:
.long _uhoh | 189:
.long _uhoh | 190:
.long _uhoh | 191:
.long _uhoh | 192:
.long _uhoh | 193:
.long _uhoh | 194:
.long _uhoh | 195:
.long _uhoh | 196:
.long _uhoh | 197:
.long _uhoh | 198:
.long _uhoh | 199:
.long _uhoh | 200:
.long _uhoh | 201:
.long _uhoh | 202:
.long _uhoh | 203:
.long _uhoh | 204:
.long _uhoh | 205:
.long _uhoh | 206:
.long _uhoh | 207:
.long _uhoh | 208:
.long _uhoh | 209:
.long _uhoh | 210:
.long _uhoh | 211:
.long _uhoh | 212:
.long _uhoh | 213:
.long _uhoh | 214:
.long _uhoh | 215:
.long _uhoh | 216:
.long _uhoh | 217:
.long _uhoh | 218:
.long _uhoh | 219:
.long _uhoh | 220:
.long _uhoh | 221:
.long _uhoh | 222:
.long _uhoh | 223:
.long _uhoh | 224:
.long _uhoh | 225:
.long _uhoh | 226:
.long _uhoh | 227:
.long _uhoh | 228:
.long _uhoh | 229:
.long _uhoh | 230:
.long _uhoh | 231:
.long _uhoh | 232:
.long _uhoh | 233:
.long _uhoh | 234:
.long _uhoh | 235:
.long _uhoh | 236:
.long _uhoh | 237:
.long _uhoh | 238:
.long _uhoh | 239:
.long _uhoh | 240:
.long _uhoh | 241:
.long _uhoh | 242:
.long _uhoh | 243:
.long _uhoh | 244:
.long _uhoh | 245:
.long _uhoh | 246:
.long _uhoh | 247:
.long _uhoh | 248:
.long _uhoh | 249:
.long _uhoh | 250:
.long _uhoh | 251:
.long _uhoh | 252:
.long _uhoh | 253:
.long _uhoh | 254:
.long _uhoh | 255:
.globl _uhoh
_uhoh: nop | Leave spot for breakpoint
move.w #0x2700,%sr
move.w (%a7),_boot_panic_registers+4 | SR
move.l 2(%a7),_boot_panic_registers | PC
move.w 6(%a7),_boot_panic_registers+6 | format & vector
movem.l %d0-%d7/%a0-%a7, _boot_panic_registers+8
movec %sfc, %d0
movem.l %d0, _boot_panic_registers+72
movec %dfc, %d0
movem.l %d0, _boot_panic_registers+76
movec %vbr, %d0
movem.l %d0, _boot_panic_registers+80
jmp _dbug_dumpanic
bra.s _crt0_cold_start
.globl _spuriousInterrupt
_spuriousInterrupt:
addql #1,_M68kSpuriousInterruptCount
rte
.align 2
.word 0 | Padding
ethernet_address_buffer:
.word 0x08F3 | Default address
.word 0xDEAD
.word 0xCAFE
.data
.equ _CPU340, 0x0
.equ _CPU349, 0x31
.equ _EPLD_CS_BASE, 0x1
.equ _PROM_Start, 0x01000000
.equ _FLEX_Start, 0x08000000
.equ _I2C_Start, 0x0c000000
.equ _BCCram_Start, 0x00000000
.equ _BCCram_Size, 0x00010000
.equ _ExtRam_Start, 0x10000000
.equ _ExtRam_Size, 0x00400000
.equ _FastRam_Start, 0x00000000
.equ _FastRam_Size, 0x00001000
.equ _SPEED349, 0xD680
.equ _SPEED340, 0xD700
.equ pdcs_mask, 0x1F
.equ pdcs_sw12, 7
.equ pdcs_sw11, 6
.equ pdcs_sw14, 5
.equ bit_cache, pdcs_sw12
.equ bit_meminit, pdcs_sw11
_AsteccBusWidth: ds.b 1
_AsteccCsSwitch: ds.b 1
_AsteccCpuName: ds.l 1
.align 4
_crt0_init_stack:
ds.l 500
_crt0_init_stktop:
.text
.align 4
dc.l _crt0_init_stktop
dc.l _crt0_cold_start
dc.l _crt0_warm_start
.ascii "BOOT XHM68K/Spectra for ASTECC 68349 and 68340 boards"
dc.w 0
.align 4
.globl start
start:
_crt0_cold_start:
moveq.l #0,%d0 | signal cold reset
bra.s _crt0_common_start
_crt0_warm_start:
moveq.l #1,%d0 | signal warm reset
_crt0_common_start:
move.w #0x2700,%sr | disable interrupts and switch to interrupt mode
movea.l #_crt0_init_stktop,%sp | set up initialization stack
move.l #Entry,%d1 | VBR initialization
movec.l %d1,%vbr |
moveq.l #0x07,%d1
movec.l %d1,%dfc | prepare access in CPU space
move.l #(BASE_SIM+0x111),%d1 | mask CPU, RESERVED USER SPACES
moves.l %d1,BASE_REG | base initialization (must be MOVES, PCC-130795)
movea.l #BASE_SIM,%a0
move.b #0,SIM_SYPCR(%a0) | system protection control register
clr.b SIM_PPRA1(%a0)
move.w #0x427F,SIM_MCR(%a0)
move.b #0xE8,SIM_PPRB(%a0)
move.b #0x80,SIM_AVR(%a0)
cmp.b #_CPU349,SIM_IDR(%a0)
bne cpu_is_68340
cpu_is_68349:
move.w #_SPEED349,SIM_SYNCR(%a0) | clock
sync_wait349:
btst.b #3,(SIM_SYNCR+1)(%a0)
beq sync_wait349
move.l #0x00000000,QDMM_MCR(%a0)
move.l #_FastRam_Start+0x0005,QDMM_QBAR0(%a0)
move.l #_FastRam_Start+0x0405,QDMM_QBAR1(%a0)
move.l #_FastRam_Start+0x0805,QDMM_QBAR2(%a0)
move.l #_FastRam_Start+0x0c05,QDMM_QBAR3(%a0)
lea.l _copy_start_code(%pc),%a3
lea.l _copy_end_code(%pc),%a4
move.l %a4,%d1
sub.l %a3,%d1
add.l #3,%d1 | adjust to next long word
lsr.l #2,%d1
move.l #_FastRam_Start,%a4
_copy_loop:
move.l (%a3)+,(%a4)+
subq.l #1,%d1
bne.s _copy_loop
bra.l _FastRam_Start | jump to code in internal RAM
_copy_start_code:
bra.l _begin_68349_init
_table_csepld:
dc.b (_EPLD_CS_BASE&0x0F)+0x80 | 16 bits, 0ws
dc.b 0x80 | 16 bits, 0 ws
dc.b 0x90 | 16 bits, ext /dsack
dc.b 0x90 | 16 bits, ext /dsack
_table_cs349:
dc.l 0x003FFFF4 | Mask CS0 (4Mbytes PROM, 32bits, 1WS)
dc.l (_PROM_Start&0xFFFFFF00)+0x00000003 | Base CS0
dc.l 0x003FFFF1 | MASK CS1 (4Mbytes RAM, 16bits, 0WS)
dc.l (_BCCram_Start&0xFFFFFF00)+0x00000003 | Base CS1
dc.l 0x000000FF | MASK CS2 (FLEX, ext DTACK, 256 bytes)
dc.l (_FLEX_Start&0xFFFFFF00)+0x00000003 | Base CS2
dc.l 0x000000FF | Mask CS3 (I2C, ext DTACK, 256 bytes)
dc.l (_I2C_Start&0xFFFFFF00)+0x00000003 | Base CS3
_begin_68349_init:
_cs68349_init:
lea.l SIM_MASKH0(%a0),%a4
lea.l _table_cs349(%pc),%a3
moveq.l #0x07,%d1
_cs349_init2:
move.l (%a3)+,(%a4)+
dbra %d1,_cs349_init2
moveq.l #EPLD_SPACE,%d1
movec.l %d1,%dfc
movec.l %d1,%sfc
move.l #GLUE_EPLD,%a1
move.l #DRAM_EPLD,%a2
_csepld_clear:
move.l %a1,%a4
move.w #3,%d6
clr.b %d1
_csepld_clear1:
moves.b %d1,(%a4)+
dbra %d6,_csepld_clear1
moves.b REG_BUSWIDTH(%a2),%d3
move.b %d3,%d4
and.b #1,%d3
rol.b #2,%d4
and.b #3,%d4
lea.l SIM_MASKH0(%a0),%a4
lea.l _table_cs349(%pc),%a3
move.l (%a3)+,%d1
and.b #0xFC,%d1 | clear PS0 & PS1
or.b %d4,%d1 | set boot PROM bus width
move.l %d1,(%a4)+
moves.b REG_PDCS(%a1),%d5
btst.b #0,%d3
beq _cs_init_end
lea.l SIM_MASKH0(%a0),%a4
lea.l _table_cs349(%pc),%a3
moveq.l #0x03,%d1
_cs349_clear:
move.l (%a3)+,(%a4)+
move.l (%a3)+,%d6
and.b #0xFE,%d6 | disable chip-select
move.l %d6,(%a4)+
dbra %d1,_cs349_clear
_csepld_init:
move.l %a1,%a4
lea.l _table_csepld(%pc),%a3
move.b (%a3)+,%d1
or.b #0x20,%d1 | default width is 32 bits
tst.b %d4 | is boot PROM bus width 32 bits ?
beq _csepld1 | if not
and.b #0xDF,%d1 | set width to 16 bits
_csepld1:
moves.b %d1,(%a4)+
moveq.l #0x02,%d6
_csepld2:
move.b (%a3)+,%d1
moves.b %d1,(%a4)+
dbra %d6,_csepld2
_cs_init_end:
_dram_init:
move.w #15,%d1
move.l #_ExtRam_Start,%a3
_dram_init1:
clr.l (%a3)+ | must access DRAM
dbra %d1,_dram_init1 | prior to init refresh
_dram_init2:
move.b #3,%d1
moves.b %d1,REG_WS(%a2) | set 3 wait-states
move.b #0x81,%d1
moves.b %d1,REG_REFRESH(%a2) | refresh every 10µs
move.b #0,%d1
moves.b %d1,REG_CONFIG(%a2) | default size = 4Mbytes
_init_cache:
move.l #0x000001E0,CACHE_MCR(%a0)
btst.b #bit_cache,%d5
bne _init_cache_end
or.l #0x00000001,CACHE_MCR(%a0)
_init_cache_end:
clr.b %d1
moves.b %d1,REG_TIMER1(%a1) | disable timer 1
moves.b %d1,REG_TIMER2(%a1) | disable timer 2
move.b #3,%d1
moves.b %d1,REG_I2C(%a1) | tri-states I2C ports
move.b #2,%d1
moves.b %d1,REG_BAUDRATE(%a1) | baudrate = 38400
clr.b %d1
moves.b %d1,REG_IO(%a1) | set port as input
move.l #68349,%d2
jmp.l (_fill_test) | must be absolute long
_copy_end_code:
_table_cs340:
dc.l 0x003FFFF0
dc.l ((_PROM_Start&0xFFFFFF00)+0x00000003)
dc.l 0x0000FFFD
dc.l ((_BCCram_Start&0xFFFFFF00)+0x00000003)
dc.l 0x000000FF
dc.l ((_FLEX_Start&0xFFFFFF00)+0x00000003)
dc.l 0x000000FF
dc.l ((_I2C_Start&0xFFFFFF00)+0x00000003)
cpu_is_68340:
move.w #_SPEED340,SIM_SYNCR(%a0) | clock
sync_wait340:
btst.b #3,(SIM_SYNCR+1)(%a0)
beq sync_wait340
lea.l SIM_MASKH0(%a0),%a4
lea.l _table_cs340(%pc),%a3
moveq.l #0x07,%d1
_b_cs340:
move.l (%a3)+,%a5
move.l %a5,(%a4)+ | pour test
dbra %d1,_b_cs340
move.l #68340,%d2
move.b #0,%d3 | CPU
move.b #1,%d4 | 16 bits
_fill_test:
tst.l %d0
bne _dont_fill
cmp.b #_CPU349,SIM_IDR(%a0)
bne _fill
btst.b #bit_meminit,%d5
bne _dont_fill
_fill:
move.l #_crt0_init_stack,%a3 | skip Astecc vars
move.l #_ExtRam_Start,%d1
sub.l #_crt0_init_stack,%d1
add.l #_ExtRam_Size,%d1 | get size
lsr.l #2,%d1 | ajust for long word
_fill_loop:
clr.l (%a3)+
subq.l #1,%d1
bne _fill_loop
cmp.b #_CPU349,SIM_IDR(%a0)
bne _fill_bccram
movea.l #_FastRam_Start,%a3 | get start
move.l #_FastRam_Size,%d1 | get size
lsr.l #2,%d1 | ajust for long word
_QDMMfill_loop:
clr.l (%a3)+
subq.l #1,%d1
bne _QDMMfill_loop
bra _dont_fill
_fill_bccram:
movea.l #_BCCram_Start,%a3 | get start
move.l #_BCCram_Size,%d1 | get size
lsr.l #2,%d1 | ajust for long word
_BCCfill_loop:
clr.l (%a3)+
subq.l #1,%d1
bne _BCCfill_loop
*-------------------------------------------------*/
_dont_fill:
move.b %d3,_AsteccCsSwitch
move.b %d4,_AsteccBusWidth
move.l %d2,_AsteccCpuName
jmp _Init68340 | Start C code (which never returns)
.globl _CopyDataClearBSSAndStart
_CopyDataClearBSSAndStart:
lea _copy_start,%a0 | Get start of DATA in RAM
lea _etext,%a2 | Get start of DATA in ROM
cmpl %a0,%a2 | Are they the same?
beq.s NOCOPY | Yes, no copy necessary
lea _copy_end,%a1 | Get end of DATA in RAM
bra.s COPYLOOPTEST | Branch into copy loop
COPYLOOP:
movel %a2@+,%a0@+ | Copy word from ROM to RAM
COPYLOOPTEST:
cmpl %a1,%a0 | Done?
bcs.s COPYLOOP | No, skip
NOCOPY:
lea _clear_start,%a0 | Get start of BSS
lea _clear_end,%a1 | Get end of BSS
clrl %d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel %d0,%a0@+ | Clear a word
ZEROLOOPTEST:
cmpl %a1,%a0 | Done?
bcs.s ZEROLOOP | No, skip
movel #_stack_init,%a7 | set master stack pointer
movel %d0,%a7@- | environp
movel %d0,%a7@- | argv
movel %d0,%a7@- | argc
jsr boot_card | Call C main
.globl _mainDone
_mainDone:
nop | Leave spot for breakpoint
movew #1,%a7 | Force a double bus error
movel %d0,%a7@- | This should cause a RESET
move.w #0x2700,%sr
bra.l _mainDone | Stuck forever
.align 2
.data
.align 2
.globl environ
environ:
.long 0
.globl _M68kSpuriousInterruptCount
_M68kSpuriousInterruptCount:
.long 0
.data
.align 4
_AsteccBusWidth: ds.b 1
_AsteccCsSwitch: ds.b 1
_AsteccCpuName: ds.l 1