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[rfa] Add sh64 files to src/cpu/
- From: Andrew Cagney <ac131313 at redhat dot com>
- To: binutils at sources dot redhat dot com
- Cc: Joern Rennecke <renneckej at superh dot com>
- Date: Thu, 19 Feb 2004 11:05:45 -0500
- Subject: [rfa] Add sh64 files to src/cpu/
Hello,
With the attached Red Hat is contributing the sh64 input files to the
FSF. Joern will follow up with a patch adding more recent SuperH changes.
Is this part ok to commit?
Andrew
2004-02-19 Andrew Cagney <cagney@redhat.com>
* sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
written by Ben Elliston.
Index: sh.cpu
===================================================================
RCS file: sh.cpu
diff -N sh.cpu
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sh.cpu 19 Feb 2004 16:01:26 -0000
@@ -0,0 +1,368 @@
+; Hitachi SH architecture description. -*- Scheme -*-
+;
+; Copyright 2000, 2001 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Hitachi
+; Semiconductor (America) Inc.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+
+(include "simplify.inc")
+
+(define-arch
+ (name sh)
+ (comment "Hitachi SuperH (SH)")
+ (insn-lsb0? #t)
+ (machs sh2 sh3 sh3e sh4 sh5)
+ (isas compact media)
+)
+
+
+; Instruction sets.
+
+(define-isa
+ (name media)
+ (comment "SHmedia 32-bit instruction set")
+ (base-insn-bitsize 32)
+)
+
+(define-isa
+ (name compact)
+ (comment "SHcompact 16-bit instruction set")
+ (base-insn-bitsize 16)
+)
+
+
+; CPU family.
+
+(define-cpu
+ (name sh64)
+ (comment "SH 64-bit family")
+ (endian either)
+ (word-bitsize 32)
+)
+
+
+(define-mach
+ (name sh2)
+ (comment "SH-2 CPU core")
+ (cpu sh64)
+ (isas compact)
+)
+
+(define-mach
+ (name sh3)
+ (comment "SH-3 CPU core")
+ (cpu sh64)
+ (isas compact)
+)
+
+(define-mach
+ (name sh3e)
+ (comment "SH-3e CPU core")
+ (cpu sh64)
+ (isas compact)
+)
+
+(define-mach
+ (name sh4)
+ (comment "SH-4 CPU core")
+ (cpu sh64)
+ (isas compact)
+)
+
+(define-mach
+ (name sh5)
+ (comment "SH-5 CPU core")
+ (cpu sh64)
+ (isas compact media)
+)
+
+(define-model
+ (name sh5)
+ (comment "SH-5 reference implementation")
+ (mach sh5)
+ (unit u-exec "Execution unit" ()
+ 1 1 ; issue done
+ () () () ())
+)
+
+; Hardware elements.
+
+(define-hardware
+ (name h-pc)
+ (comment "Program counter")
+ (attrs PC (ISA compact,media))
+ (type pc UDI)
+ (get () (raw-reg h-pc))
+ (set (newval) (sequence ()
+ (set (raw-reg h-ism) (and newval 1))
+ (set (raw-reg h-pc) (and newval (inv UDI 1)))))
+)
+
+(define-pmacro (-build-greg-name n) ((.sym r n) n))
+
+(define-hardware
+ (name h-gr)
+ (comment "General purpose integer registers")
+ (attrs (ISA media,compact))
+ (type register DI (64))
+ (indices keyword "" (.map -build-greg-name (.iota 64)))
+ (get (index)
+ (if DI (eq index 63)
+ (const 0)
+ (raw-reg h-gr index)))
+ (set (index newval)
+ (if (ne index 63)
+ (set (raw-reg h-gr index) newval)
+ (nop)))
+)
+
+(define-hardware
+ (name h-grc)
+ (comment "General purpose integer registers (SHcompact view)")
+ (attrs VIRTUAL (ISA compact))
+ (type register SI (16))
+ (indices keyword "" (.map -build-greg-name (.iota 16)))
+ (get (index)
+ (and (raw-reg h-gr index) (zext DI #xFFFFFFFF)))
+ (set (index newval)
+ (set (raw-reg h-gr index) (ext DI newval)))
+)
+
+(define-pmacro (-build-creg-name n) ((.sym cr n) n))
+
+(define-hardware
+ (name h-cr)
+ (comment "Control registers")
+ (attrs (ISA media))
+ (type register DI (64))
+ (indices keyword "" (.map -build-creg-name (.iota 64)))
+ (get (index)
+ (if DI (eq index 0)
+ (zext DI (reg h-sr))
+ (raw-reg h-cr index)))
+ (set (index newval)
+ (if (eq index 0)
+ (set (reg h-sr) newval)
+ (set (raw-reg h-cr index) newval)))
+)
+
+(define-hardware
+ (name h-sr)
+ (comment "Status register")
+ (attrs (ISA compact,media))
+ (type register SI)
+)
+
+(define-hardware
+ (name h-fpscr)
+ (comment "Floating point status and control register")
+ (attrs (ISA compact,media))
+ (type register SI)
+)
+
+(define-hardware
+ (name h-frbit)
+ (comment "Floating point register file bit")
+ (attrs (ISA media,compact) VIRTUAL)
+ (type register BI)
+ (get () (and (srl (reg h-sr) 14) 1))
+ (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
+)
+
+(define-hardware
+ (name h-szbit)
+ (comment "Floating point transfer size bit")
+ (attrs (ISA media,compact) VIRTUAL)
+ (type register BI)
+ (get () (and (srl (reg h-sr) 13) 1))
+ (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
+)
+
+(define-hardware
+ (name h-prbit)
+ (comment "Floating point precision bit")
+ (attrs (ISA media,compact) VIRTUAL)
+ (type register BI)
+ (get () (and (srl (reg h-sr) 12) 1))
+ (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
+)
+
+(define-hardware
+ (name h-sbit)
+ (comment "Multiply-accumulate saturation flag")
+ (attrs (ISA compact) VIRTUAL)
+ (type register BI)
+ (get () (and (srl (reg h-sr) 1) 1))
+ (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
+)
+
+(define-hardware
+ (name h-mbit)
+ (comment "Divide-step M flag")
+ (attrs (ISA compact) VIRTUAL)
+ (type register BI)
+ (get () (and (srl (reg h-sr) 9) 1))
+ (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
+)
+
+(define-hardware
+ (name h-qbit)
+ (comment "Divide-step Q flag")
+ (attrs (ISA compact) VIRTUAL)
+ (type register BI)
+ (get () (and (srl (reg h-sr) 8) 1))
+ (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
+)
+
+(define-pmacro (-build-freg-name n) ((.sym fr n) n))
+
+(define-hardware
+ (name h-fr)
+ (comment "Single precision floating point registers")
+ (attrs (ISA media,compact))
+ (type register SF (64))
+ (indices keyword "" (.map -build-freg-name (.iota 64)))
+)
+
+
+(define-pmacro (-build-fpair-name n) ((.sym fp n) n))
+
+(define-hardware
+ (name h-fp)
+ (comment "Single precision floating point register pairs")
+ (attrs (ISA media,compact))
+ (type register DF (32))
+ (indices keyword "" (.map -build-fpair-name (.iota 32)))
+)
+
+(define-pmacro (-build-fvec-name n) ((.sym fv n) n))
+
+(define-hardware
+ (name h-fv)
+ (comment "Single precision floating point vectors")
+ (attrs VIRTUAL (ISA media,compact))
+ (type register SF (16))
+ (indices keyword "" (.map -build-fvec-name (.iota 16)))
+ ; Mask with $F to ensure 0 <= index < 15.
+ (get (index) (reg h-fr (mul (and UQI index 15) 4)))
+ (set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
+)
+
+(define-hardware
+ (name h-fmtx)
+ (comment "Single precision floating point matrices")
+ (attrs VIRTUAL (ISA media))
+ (type register SF (4))
+ (indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
+ ; Mask with $3 to ensure 0 <= index < 4.
+ (get (index) (reg h-fr (mul (and UQI index 3) 16)))
+ (set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
+)
+
+(define-pmacro (-build-dreg-name n) ((.sym dr n) n))
+
+(define-hardware
+ (name h-dr)
+ (comment "Double precision floating point registers")
+ (attrs (ISA media,compact) VIRTUAL)
+ (type register DF (32))
+ (indices keyword "" (.map -build-dreg-name (.iota 64)))
+ (get (index)
+ (subword DF
+ (or
+ (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
+ (zext DI (subword SI (reg h-fr (add index 1)) 0))) 0))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-fr index)
+ (subword SF (subword SI newval 0) 0))
+ (set (reg h-fr (add index 1))
+ (subword SF (subword SI newval 1) 0))))
+)
+
+(define-hardware
+ (name h-tr)
+ (comment "Branch target registers")
+ (attrs (ISA media))
+ (type register DI (8))
+ (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
+)
+
+(define-hardware
+ (name h-endian)
+ (comment "Current endian mode")
+ (attrs (ISA compact,media) VIRTUAL)
+ (type register BI)
+ (get () (c-call BI "sh64_endian"))
+ (set (newval) (error "cannot alter target byte order mid-program"))
+)
+
+(define-hardware
+ (name h-ism)
+ (comment "Current instruction set mode")
+ (attrs (ISA compact,media))
+ (type register BI)
+ (get () (raw-reg h-ism))
+ (set (newval) (error "cannot set ism directly"))
+)
+
+
+; Operands.
+
+(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
+(dnop ism "Instruction set mode" ((ISA compact,media)) h-ism f-nil)
+
+; Universally useful macros.
+
+; A pmacro for use in semantic bodies of unimplemented insns.
+(define-pmacro (unimp mnemonic) (nop))
+
+; Join 2 ints together in natural bit order.
+(define-pmacro (-join-si s1 s0)
+ (or (sll (zext DI s1) 32)
+ (zext DI s0)))
+
+; Join 4 half-ints together in natural bit order.
+(define-pmacro (-join-hi h3 h2 h1 h0)
+ (or (sll (zext DI h3) 48)
+ (or (sll (zext DI h2) 32)
+ (or (sll (zext DI h1) 16)
+ (zext DI h0)))))
+
+; Join 8 quarter-ints together in natural bit order.
+(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0)
+ (or (sll (zext DI b7) 56)
+ (or (sll (zext DI b6) 48)
+ (or (sll (zext DI b5) 40)
+ (or (sll (zext DI b4) 32)
+ (or (sll (zext DI b3) 24)
+ (or (sll (zext DI b2) 16)
+ (or (sll (zext DI b1) 8)
+ (zext DI b0)))))))))
+
+
+; Include the two instruction set descriptions from their respective
+; source files.
+
+(if (keep-isa? (compact))
+ (include "sh64-compact.cpu"))
+
+(if (keep-isa? (media))
+ (include "sh64-media.cpu"))
Index: sh.opc
===================================================================
RCS file: sh.opc
diff -N sh.opc
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sh.opc 19 Feb 2004 16:01:26 -0000
@@ -0,0 +1,78 @@
+/* SHmedia opcode support. -*- C -*-
+
+ Copyright 2000 Free Software Foundation, Inc.
+
+ Contributed by Red Hat Inc; developed under contract from Hitachi
+ Semiconductor (America) Inc.
+
+ This file is part of the GNU Binutils.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+/* This file is an addendum to sh-media.cpu. Heavy use of C code isn't
+ appropriate in .cpu files, so it resides here. This especially applies
+ to assembly/disassembly where parsing/printing can be quite involved.
+ Such things aren't really part of the specification of the cpu, per se,
+ so .cpu files provide the general framework and .opc files handle the
+ nitty-gritty details as necessary.
+
+ Each section is delimited with start and end markers.
+
+ <arch>-opc.h additions use: "-- opc.h"
+ <arch>-opc.c additions use: "-- opc.c"
+ <arch>-asm.c additions use: "-- asm.c"
+ <arch>-dis.c additions use: "-- dis.c"
+ <arch>-ibd.h additions use: "-- ibd.h"
+*/
+
+/* -- opc.h */
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+ byte of these instructions. */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
+
+/* -- asm.c */
+
+static const char *
+parse_fsd (cd, strp, opindex, valuep)
+ CGEN_CPU_DESC cd;
+ const char **strp;
+ int opindex;
+ long *valuep;
+{
+ abort();
+}
+
+/* -- dis.c */
+
+static void
+print_likely (cd, dis_info, value, attrs, pc, length)
+ CGEN_CPU_DESC cd;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ disassemble_info *info = (disassemble_info *) dis_info;
+ (*info->fprintf_func) (info->stream, (value) ? "/l" : "/u");
+}
+
+/* -- */
Index: sh64-compact.cpu
===================================================================
RCS file: sh64-compact.cpu
diff -N sh64-compact.cpu
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sh64-compact.cpu 19 Feb 2004 16:01:26 -0000
@@ -0,0 +1,1747 @@
+; Hitachi SHcompact instruction set description. -*- Scheme -*-
+;
+; Copyright 2000 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Hitachi
+; Semiconductor (America) Inc.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+; dshcf -- define-normal-sh-compact-field
+
+(define-pmacro (dshcf xname xcomment ignored xstart xlength)
+ (dnf xname xcomment ((ISA compact)) xstart xlength))
+
+; dshcop -- define-normal-sh-compact-operand
+
+(define-pmacro (dshcop xname xcomment ignored xhardware xfield)
+ (dnop xname xcomment ((ISA compact)) xhardware xfield))
+
+
+; SHcompact-specific attributes.
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name ILLSLOT)
+ (comment "instruction may not appear in a delay slot")
+)
+
+(define-attr
+ (for insn)
+ (type boolean)
+ (name FP-INSN)
+ (comment "floating point instruction")
+)
+
+(define-keyword
+ (name frc-names)
+ (attrs (ISA compact))
+ (print-name h-frc)
+ (values (fr0 0) (fr1 1) (fr2 2) (fr3 3) (fr4 4) (fr5 5)
+ (fr6 6) (fr7 7) (fr8 8) (fr9 9) (fr10 10) (fr11 11)
+ (fr12 12) (fr13 13) (fr14 14) (fr15 15))
+)
+
+(define-keyword
+ (name drc-names)
+ (attrs (ISA compact))
+ (print-name h-drc)
+ (values (dr0 0) (dr2 2) (dr4 4) (dr6 6) (dr8 8) (dr10 10) (dr12 12) (dr14 14))
+)
+
+(define-keyword
+ (name xf-names)
+ (attrs (ISA compact))
+ (print-name h-xf)
+ (values (xf0 0) (xf1 1) (xf2 2) (xf3 3) (xf4 4) (xf5 5)
+ (xf6 6) (xf7 7) (xf8 8) (xf9 9) (xf10 10) (xf11 11)
+ (xf12 12) (xf13 13) (xf14 14) (xf15 15))
+)
+
+; Hardware specific to the SHcompact mode.
+
+(define-pmacro (front) (mul 16 frbit))
+(define-pmacro (back) (mul 16 (not frbit)))
+
+(define-hardware
+ (name h-frc)
+ (comment "Single precision floating point registers")
+ (attrs VIRTUAL (ISA compact))
+ (indices extern-keyword frc-names)
+ (type register SF (16))
+ (get (index) (reg h-fr (add (front) index)))
+ (set (index newval) (set (reg h-fr (add (front) index)) newval))
+)
+
+(define-hardware
+ (name h-drc)
+ (comment "Double precision floating point registers")
+ (attrs VIRTUAL (ISA compact))
+ (indices extern-keyword drc-names)
+ (type register DF (8))
+ (get (index) (reg h-dr (add (front) index)))
+ (set (index newval) (set (reg h-dr (add (front) index)) newval))
+)
+
+(define-hardware
+ (name h-xf)
+ (comment "Extended single precision floating point registers")
+ (attrs VIRTUAL (ISA compact))
+ (indices extern-keyword xf-names)
+ (type register SF (16))
+ (get (index) (reg h-fr (add (back) index)))
+ (set (index newval) (set (reg h-fr (add (back) index)) newval))
+)
+
+(define-hardware
+ (name h-xd)
+ (comment "Extended double precision floating point registers")
+ (attrs VIRTUAL (ISA compact))
+ (indices extern-keyword frc-names)
+ (type register DF (8))
+ (get (index) (reg h-dr (add (back) index)))
+ (set (index newval) (set (reg h-dr (add (back) index)) newval))
+)
+
+(define-hardware
+ (name h-fvc)
+ (comment "Single precision floating point vectors")
+ (attrs VIRTUAL (ISA compact))
+ (indices keyword "" ((fv0 0) (fv4 4) (fv8 8) (fv12 12)))
+ (type register SF (4))
+ (get (index) (reg h-fr (add (front) index)))
+ (set (index newval) (set (reg h-fr (add (front) index)) newval))
+)
+
+(define-hardware
+ (name h-fpccr)
+ (comment "SHcompact floating point status/control register")
+ (attrs VIRTUAL (ISA compact))
+ (type register SI)
+ (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21)))
+ (set (newvalue) (sequence ()
+ (set (reg h-fpscr) newvalue)
+ (set prbit (and (srl newvalue 19) 1))
+ (set szbit (and (srl newvalue 20) 1))
+ (set frbit (and (srl newvalue 21) 1))))
+)
+
+(define-hardware
+ (name h-gbr)
+ (comment "Global base register")
+ (attrs VIRTUAL (ISA compact))
+ (type register SI)
+ (get () (subword SI (raw-reg h-gr 16) 1))
+ (set (newval) (set (raw-reg h-gr 16) (ext DI newval)))
+)
+
+(define-hardware
+ (name h-pr)
+ (comment "Procedure link register")
+ (attrs VIRTUAL (ISA compact))
+ (type register SI)
+ (get () (subword SI (raw-reg h-gr 18) 1))
+ (set (newval) (set (raw-reg h-gr 18) (ext DI newval)))
+)
+
+(define-hardware
+ (name h-macl)
+ (comment "Multiple-accumulate low register")
+ (attrs VIRTUAL (ISA compact))
+ (type register SI)
+ (get () (subword SI (raw-reg h-gr 17) 1))
+ (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval)))
+)
+
+(define-hardware
+ (name h-mach)
+ (comment "Multiply-accumulate high register")
+ (attrs VIRTUAL (ISA compact))
+ (type register SI)
+ (get () (subword SI (raw-reg h-gr 17) 0))
+ (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1))))
+)
+
+(define-hardware
+ (name h-tbit)
+ (comment "Condition code flag")
+ (attrs VIRTUAL (ISA compact))
+ (type register BI)
+ (get () (and BI (raw-reg h-gr 19) 1))
+ (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval))))
+)
+
+
+(dshcf f-op4 "Opcode (4 bits)" () 15 4)
+(dshcf f-op8 "Opcode (8 bits)" () 15 8)
+(dshcf f-op16 "Opcode (16 bits)" () 15 16)
+
+(dshcf f-sub4 "Sub opcode (4 bits)" () 3 4)
+(dshcf f-sub8 "Sub opcode (8 bits)" () 7 8)
+(dshcf f-sub10 "Sub opcode (10 bits)" () 9 10)
+
+(dshcf f-rn "Register selector n" () 11 4)
+(dshcf f-rm "Register selector m" () 7 4)
+
+(dshcf f-8-1 "One bit at bit 8" () 8 1)
+
+(df f-disp8 "Displacement (8 bits)" ((ISA compact) PCREL-ADDR) 7 8 INT
+ ((value pc) (sra SI value 1))
+ ((value pc) (add SI (sll SI value 1) (add pc 4))))
+
+(df f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT
+ ((value pc) (sra SI value 1))
+ ((value pc) (add SI (sll SI value 1) (add pc 4))))
+
+(dshcf f-imm8 "Immediate (8 bits)" () 7 8)
+(dshcf f-imm4 "Immediate (4 bits)" () 3 4)
+
+(df f-imm4x2 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (sll SI value 1)))
+
+(df f-imm4x4 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT
+ ((value pc) (srl SI value 2))
+ ((value pc) (sll SI value 2)))
+
+(df f-imm8x2 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT
+ ((value pc) (sra SI value 1))
+ ((value pc) (sll SI value 1)))
+
+(df f-imm8x4 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT
+ ((value pc) (sra SI value 2))
+ ((value pc) (sll SI value 2)))
+
+(df f-dn "Double selector n" ((ISA compact)) 11 3 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (sll SI value 1)))
+
+(df f-dm "Double selector m" ((ISA compact)) 7 3 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (sll SI value 1)))
+
+(df f-vn "Vector selector n" ((ISA compact)) 11 2 UINT
+ ((value pc) (srl SI value 2))
+ ((value pc) (sll SI value 2)))
+
+(df f-vm "Vector selector m" ((ISA compact)) 9 2 UINT
+ ((value pc) (srl SI value 2))
+ ((value pc) (sll SI value 2)))
+
+(df f-xn "Extended selector n" ((ISA compact)) 11 3 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (add SI (sll SI value 1) 1)))
+
+(df f-xm "Extended selector m" ((ISA compact)) 7 3 UINT
+ ((value pc) (srl SI value 1))
+ ((value pc) (add SI (sll SI value 1) 1)))
+
+
+; Operands.
+
+(dshcop rm "Left general purpose register" () h-grc f-rm)
+(dshcop rn "Right general purpose register" () h-grc f-rn)
+(dshcop r0 "Register 0" () h-grc 0)
+
+(dshcop frn "Single precision register" () h-frc f-rn)
+(dshcop frm "Single precision register" () h-frc f-rm)
+
+(dshcop fvn "Left floating point vector" () h-fvc f-vn)
+(dshcop fvm "Right floating point vector" () h-fvc f-vm)
+
+(dshcop drn "Left double precision register" () h-drc f-dn)
+(dshcop drm "Right double precision register" () h-drc f-dm)
+
+(dshcop imm4 "Immediate value (4 bits)" () h-sint f-imm4)
+(dshcop imm8 "Immediate value (8 bits)" () h-sint f-imm8)
+(dshcop uimm8 "Immediate value (8 bits unsigned)" () h-uint f-imm8)
+
+(dshcop imm4x2 "Immediate value (4 bits, 2x scale)" () h-uint f-imm4x2)
+(dshcop imm4x4 "Immediate value (4 bits, 4x scale)" () h-uint f-imm4x4)
+(dshcop imm8x2 "Immediate value (8 bits, 2x scale)" () h-uint f-imm8x2)
+(dshcop imm8x4 "Immediate value (8 bits, 4x scale)" () h-uint f-imm8x4)
+
+(dshcop disp8 "Displacement (8 bits)" () h-iaddr f-disp8)
+(dshcop disp12 "Displacement (12 bits)" () h-iaddr f-disp12)
+
+(dshcop rm64 "Register m (64 bits)" () h-gr f-rm)
+(dshcop rn64 "Register n (64 bits)" () h-gr f-rn)
+
+(dshcop gbr "Global base register" () h-gbr f-nil)
+(dshcop pr "Procedure link register" () h-pr f-nil)
+
+(dshcop fpscr "Floating point status/control register" () h-fpccr f-nil)
+
+(dshcop tbit "Condition code flag" () h-tbit f-nil)
+(dshcop sbit "Multiply-accumulate saturation flag" () h-sbit f-nil)
+(dshcop mbit "Divide-step M flag" () h-mbit f-nil)
+(dshcop qbit "Divide-step Q flag" () h-qbit f-nil)
+(dshcop fpul "Floating point ???" () h-fr 32)
+
+(dshcop frbit "Floating point register bank bit" () h-frbit f-nil)
+(dshcop szbit "Floating point transfer size bit" () h-szbit f-nil)
+(dshcop prbit "Floating point precision bit" () h-prbit f-nil)
+
+(dshcop macl "Multiply-accumulate low register" () h-macl f-nil)
+(dshcop mach "Multiply-accumulate high register" () h-mach f-nil)
+
+
+(define-operand (name fsdm) (comment "bar")
+ (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd")))
+
+(define-operand (name fsdn) (comment "bar")
+ (attrs (ISA compact)) (type h-frc) (index f-rn))
+
+
+; Cover macro to dni to indicate these are all SHcompact instructions.
+; dshmi: define-normal-sh-compact-insn
+
+(define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics)
+ (define-insn
+ (name (.sym xname -compact))
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs) (ISA compact))
+ (syntax xsyntax)
+ (format xformat)
+ (semantics xsemantics)))
+
+(define-pmacro (dr operand) (reg h-dr (index-of operand)))
+(define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1))))
+
+(dshci add "Add"
+ ()
+ "add $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 12))
+ (set rn (add rn rm)))
+
+(dshci addi "Add immediate"
+ ()
+ "add #$imm8, $rn"
+ (+ (f-op4 7) rn imm8)
+ (set rn (add rn (ext SI (and QI imm8 255)))))
+
+(dshci addc "Add with carry"
+ ()
+ "addc $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 14))
+ (sequence ((BI flag))
+ (set flag (add-cflag rn rm tbit))
+ (set rn (addc rn rm tbit))
+ (set tbit flag)))
+
+(dshci addv "Add with overflow"
+ ()
+ "addv $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 15))
+ (sequence ((BI t))
+ (set t (add-oflag rn rm 0))
+ (set rn (add rn rm))
+ (set tbit t)))
+
+(dshci and "Bitwise AND"
+ ()
+ "and $rm64, $rn64"
+ (+ (f-op4 2) rn64 rm64 (f-sub4 9))
+ (set rn64 (and rm64 rn64)))
+
+(dshci andi "Bitwise AND immediate"
+ ()
+ "and #$uimm8, r0"
+ (+ (f-op8 #xc9) uimm8)
+ (set r0 (and r0 (zext DI uimm8))))
+
+(dshci andb "Bitwise AND memory byte"
+ ()
+ "and.b #$imm8, @(r0, gbr)"
+ (+ (f-op8 #xcd) imm8)
+ (sequence ((DI addr) (UQI data))
+ (set addr (add r0 gbr))
+ (set data (and (mem UQI addr) imm8))
+ (set (mem UQI addr) data)))
+
+(dshci bf "Conditional branch"
+ ()
+ "bf $disp8"
+ (+ (f-op8 #x8b) disp8)
+ (if (not tbit)
+ (set pc disp8)))
+
+(dshci bfs "Conditional branch with delay slot"
+ ()
+ "bf/s $disp8"
+ (+ (f-op8 #x8f) disp8)
+ (if (not tbit)
+ (delay 1 (set pc disp8))))
+
+(dshci bra "Branch"
+ ()
+ "bra $disp12"
+ (+ (f-op4 10) disp12)
+ (delay 1 (set pc disp12)))
+
+(dshci braf "Branch far"
+ ()
+ "braf $rn"
+ (+ (f-op4 0) rn (f-sub8 35))
+ (delay 1 (set pc (add (ext DI rn) (add pc 4)))))
+
+(dshci brk "Breakpoint"
+ ()
+ "brk"
+ (+ (f-op16 59))
+ (c-call "sh64_break" pc))
+
+(dshci bsr "Branch to subroutine"
+ ()
+ "bsr $disp12"
+ (+ (f-op4 11) disp12)
+ (delay 1 (sequence ()
+ (set pr (add pc 4))
+ (set pc disp12))))
+
+(dshci bsrf "Branch to far subroutine"
+ ()
+ "bsrf $rn"
+ (+ (f-op4 0) rn (f-sub8 3))
+ (delay 1 (sequence ()
+ (set pr (add pc 4))
+ (set pc (add (ext DI rn) (add pc 4))))))
+
+(dshci bt "Conditional branch"
+ ()
+ "bt $disp8"
+ (+ (f-op8 #x89) disp8)
+ (if tbit
+ (set pc disp8)))
+
+(dshci bts "Conditional branch with delay slot"
+ ()
+ "bt/s $disp8"
+ (+ (f-op8 #x8d) disp8)
+ (if tbit
+ (delay 1 (set pc disp8))))
+
+(dshci clrmac "Clear MACL and MACH"
+ ()
+ "clrmac"
+ (+ (f-op16 40))
+ (sequence ()
+ (set macl 0)
+ (set mach 0)))
+
+(dshci clrs "Clear S-bit"
+ ()
+ "clrs"
+ (+ (f-op16 72))
+ (set sbit 0))
+
+(dshci clrt "Clear T-bit"
+ ()
+ "clrt"
+ (+ (f-op16 8))
+ (set tbit 0))
+
+(dshci cmpeq "Compare if equal"
+ ()
+ "cmp/eq $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 0))
+ (set tbit (eq rm rn)))
+
+(dshci cmpeqi "Compare if equal (immediate)"
+ ()
+ "cmp/eq #$imm8, r0"
+ (+ (f-op8 #x88) imm8)
+ (set tbit (eq r0 (ext SI (and QI imm8 255)))))
+
+(dshci cmpge "Compare if greater than or equal"
+ ()
+ "cmp/ge $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 3))
+ (set tbit (ge rn rm)))
+
+(dshci cmpgt "Compare if greater than"
+ ()
+ "cmp/gt $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 7))
+ (set tbit (gt rn rm)))
+
+(dshci cmphi "Compare if greater than (unsigned)"
+ ()
+ "cmp/hi $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 6))
+ (set tbit (gtu rn rm)))
+
+(dshci cmphs "Compare if greater than or equal (unsigned)"
+ ()
+ "cmp/hs $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 2))
+ (set tbit (geu rn rm)))
+
+(dshci cmppl "Compare if greater than zero"
+ ()
+ "cmp/pl $rn"
+ (+ (f-op4 4) rn (f-sub8 21))
+ (set tbit (gt rn 0)))
+
+(dshci cmppz "Compare if greater than or equal zero"
+ ()
+ "cmp/pz $rn"
+ (+ (f-op4 4) rn (f-sub8 17))
+ (set tbit (ge rn 0)))
+
+(dshci cmpstr "Compare bytes"
+ ()
+ "cmp/str $rm, $rn"
+ (+ (f-op4 2) rn rm (f-sub4 12))
+ (sequence ((BI t) (SI temp))
+ (set temp (xor rm rn))
+ (set t (eq (and temp #xff000000) 0))
+ (set t (or (eq (and temp #xff0000) 0) t))
+ (set t (or (eq (and temp #xff00) 0) t))
+ (set t (or (eq (and temp #xff) 0) t))
+ (set tbit (if BI (gtu t 0) 1 0))))
+
+(dshci div0s "Initialise divide-step state for signed division"
+ ()
+ "div0s $rm, $rn"
+ (+ (f-op4 2) rn rm (f-sub4 7))
+ (sequence ()
+ (set qbit (srl rn 31))
+ (set mbit (srl rm 31))
+ (set tbit (if BI (eq (srl rm 31) (srl rn 31)) 0 1))))
+
+(dshci div0u "Initialise divide-step state for unsigned division"
+ ()
+ "div0u"
+ (+ (f-op16 25))
+ (sequence ()
+ (set tbit 0)
+ (set qbit 0)
+ (set mbit 0)))
+
+(dshci div1 "Divide step"
+ ()
+ "div1 $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 4))
+ (sequence ((BI oldq) (SI tmp0) (UQI tmp1))
+ (set oldq qbit)
+ (set qbit (srl rn 31))
+ (set rn (or (sll rn 1) (zext SI tbit)))
+ (if (not oldq)
+ (if (not mbit)
+ (sequence ()
+ (set tmp0 rn)
+ (set rn (sub rn rm))
+ (set tmp1 (gtu rn tmp0))
+ (if (not qbit)
+ (set qbit (if BI tmp1 1 0))
+ (set qbit (if BI (eq tmp1 0) 1 0))))
+ (sequence ()
+ (set tmp0 rn)
+ (set rn (add rn rm))
+ (set tmp1 (ltu rn tmp0))
+ (if (not qbit)
+ (set qbit (if BI (eq tmp1 0) 1 0))
+ (set qbit (if BI tmp1 1 0)))))
+ (if (not mbit)
+ (sequence ()
+ (set tmp0 rn)
+ (set rn (add rm rn))
+ (set tmp1 (ltu rn tmp0))
+ (if (not qbit)
+ (set qbit (if BI tmp1 1 0))
+ (set qbit (if BI (eq tmp1 0) 1 0))))
+ (sequence ()
+ (set tmp0 rn)
+ (set rn (sub rn rm))
+ (set tmp1 (gtu rn tmp0))
+ (if (not qbit)
+ (set qbit (if BI (eq tmp1 0) 1 0))
+ (set qbit (if BI tmp1 1 0))))))
+ (set tbit (if BI (eq qbit mbit) 1 0))))
+
+(dshci dmulsl "Multiply long (signed)"
+ ()
+ "dmuls.l $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 13))
+ (sequence ((DI result))
+ (set result (mul (ext DI rm) (ext DI rn)))
+ (set mach (subword SI result 0))
+ (set macl (subword SI result 1))))
+
+(dshci dmulul "Multiply long (unsigned)"
+ ()
+ "dmulu.l $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 5))
+ (sequence ((DI result))
+ (set result (mul (zext DI rm) (zext DI rn)))
+ (set mach (subword SI result 0))
+ (set macl (subword SI result 1))))
+
+(dshci dt "Decrement and set"
+ ()
+ "dt $rn"
+ (+ (f-op4 4) rn (f-sub8 16))
+ (sequence ()
+ (set rn (sub rn 1))
+ (set tbit (eq rn 0))))
+
+(dshci extsb "Sign extend byte"
+ ()
+ "exts.b $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 14))
+ (set rn (ext SI (subword QI rm 3))))
+
+(dshci extsw "Sign extend word"
+ ()
+ "exts.w $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 15))
+ (set rn (ext SI (subword HI rm 1))))
+
+(dshci extub "Zero extend byte"
+ ()
+ "extu.b $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 12))
+ (set rn (zext SI (subword QI rm 3))))
+
+(dshci extuw "Zero etxend word"
+ ()
+ "extu.w $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 13))
+ (set rn (zext SI (subword HI rm 1))))
+
+(dshci fabs "Floating point absolute"
+ (FP-INSN)
+ "fabs $fsdn"
+ (+ (f-op4 15) fsdn (f-sub8 #x5d))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_fabsd" (dr fsdn)))
+ (set fsdn (c-call SF "sh64_fabss" fsdn))))
+
+(dshci fadd "Floating point add"
+ (FP-INSN)
+ "fadd $fsdm, $fsdn"
+ (+ (f-op4 15) fsdn fsdm (f-sub4 0))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_faddd" (dr fsdm) (dr fsdn)))
+ (set fsdn (c-call SF "sh64_fadds" fsdm fsdn))))
+
+(dshci fcmpeq "Floating point compare equal"
+ (FP-INSN)
+ "fcmp/eq $fsdm, $fsdn"
+ (+ (f-op4 15) fsdn fsdm (f-sub4 4))
+ (if prbit
+ (set tbit (c-call BI "sh64_fcmpeqd" (dr fsdm) (dr fsdn)))
+ (set tbit (c-call BI "sh64_fcmpeqs" fsdm fsdn))))
+
+(dshci fcmpgt "Floating point compare greater than"
+ (FP-INSN)
+ "fcmp/gt $fsdm, $fsdn"
+ (+ (f-op4 15) fsdn fsdm (f-sub4 5))
+ (if prbit
+ (set tbit (c-call BI "sh64_fcmpgtd" (dr fsdn) (dr fsdm)))
+ (set tbit (c-call BI "sh64_fcmpgts" fsdn fsdm))))
+
+(dshci fcnvds "Floating point convert (double to single)"
+ (FP-INSN)
+ "fcnvds $drn, fpul"
+ (+ (f-op4 15) drn (f-8-1 10) (f-sub8 #xbd))
+ (set fpul (c-call SF "sh64_fcnvds" drn)))
+
+(dshci fcnvsd "Floating point convert (single to double)"
+ (FP-INSN)
+ "fcnvsd fpul, $drn"
+ (+ (f-op4 15) drn (f-8-1 0) (f-sub8 #xad))
+ (set drn (c-call DF "sh64_fcnvsd" fpul)))
+
+(dshci fdiv "Floating point divide"
+ (FP-INSN)
+ "fdiv $fsdm, $fsdn"
+ (+ (f-op4 15) fsdn fsdm (f-sub4 3))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_fdivd" (dr fsdn) (dr fsdm)))
+ (set fsdn (c-call SF "sh64_fdivs" fsdn fsdm))))
+
+(dshci fipr "Floating point inner product"
+ (FP-INSN)
+ "fipr $fvm, $fvn"
+ (+ (f-op4 15) fvn fvm (f-sub8 #xed))
+ (sequence ((QI m) (QI n) (SF res))
+ (set m (index-of fvm))
+ (set n (index-of fvn))
+ (set res (c-call SF "sh64_fmuls" fvm fvn))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 1)) (reg h-frc (add n 1)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 2)) (reg h-frc (add n 2)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 3)) (reg h-frc (add n 3)))))
+ (set (reg h-frc (add n 3)) res)))
+
+(dshci flds "Floating point load status register"
+ (FP-INSN)
+ "flds $frn"
+ (+ (f-op4 15) frn (f-sub8 #x1d))
+ (set fpul frn))
+
+(dshci fldi0 "Floating point load immediate 0.0"
+ (FP-INSN)
+ "fldi0 $frn"
+ (+ (f-op4 15) frn (f-sub8 #x8d))
+ (set frn (c-call SF "sh64_fldi0")))
+
+(dshci fldi1 "Floating point load immediate 1.0"
+ (FP-INSN)
+ "fldi1 $frn"
+ (+ (f-op4 15) frn (f-sub8 #x9d))
+ (set frn (c-call SF "sh64_fldi1")))
+
+(dshci float "Floating point integer conversion"
+ (FP-INSN)
+ "float fpul, $fsdn"
+ (+ (f-op4 15) fsdn (f-sub8 #x2d))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_floatld" fpul))
+ (set fsdn (c-call SF "sh64_floatls" fpul))))
+
+(dshci fmac "Floating point multiply and accumulate"
+ (FP-INSN)
+ "fmac fr0, $frm, $frn"
+ (+ (f-op4 15) frn frm (f-sub4 14))
+ (set frn (c-call SF "sh64_fmacs" (reg h-frc 0) frm frn)))
+
+(define-pmacro (even x) (eq (and x 1) 0))
+(define-pmacro (odd x) (eq (and x 1) 1))
+(define-pmacro (extd x) (odd (index-of x)))
+
+(dshci fmov1 "Floating point move (register to register)"
+ (FP-INSN)
+ "fmov $frm, $frn"
+ (+ (f-op4 15) frn frm (f-sub4 12))
+ (if (not szbit)
+ ; single precision operation
+ (set frn frm)
+ ; double or extended operation
+ (if (extd frm)
+ (if (extd frn)
+ (set (xd frn) (xd frm))
+ (set (dr frn) (xd frm)))
+ (if (extd frn)
+ (set (xd frn) (dr frm))
+ (set (dr frn) (dr frm))))))
+
+(dshci fmov2 "Floating point load"
+ (FP-INSN)
+ "fmov @$rm, $frn"
+ (+ (f-op4 15) frn rm (f-sub4 8))
+ (if (not szbit)
+ ; single precision operation
+ (set frn (mem SF rm))
+ ; double or extended operation
+ (if (extd frn)
+ (set (xd frn) (mem DF rm))
+ (set (dr frn) (mem DF rm)))))
+
+(dshci fmov3 "Floating point load (post-increment)"
+ (FP-INSN)
+ "fmov @${rm}+, frn"
+ (+ (f-op4 15) frn rm (f-sub4 9))
+ (if (not szbit)
+ ; single precision operation
+ (sequence ()
+ (set frn (mem SF rm))
+ (set rm (add rm 4)))
+ ; double or extended operation
+ (sequence ()
+ (if (extd frn)
+ (set (xd frn) (mem DF rm))
+ (set (dr frn) (mem DF rm)))
+ (set rm (add rm 8)))))
+
+(dshci fmov4 "Floating point load (register/register indirect)"
+ (FP-INSN)
+ "fmov @(r0, $rm), $frn"
+ (+ (f-op4 15) frn rm (f-sub4 6))
+ (if (not szbit)
+ ; single precision operation
+ (set frn (mem SF (add r0 rm)))
+ ; double or extended operation
+ (if (extd frn)
+ (set (xd frn) (mem DF (add r0 rm)))
+ (set (dr frn) (mem DF (add r0 rm))))))
+
+(dshci fmov5 "Floating point store"
+ (FP-INSN)
+ "fmov $frm, @$rn"
+ (+ (f-op4 15) rn frm (f-sub4 10))
+ (if (not szbit)
+ ; single precision operation
+ (set (mem SF rn) frm)
+ ; double or extended operation
+ (if (extd frm)
+ (set (mem DF rn) (xd frm))
+ (set (mem DF rn) (dr frm)))))
+
+(dshci fmov6 "Floating point store (pre-decrement)"
+ (FP-INSN)
+ "fmov $frm, @-$rn"
+ (+ (f-op4 15) rn frm (f-sub4 11))
+ (if (not szbit)
+ ; single precision operation
+ (sequence ()
+ (set rn (sub rn 4))
+ (set (mem SF rn) frm))
+ ; double or extended operation
+ (sequence ()
+ (set rn (sub rn 8))
+ (if (extd frm)
+ (set (mem DF rn) (xd frm))
+ (set (mem DF rn) (dr frm))))))
+
+(dshci fmov7 "Floating point store (register/register indirect)"
+ (FP-INSN)
+ "fmov $frm, @(r0, $rn)"
+ (+ (f-op4 15) rn frm (f-sub4 7))
+ (if (not szbit)
+ ; single precision operation
+ (set (mem SF (add r0 rn)) frm)
+ ; double or extended operation
+ (if (extd frm)
+ (set (mem DF (add r0 rn)) (xd frm))
+ (set (mem DF (add r0 rn)) (dr frm)))))
+
+(dshci fmul "Floating point multiply"
+ (FP-INSN)
+ "fmul $fsdm, $fsdn"
+ (+ (f-op4 15) fsdn fsdm (f-sub4 2))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_fmuld" (dr fsdm) (dr fsdn)))
+ (set fsdn (c-call SF "sh64_fmuls" fsdm fsdn))))
+
+(dshci fneg "Floating point negate"
+ (FP-INSN)
+ "fneg $fsdn"
+ (+ (f-op4 15) fsdn (f-sub8 #x4d))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_fnegd" (dr fsdn)))
+ (set fsdn (c-call SF "sh64_fnegs" fsdn))))
+
+(dshci frchg "Toggle floating point register banks"
+ (FP-INSN)
+ "frchg"
+ (+ (f-op16 #xfbfd))
+ (set frbit (not frbit)))
+
+(dshci fschg "Set size of floating point transfers"
+ (FP-INSN)
+ "fschg"
+ (+ (f-op16 #xf3fd))
+ (set szbit (not szbit)))
+
+(dshci fsqrt "Floating point square root"
+ (FP-INSN)
+ "fsqrt $fsdn"
+ (+ (f-op4 15) fsdn (f-sub8 #x6d))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_fsqrtd" (dr fsdn)))
+ (set fsdn (c-call SF "sh64_fsqrts" fsdn))))
+
+(dshci fsts "Floating point store status register"
+ (FP-INSN)
+ "fsts fpul, $frn"
+ (+ (f-op4 15) frn (f-sub8 13))
+ (set frn fpul))
+
+(dshci fsub "Floating point subtract"
+ (FP-INSN)
+ "fsub $fsdm, $fsdn"
+ (+ (f-op4 15) fsdn fsdm (f-sub4 1))
+ (if prbit
+ (set (dr fsdn) (c-call DF "sh64_fsubd" (dr fsdn) (dr fsdm)))
+ (set fsdn (c-call SF "sh64_fsubs" fsdn fsdm))))
+
+(dshci ftrc "Floating point truncate"
+ (FP-INSN)
+ "ftrc $fsdn, fpul"
+ (+ (f-op4 15) fsdn (f-sub8 #x3d))
+ (set fpul (if SF prbit
+ (c-call SF "sh64_ftrcdl" (dr fsdn))
+ (c-call SF "sh64_ftrcsl" fsdn))))
+
+(dshci ftrv "Floating point transform vector"
+ (FP-INSN)
+ "ftrv xmtrx, $fvn"
+ (+ (f-op4 15) fvn (f-sub10 #x1fd))
+ (sequence ((QI n) (SF res))
+ (set n (index-of fvn))
+ (set res (c-call SF "sh64_fmuls" (reg h-xf 0) (reg h-frc n)))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 4) (reg h-frc (add n 1)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 8) (reg h-frc (add n 2)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 12) (reg h-frc (add n 3)))))
+ (set (reg h-frc n) res)
+ (set res (c-call SF "sh64_fmuls" (reg h-xf 1) (reg h-frc n)))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 5) (reg h-frc (add n 1)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 9) (reg h-frc (add n 2)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 13) (reg h-frc (add n 3)))))
+ (set (reg h-frc (add n 1)) res)
+ (set res (c-call SF "sh64_fmuls" (reg h-xf 2) (reg h-frc n)))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 6) (reg h-frc (add n 1)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 10) (reg h-frc (add n 2)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 14) (reg h-frc (add n 3)))))
+ (set (reg h-frc (add n 2)) res)
+ (set res (c-call SF "sh64_fmuls" (reg h-xf 3) (reg h-frc n)))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 7) (reg h-frc (add n 1)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 11) (reg h-frc (add n 2)))))
+ (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 15) (reg h-frc (add n 3)))))
+ (set (reg h-frc (add n 3)) res)))
+
+(dshci jmp "Jump"
+ ()
+ "jmp @$rn"
+ (+ (f-op4 4) rn (f-sub8 43))
+ (delay 1 (set pc rn)))
+
+(dshci jsr "Jump to subroutine"
+ ()
+ "jsr @$rn"
+ (+ (f-op4 4) rn (f-sub8 11))
+ (delay 1 (sequence ()
+ (set pr (add pc 4))
+ (set pc rn))))
+
+(dshci ldc "Load control register (GBR)"
+ ()
+ "ldc $rn, gbr"
+ (+ (f-op4 4) rn (f-sub8 30))
+ (set gbr rn))
+
+(dshci ldcl "Load control register (GBR)"
+ ()
+ "ldc.l @${rn}+, gbr"
+ (+ (f-op4 4) rn (f-sub8 39))
+ (sequence ()
+ (set gbr (mem SI rn))
+ (set rn (add rn 4))))
+
+(dshci lds-fpscr "Load status register (FPSCR)"
+ ()
+ "lds $rn, fpscr"
+ (+ (f-op4 4) rn (f-sub8 106))
+ (set fpscr rn))
+
+(dshci ldsl-fpscr "Load status register (FPSCR)"
+ ()
+ "lds.l @${rn}+, fpscr"
+ (+ (f-op4 4) rn (f-sub8 102))
+ (sequence ()
+ (set fpscr (mem SI rn))
+ (set rn (add rn 4))))
+
+(dshci lds-fpul "Load status register (FPUL)"
+ ()
+ "lds $rn, fpul"
+ (+ (f-op4 4) rn (f-sub8 90))
+ ; Use subword to convert rn's mode.
+ (set fpul (subword SF rn 0)))
+
+(dshci ldsl-fpul "Load status register (FPUL)"
+ ()
+ "lds.l @${rn}+, fpul"
+ (+ (f-op4 4) rn (f-sub8 86))
+ (sequence ()
+ (set fpul (mem SF rn))
+ (set rn (add rn 4))))
+
+(dshci lds-mach "Load status register (MACH)"
+ ()
+ "lds $rn, mach"
+ (+ (f-op4 4) rn (f-sub8 10))
+ (set mach rn))
+
+(dshci ldsl-mach "Load status register (MACH), post-increment"
+ ()
+ "lds.l @${rn}+, mach"
+ (+ (f-op4 4) rn (f-sub8 6))
+ (sequence ()
+ (set mach (mem SI rn))
+ (set rn (add rn 4))))
+
+(dshci lds-macl "Load status register (MACL)"
+ ()
+ "lds $rn, macl"
+ (+ (f-op4 4) rn (f-sub8 26))
+ (set macl rn))
+
+(dshci ldsl-macl "Load status register (MACL), post-increment"
+ ()
+ "lds.l @${rn}+, macl"
+ (+ (f-op4 4) rn (f-sub8 22))
+ (sequence ()
+ (set macl (mem SI rn))
+ (set rn (add rn 4))))
+
+(dshci lds-pr "Load status register (PR)"
+ ()
+ "lds $rn, pr"
+ (+ (f-op4 4) rn (f-sub8 42))
+ (set pr rn))
+
+(dshci ldsl-pr "Load status register (PR), post-increment"
+ ()
+ "lds.l @${rn}+, pr"
+ (+ (f-op4 4) rn (f-sub8 38))
+ (sequence ()
+ (set pr (mem SI rn))
+ (set rn (add rn 4))))
+
+(dshci macl "Multiply and accumulate (long)"
+ ()
+ "mac.l @${rm}+, @${rn}+"
+ (+ (f-op4 0) rn rm (f-sub4 15))
+ (sequence ((DI tmpry) (DI mac) (DI result) (SI x) (SI y))
+ (set x (mem SI rn))
+ (set rn (add rn 4))
+ (if (eq (index-of rn) (index-of rm))
+ (sequence ()
+ (set rn (add rn 4))
+ (set rm (add rm 4))))
+ (set y (mem SI rm))
+ (set rm (add rm 4))
+ (set tmpry (mul (zext DI x) (zext DI y)))
+ (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
+ (set result (add mac tmpry))
+ (sequence ()
+ (if sbit
+ (sequence ((SI min) (SI max))
+ (set max (srl (inv DI 0) 16))
+ ; Preserve bit 48 for sign.
+ (set min (srl (inv DI 0) 15))
+ (if (gt result max)
+ (set result max)
+ (if (lt result min)
+ (set result min)))))
+ (set mach (subword SI result 0))
+ (set macl (subword SI result 1)))))
+
+(dshci macw "Multiply and accumulate (word)"
+ ()
+ "mac.w @${rm}+, @${rn}+"
+ (+ (f-op4 4) rn rm (f-sub4 15))
+ (sequence ((SI tmpry) (DI mac) (DI result) (HI x) (HI y))
+ (set x (mem HI rn))
+ (set rn (add rn 2))
+ (if (eq (index-of rn) (index-of rm))
+ (sequence ()
+ (set rn (add rn 2))
+ (set rm (add rm 2))))
+ (set y (mem HI rm))
+ (set rm (add rm 2))
+ (set tmpry (mul (zext SI x) (zext SI y)))
+ (if sbit
+ (sequence ()
+ (if (add-oflag tmpry macl 0)
+ (set mach 1))
+ (set macl (add tmpry macl)))
+ (sequence ()
+ (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
+ (set result (add mac (ext DI tmpry)))
+ (set mach (subword SI result 0))
+ (set macl (subword SI result 1))))))
+
+(dshci mov "Move"
+ ()
+ "mov $rm64, $rn64"
+ (+ (f-op4 6) rn64 rm64 (f-sub4 3))
+ (set rn64 rm64))
+
+(dshci movi "Move immediate"
+ ()
+ "mov #$imm8, $rn"
+ (+ (f-op4 14) rn imm8)
+ (set rn (ext DI (and QI imm8 255))))
+
+(dshci movb1 "Store byte to memory (register indirect w/ zero displacement)"
+ ()
+ "mov.b $rm, @$rn"
+ (+ (f-op4 2) rn rm (f-sub4 0))
+ (set (mem UQI rn) (subword UQI rm 3)))
+
+(dshci movb2 "Store byte to memory (register indirect w/ pre-decrement)"
+ ()
+ "mov.b $rm, @-$rn"
+ (+ (f-op4 2) rn rm (f-sub4 4))
+ (sequence ((DI addr))
+ (set addr (sub rn 1))
+ (set (mem UQI addr) (subword UQI rm 3))
+ (set rn addr)))
+
+(dshci movb3 "Store byte to memory (register/register indirect)"
+ ()
+ "mov.b $rm, @(r0,$rn)"
+ (+ (f-op4 0) rn rm (f-sub4 4))
+ (set (mem UQI (add r0 rn)) (subword UQI rm 3)))
+
+(dshci movb4 "Store byte to memory (GBR-relative w/ displacement)"
+ ()
+ "mov.b r0, @($imm8, gbr)"
+ (+ (f-op8 #xc0) imm8)
+ (sequence ((DI addr))
+ (set addr (add gbr imm8))
+ (set (mem UQI addr) (subword UQI r0 3))))
+
+(dshci movb5 "Store byte to memory (register indirect w/ displacement)"
+ ()
+ "mov.b r0, @($imm4, $rm)"
+ (+ (f-op8 #x80) rm imm4)
+ (sequence ((DI addr))
+ (set addr (add rm imm4))
+ (set (mem UQI addr) (subword UQI r0 3))))
+
+(dshci movb6 "Load byte from memory (register indirect w/ zero displacement)"
+ ()
+ "mov.b @$rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 0))
+ (set rn (ext SI (mem QI rm))))
+
+(dshci movb7 "Load byte from memory (register indirect w/ post-increment)"
+ ()
+ "mov.b @${rm}+, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 4))
+ (sequence ((QI data))
+ (set data (mem QI rm))
+ (if (eq (index-of rm) (index-of rn))
+ (set rm (ext SI data))
+ (set rm (add rm 1)))
+ (set rn (ext SI data))))
+
+(dshci movb8 "Load byte from memory (register/register indirect)"
+ ()
+ "mov.b @(r0, $rm), $rn"
+ (+ (f-op4 0) rn rm (f-sub4 12))
+ (set rn (ext SI (mem QI (add r0 rm)))))
+
+(dshci movb9 "Load byte from memory (GBR-relative with displacement)"
+ ()
+ "mov.b @($imm8, gbr), r0"
+ (+ (f-op8 #xc4) imm8)
+ (set r0 (ext SI (mem QI (add gbr imm8)))))
+
+(dshci movb10 "Load byte from memory (register indirect w/ displacement)"
+ ()
+ "mov.b @($imm4, $rm), r0"
+ (+ (f-op8 #x84) rm imm4)
+ (set r0 (ext SI (mem QI (add rm imm4)))))
+
+(dshci movl1 "Store long word to memory (register indirect w/ zero displacement)"
+ ()
+ "mov.l $rm, @$rn"
+ (+ (f-op4 2) rn rm (f-sub4 2))
+ (set (mem SI rn) rm))
+
+(dshci movl2 "Store long word to memory (register indirect w/ pre-decrement)"
+ ()
+ "mov.l $rm, @-$rn"
+ (+ (f-op4 2) rn rm (f-sub4 6))
+ (sequence ((SI addr))
+ (set addr (sub rn 4))
+ (set (mem SI addr) rm)
+ (set rn addr)))
+
+(dshci movl3 "Store long word to memory (register/register indirect)"
+ ()
+ "mov.l $rm, @(r0, $rn)"
+ (+ (f-op4 0) rn rm (f-sub4 6))
+ (set (mem SI (add r0 rn)) rm))
+
+(dshci movl4 "Store long word to memory (GBR-relative w/ displacement)"
+ ()
+ "mov.l r0, @($imm8x4, gbr)"
+ (+ (f-op8 #xc2) imm8x4)
+ (set (mem SI (add gbr imm8x4)) r0))
+
+(dshci movl5 "Store long word to memory (register indirect w/ displacement)"
+ ()
+ "mov.l $rm, @($imm4x4, $rn)"
+ (+ (f-op4 1) rn rm imm4x4)
+ (set (mem SI (add rn imm4x4)) rm))
+
+(dshci movl6 "Load long word to memory (register indirect w/ zero displacement)"
+ ()
+ "mov.l @$rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 2))
+ (set rn (mem SI rm)))
+
+(dshci movl7 "Load long word from memory (register indirect w/ post-increment)"
+ ()
+ "mov.l @${rm}+, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 6))
+ (sequence ()
+ (set rn (mem SI rm))
+ (if (eq (index-of rm) (index-of rn))
+ (set rm rn)
+ (set rm (add rm 4)))))
+
+(dshci movl8 "Load long word from memory (register/register indirect)"
+ ()
+ "mov.l @(r0, $rm), $rn"
+ (+ (f-op4 0) rn rm (f-sub4 14))
+ (set rn (mem SI (add r0 rm))))
+
+(dshci movl9 "Load long word from memory (GBR-relative w/ displacement)"
+ ()
+ "mov.l @($imm8x4, gbr), r0"
+ (+ (f-op8 #xc6) imm8x4)
+ (set r0 (mem SI (add gbr imm8x4))))
+
+(dshci movl10 "Load long word from memory (PC-relative w/ displacement)"
+ (ILLSLOT)
+ "mov.l @($imm8x4, pc), $rn"
+ (+ (f-op4 13) rn imm8x4)
+ (set rn (mem SI (add imm8x4 (and (add pc 4) (inv 3))))))
+
+(dshci movl11 "Load long word from memory (register indirect w/ displacement)"
+ ()
+ "mov.l @($imm4x4, $rm), $rn"
+ (+ (f-op4 5) rn rm imm4x4)
+ (set rn (mem SI (add rm imm4x4))))
+
+(dshci movw1 "Store word to memory (register indirect w/ zero displacement)"
+ ()
+ "mov.w $rm, @$rn"
+ (+ (f-op4 2) rn rm (f-sub4 1))
+ (set (mem HI rn) (subword HI rm 1)))
+
+(dshci movw2 "Store word to memory (register indirect w/ pre-decrement)"
+ ()
+ "mov.w $rm, @-$rn"
+ (+ (f-op4 2) rn rm (f-sub4 5))
+ (sequence ((DI addr))
+ (set addr (sub rn 2))
+ (set (mem HI addr) (subword HI rm 1))
+ (set rn addr)))
+
+(dshci movw3 "Store word to memory (register/register indirect)"
+ ()
+ "mov.w $rm, @(r0, $rn)"
+ (+ (f-op4 0) rn rm (f-sub4 5))
+ (set (mem HI (add r0 rn)) (subword HI rm 1)))
+
+(dshci movw4 "Store word to memory (GBR-relative w/ displacement)"
+ ()
+ "mov.w r0, @($imm8x2, gbr)"
+ (+ (f-op8 #xc1) imm8x2)
+ (set (mem HI (add gbr imm8x2)) (subword HI r0 1)))
+
+(dshci movw5 "Store word to memory (register indirect w/ displacement)"
+ ()
+ "mov.w r0, @($imm4x2, $rn)"
+ (+ (f-op8 #x81) rn imm4x2)
+ (set (mem HI (add rn imm4x2)) (subword HI r0 1)))
+
+(dshci movw6 "Load word from memory (register indirect w/ zero displacement)"
+ ()
+ "mov.w @$rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 1))
+ (set rn (ext SI (mem HI rm))))
+
+(dshci movw7 "Load word from memory (register indirect w/ post-increment)"
+ ()
+ "mov.w @${rm}+, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 5))
+ (sequence ((HI data))
+ (set data (mem HI rm))
+ (if (eq (index-of rm) (index-of rn))
+ (set rm (ext SI data))
+ (set rm (add rm 2)))
+ (set rn (ext SI data))))
+
+(dshci movw8 "Load word from memory (register/register indirect)"
+ ()
+ "mov.w @(r0, $rm), $rn"
+ (+ (f-op4 0) rn rm (f-sub4 13))
+ (set rn (ext SI (mem HI (add r0 rm)))))
+
+(dshci movw9 "Load word from memory (GBR-relative w/ displacement)"
+ ()
+ "mov.w @($imm8x2, gbr), r0"
+ (+ (f-op8 #xc5) imm8x2)
+ (set r0 (ext SI (mem HI (add gbr imm8x2)))))
+
+(dshci movw10 "Load word from memory (PC-relative w/ displacement)"
+ (ILLSLOT)
+ "mov.w @($imm8x2, pc), $rn"
+ (+ (f-op4 9) rn imm8x2)
+ (set rn (ext SI (mem HI (add (add pc 4) imm8x2)))))
+
+(dshci movw11 "Load word from memory (register indirect w/ displacement)"
+ ()
+ "mov.w @($imm4x2, $rm), r0"
+ (+ (f-op8 #x85) rm imm4x2)
+ (set r0 (ext SI (mem HI (add rm imm4x2)))))
+
+(dshci mova "Move effective address"
+ (ILLSLOT)
+ "mova @($imm8x4, pc), r0"
+ (+ (f-op8 #xc7) imm8x4)
+ (set r0 (add (and (add pc 4) (inv 3)) imm8x4)))
+
+(dshci movcal "Move with cache block allocation"
+ ()
+ "movca.l r0, @$rn"
+ (+ (f-op4 0) rn (f-sub8 #xc3))
+ (set (mem SI rn) r0))
+
+(dshci movt "Move t-bit"
+ ()
+ "movt $rn"
+ (+ (f-op4 0) rn (f-sub8 41))
+ (set rn (zext SI tbit)))
+
+(dshci mull "Multiply"
+ ()
+ "mul.l $rm, $rn"
+ (+ (f-op4 0) rn rm (f-sub4 7))
+ (set macl (mul rm rn)))
+
+(dshci mulsw "Multiply words (signed)"
+ ()
+ "muls.w $rm, $rn"
+ (+ (f-op4 2) rn rm (f-sub4 15))
+ (set macl (mul (ext SI (subword HI rm 1)) (ext SI (subword HI rn 1)))))
+
+(dshci muluw "Multiply words (unsigned)"
+ ()
+ "mulu.w $rm, $rn"
+ (+ (f-op4 2) rn rm (f-sub4 14))
+ (set macl (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))))
+
+(dshci neg "Negate"
+ ()
+ "neg $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 11))
+ (set rn (neg rm)))
+
+(dshci negc "Negate with carry"
+ ()
+ "negc $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 10))
+ (sequence ((BI flag))
+ (set flag (sub-cflag 0 rm tbit))
+ (set rn (subc 0 rm tbit))
+ (set tbit flag)))
+
+(dshci nop "No operation"
+ ()
+ "nop"
+ (+ (f-op16 9))
+ (nop))
+
+(dshci not "Bitwise NOT"
+ ()
+ "not $rm64, $rn64"
+ (+ (f-op4 6) rn64 rm64 (f-sub4 7))
+ (set rn64 (inv rm64)))
+
+(dshci ocbi "Invalidate operand cache block"
+ ()
+ "ocbi @$rn"
+ (+ (f-op4 0) rn (f-sub8 147))
+ (unimp "ocbi"))
+
+(dshci ocbp "Purge operand cache block"
+ ()
+ "ocbp @$rn"
+ (+ (f-op4 0) rn (f-sub8 163))
+ (unimp "ocbp"))
+
+(dshci ocbwb "Write back operand cache block"
+ ()
+ "ocbwb @$rn"
+ (+ (f-op4 0) rn (f-sub8 179))
+ (unimp "ocbwb"))
+
+(dshci or "Bitwise OR"
+ ()
+ "or $rm64, $rn64"
+ (+ (f-op4 2) rn64 rm64 (f-sub4 11))
+ (set rn64 (or rm64 rn64)))
+
+(dshci ori "Bitwise OR immediate"
+ ()
+ "or #$uimm8, r0"
+ (+ (f-op8 #xcb) uimm8)
+ (set r0 (or r0 (zext DI uimm8))))
+
+(dshci orb "Bitwise OR immediate"
+ ()
+ "or.b #$imm8, @(r0, gbr)"
+ (+ (f-op8 #xcf) imm8)
+ (sequence ((DI addr) (UQI data))
+ (set addr (add r0 gbr))
+ (set data (or (mem UQI addr) imm8))
+ (set (mem UQI addr) data)))
+
+(dshci pref "Prefetch data"
+ ()
+ "pref @$rn"
+ (+ (f-op4 0) rn (f-sub8 131))
+ (unimp "pref"))
+
+(dshci rotcl "Rotate with carry left"
+ ()
+ "rotcl $rn"
+ (+ (f-op4 4) rn (f-sub8 36))
+ (sequence ((BI temp))
+ (set temp (srl rn 31))
+ (set rn (or (sll rn 1) tbit))
+ (set tbit (if BI temp 1 0))))
+
+(dshci rotcr "Rotate with carry right"
+ ()
+ "rotcr $rn"
+ (+ (f-op4 4) rn (f-sub8 37))
+ (sequence ((BI lsbit) (SI temp))
+ (set lsbit (if BI (eq (and rn 1) 0) 0 1))
+ (set temp tbit)
+ (set rn (or (srl rn 1) (sll temp 31)))
+ (set tbit (if BI lsbit 1 0))))
+
+(dshci rotl "Rotate left"
+ ()
+ "rotl $rn"
+ (+ (f-op4 4) rn (f-sub8 4))
+ (sequence ((BI temp))
+ (set temp (srl rn 31))
+ (set rn (or (sll rn 1) temp))
+ (set tbit (if BI temp 1 0))))
+
+(dshci rotr "Rotate right"
+ ()
+ "rotr $rn"
+ (+ (f-op4 4) rn (f-sub8 5))
+ (sequence ((BI lsbit) (SI temp))
+ (set lsbit (if BI (eq (and rn 1) 0) 0 1))
+ (set temp lsbit)
+ (set rn (or (srl rn 1) (sll temp 31)))
+ (set tbit (if BI lsbit 1 0))))
+
+(dshci rts "Return from subroutine"
+ ()
+ "rts"
+ (+ (f-op16 11))
+ (delay 1 (set pc pr)))
+
+(dshci sets "Set S-bit"
+ ()
+ "sets"
+ (+ (f-op16 88))
+ (set sbit 1))
+
+(dshci sett "Set T-bit"
+ ()
+ "sett"
+ (+ (f-op16 24))
+ (set tbit 1))
+
+(dshci shad "Shift arithmetic dynamic"
+ ()
+ "shad $rm, $rn"
+ (+ (f-op4 4) rn rm (f-sub4 12))
+ (sequence ((QI shamt))
+ (set shamt (and QI rm 31))
+ (if (ge rm 0)
+ (set rn (sll rn shamt))
+ (if (ne shamt 0)
+ (set rn (sra rn (sub 32 shamt)))
+ (if (lt rn 0)
+ (set rn (neg 1))
+ (set rn 0))))))
+
+(dshci shal "Shift left arithmetic one bit"
+ ()
+ "shal $rn"
+ (+ (f-op4 4) rn (f-sub8 32))
+ (sequence ((BI t))
+ (set t (srl rn 31))
+ (set rn (sll rn 1))
+ (set tbit (if BI t 1 0))))
+
+(dshci shar "Shift right arithmetic one bit"
+ ()
+ "shar $rn"
+ (+ (f-op4 4) rn (f-sub8 33))
+ (sequence ((BI t))
+ (set t (and rn 1))
+ (set rn (sra rn 1))
+ (set tbit (if BI t 1 0))))
+
+(dshci shld "Shift logical dynamic"
+ ()
+ "shld $rm, $rn"
+ (+ (f-op4 4) rn rm (f-sub4 13))
+ (sequence ((QI shamt))
+ (set shamt (and QI rm 31))
+ (if (ge rm 0)
+ (set rn (sll rn shamt))
+ (if (ne shamt 0)
+ (set rn (srl rn (sub 32 shamt)))
+ (set rn 0)))))
+
+(dshci shll "Shift left logical one bit"
+ ()
+ "shll $rn"
+ (+ (f-op4 4) rn (f-sub8 0))
+ (sequence ((BI t))
+ (set t (srl rn 31))
+ (set rn (sll rn 1))
+ (set tbit (if BI t 1 0))))
+
+(dshci shll2 "Shift left logical two bits"
+ ()
+ "shll2 $rn"
+ (+ (f-op4 4) rn (f-sub8 8))
+ (set rn (sll rn 2)))
+
+(dshci shll8 "Shift left logical eight bits"
+ ()
+ "shll8 $rn"
+ (+ (f-op4 4) rn (f-sub8 24))
+ (set rn (sll rn 8)))
+
+(dshci shll16 "Shift left logical sixteen bits"
+ ()
+ "shll16 $rn"
+ (+ (f-op4 4) rn (f-sub8 40))
+ (set rn (sll rn 16)))
+
+(dshci shlr "Shift right logical one bit"
+ ()
+ "shlr $rn"
+ (+ (f-op4 4) rn (f-sub8 1))
+ (sequence ((BI t))
+ (set t (and rn 1))
+ (set rn (srl rn 1))
+ (set tbit (if BI t 1 0))))
+
+(dshci shlr2 "Shift right logical two bits"
+ ()
+ "shlr2 $rn"
+ (+ (f-op4 4) rn (f-sub8 9))
+ (set rn (srl rn 2)))
+
+(dshci shlr8 "Shift right logical eight bits"
+ ()
+ "shlr8 $rn"
+ (+ (f-op4 4) rn (f-sub8 25))
+ (set rn (srl rn 8)))
+
+(dshci shlr16 "Shift right logical sixteen bits"
+ ()
+ "shlr16 $rn"
+ (+ (f-op4 4) rn (f-sub8 41))
+ (set rn (srl rn 16)))
+
+(dshci stc-gbr "Store control register (GBR)"
+ ()
+ "stc gbr, $rn"
+ (+ (f-op4 0) rn (f-sub8 18))
+ (set rn gbr))
+
+(dshci stcl-gbr "Store control register (GBR)"
+ ()
+ "stc.l gbr, @-$rn"
+ (+ (f-op4 4) rn (f-sub8 19))
+ (sequence ((DI addr))
+ (set addr (sub rn 4))
+ (set (mem SI addr) gbr)
+ (set rn addr)))
+
+(dshci sts-fpscr "Store status register (FPSCR)"
+ ()
+ "sts fpscr, $rn"
+ (+ (f-op4 0) rn (f-sub8 106))
+ (set rn fpscr))
+
+(dshci stsl-fpscr "Store status register (FPSCR)"
+ ()
+ "sts.l fpscr, @-$rn"
+ (+ (f-op4 4) rn (f-sub8 98))
+ (sequence ((DI addr))
+ (set addr (sub rn 4))
+ (set (mem SI addr) fpscr)
+ (set rn addr)))
+
+(dshci sts-fpul "Store status register (FPUL)"
+ ()
+ "sts fpul, $rn"
+ (+ (f-op4 0) rn (f-sub8 90))
+ (set rn (subword SI fpul 0)))
+
+(dshci stsl-fpul "Store status register (FPUL)"
+ ()
+ "sts.l fpul, @-$rn"
+ (+ (f-op4 4) rn (f-sub8 82))
+ (sequence ((DI addr))
+ (set addr (sub rn 4))
+ (set (mem SF addr) fpul)
+ (set rn addr)))
+
+(dshci sts-mach "Store status register (MACH)"
+ ()
+ "sts mach, $rn"
+ (+ (f-op4 0) rn (f-sub8 10))
+ (set rn mach))
+
+(dshci stsl-mach "Store status register (MACH)"
+ ()
+ "sts.l mach, @-$rn"
+ (+ (f-op4 4) rn (f-sub8 2))
+ (sequence ((DI addr))
+ (set addr (sub rn 4))
+ (set (mem SI addr) mach)
+ (set rn addr)))
+
+(dshci sts-macl "Store status register (MACL)"
+ ()
+ "sts macl, $rn"
+ (+ (f-op4 0) rn (f-sub8 26))
+ (set rn macl))
+
+(dshci stsl-macl "Store status register (MACL)"
+ ()
+ "sts.l macl, @-$rn"
+ (+ (f-op4 4) rn (f-sub8 18))
+ (sequence ((DI addr))
+ (set addr (sub rn 4))
+ (set (mem SI addr) macl)
+ (set rn addr)))
+
+(dshci sts-pr "Store status register (PR)"
+ ()
+ "sts pr, $rn"
+ (+ (f-op4 0) rn (f-sub8 42))
+ (set rn pr))
+
+(dshci stsl-pr "Store status register (PR)"
+ ()
+ "sts.l pr, @-$rn"
+ (+ (f-op4 4) rn (f-sub8 34))
+ (sequence ((DI addr))
+ (set addr (sub rn 4))
+ (set (mem SI addr) pr)
+ (set rn addr)))
+
+(dshci sub "Subtract"
+ ()
+ "sub $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 8))
+ (set rn (sub rn rm)))
+
+(dshci subc "Subtract and detect carry"
+ ()
+ "subc $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 10))
+ (sequence ((BI flag))
+ (set flag (sub-cflag rn rm tbit))
+ (set rn (subc rn rm tbit))
+ (set tbit flag)))
+
+(dshci subv "Subtract and detect overflow"
+ ()
+ "subv $rm, $rn"
+ (+ (f-op4 3) rn rm (f-sub4 11))
+ (sequence ((BI t))
+ (set t (sub-oflag rn rm 0))
+ (set rn (sub rn rm))
+ (set tbit (if BI t 1 0))))
+
+(dshci swapb "Swap bytes"
+ ()
+ "swap.b $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 8))
+ (sequence ((UHI top-half) (UQI byte1) (UQI byte0))
+ (set top-half (subword HI rm 0))
+ (set byte1 (subword QI rm 2))
+ (set byte0 (subword QI rm 3))
+ (set rn (or SI (sll SI top-half 16) (or SI (sll SI byte0 8) byte1)))))
+
+(dshci swapw "Swap words"
+ ()
+ "swap.w $rm, $rn"
+ (+ (f-op4 6) rn rm (f-sub4 9))
+ (set rn (or (srl rm 16) (sll rm 16))))
+
+(dshci tasb "Test and set byte"
+ ()
+ "tas.b @$rn"
+ (+ (f-op4 4) rn (f-sub8 27))
+ (sequence ((UQI byte))
+ (set byte (mem UQI rn))
+ (set tbit (if BI (eq byte 0) 1 0))
+ (set byte (or byte 128))
+ (set (mem UQI rn) byte)))
+
+(dshci trapa "Trap"
+ (ILLSLOT)
+ "trapa #$uimm8"
+ (+ (f-op8 #xc3) uimm8)
+ (c-call "sh64_compact_trapa" uimm8 pc))
+
+(dshci tst "Test and set t-bit"
+ ()
+ "tst $rm, $rn"
+ (+ (f-op4 2) rn rm (f-sub4 8))
+ (set tbit (if BI (eq (and rm rn) 0) 1 0)))
+
+(dshci tsti "Test and set t-bit immediate"
+ ()
+ "tst #$uimm8, r0"
+ (+ (f-op8 #xc8) uimm8)
+ (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0)))
+
+(dshci tstb "Test and set t-bit immedate with memory byte"
+ ()
+ "tst.b #$imm8, @(r0, gbr)"
+ (+ (f-op8 #xcc) imm8)
+ (sequence ((DI addr))
+ (set addr (add r0 gbr))
+ (set tbit (if BI (eq (and (mem UQI addr) imm8) 0) 1 0))))
+
+(dshci xor "Exclusive OR"
+ ()
+ "xor $rm64, $rn64"
+ (+ (f-op4 2) rn64 rm64 (f-sub4 10))
+ (set rn64 (xor rn64 rm64)))
+
+(dshci xori "Exclusive OR immediate"
+ ()
+ "xor #$uimm8, r0"
+ (+ (f-op8 #xca) uimm8)
+ (set (reg h-gr 0) (xor (reg h-gr 0) (zext DI uimm8))))
+
+(dshci xorb "Exclusive OR immediate with memory byte"
+ ()
+ "xor.b #$imm8, @(r0, gbr)"
+ (+ (f-op8 #xce) imm8)
+ (sequence ((DI addr) (UQI data))
+ (set addr (add r0 gbr))
+ (set data (xor (mem UQI addr) imm8))
+ (set (mem UQI addr) data)))
+
+(dshci xtrct "Extract"
+ ()
+ "xtrct $rm, $rn"
+ (+ (f-op4 2) rn rm (f-sub4 13))
+ (set rn (or (sll rm 16) (srl rn 16))))
Index: sh64-media.cpu
===================================================================
RCS file: sh64-media.cpu
diff -N sh64-media.cpu
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sh64-media.cpu 19 Feb 2004 16:01:27 -0000
@@ -0,0 +1,1732 @@
+; Hitachi SHmedia instruction set description. -*- Scheme -*-
+;
+; Copyright 2000, 2001 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc; developed under contract from Hitachi
+; Semiconductor (America) Inc.
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 2 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+
+; dshmf -- define-normal-sh-media-field
+
+(define-pmacro (dshmf xname xcomment ignored xstart xlength)
+ (dnf xname xcomment ((ISA media)) xstart xlength))
+
+; dshmop -- define-normal-sh-media-operand
+
+(define-pmacro (dshmop xname xcomment ignored xhardware xfield)
+ (dnop xname xcomment ((ISA media)) xhardware xfield))
+
+; dnshmi -- define-normal-sh-media-insn
+
+(define-pmacro (dshmi xname xcomment xattrs xsyntax xformat xsemantics)
+ (define-insn
+ (name xname)
+ (comment xcomment)
+ (.splice attrs (.unsplice xattrs) (ISA media))
+ (syntax xsyntax)
+ (format xformat)
+ (semantics xsemantics)))
+
+; Saturation functions.
+; Force a value `i' into words `n' bits wide.
+; See Hitachi SH-5 CPU core, volume 2, p. 25 for details.
+
+; saturate -- signed saturatation function
+
+(define-pmacro (saturate mode n i)
+ (if mode (lt i (neg mode (sll mode 1 (sub n 1))))
+ (neg (sll mode 1 (sub n 1)))
+ (if mode (lt i (sll mode 1 (sub n 1)))
+ i
+ (sub mode (sll mode 1 (sub n 1)) 1))))
+
+; usaturate -- unsigned saturation function
+
+(define-pmacro (usaturate mode n i)
+ (if mode (lt i (const mode 0))
+ (const mode 0)
+ (if mode (lt i (sll mode 1 n))
+ i
+ (sub mode (sll mode 1 n) 1))))
+
+
+; Ifields.
+
+(dshmf f-op "Opcode" () 31 6)
+(dshmf f-ext "Extension opcode" () 19 4)
+(dshmf f-rsvd "Reserved" (RESERVED) 3 4)
+
+(dshmf f-left "Left register" () 25 6)
+(dshmf f-right "Right register" () 15 6)
+(dshmf f-dest "Destination register" () 9 6)
+
+(define-multi-ifield
+ (name f-left-right)
+ (comment "Left and right matched register pair")
+ (attrs (ISA media))
+ (mode UINT)
+ (subfields f-left f-right)
+ (insert (sequence ()
+ (set (ifield f-left)
+ (and (ifield f-left-right) 63))
+ (set (ifield f-right)
+ (and (ifield f-left-right) 63))))
+ (extract (set (ifield f-left-right) (ifield f-left)))
+)
+
+(dshmf f-tra "Target register" () 6 3)
+(dshmf f-trb "Target register" () 22 3)
+(dshmf f-likely "Likely bit" () 9 1)
+(dshmf f-25 "Three unused bits at bit 25" () 25 3)
+(dshmf f-8-2 "Two unused bits at bit 8" () 8 2)
+
+(df f-imm6 "Immediate value (6 bits)" ((ISA media)) 15 6 INT #f #f)
+(df f-imm10 "Immediate value (10 bits)" ((ISA media)) 19 10 INT #f #f)
+(df f-imm16 "Immediate value (16 bits)" ((ISA media)) 25 16 INT #f #f)
+
+(dshmf f-uimm6 "Immediate value (6 bits)" () 15 6)
+(dshmf f-uimm16 "Immediate value (16 bits)" () 25 16)
+
+; Various displacement fields.
+; The 10 bit field, for example, has different scaling for displacements.
+
+(df f-disp6 "Displacement (6 bits)" ((ISA media)) 15 6 INT #f #f)
+
+(df f-disp6x32 "Displacement (6 bits)" ((ISA media)) 15 6 INT
+ ((value pc) (sra SI value 5))
+ ((value pc) (sll SI value 5)))
+
+(df f-disp10 "Displacement (10 bits)" ((ISA media)) 19 10 INT #f #f)
+
+(df f-disp10x8 "Displacement (10 bits)" ((ISA media)) 19 10 INT
+ ((value pc) (sra SI value 3))
+ ((value pc) (sll SI value 3)))
+
+(df f-disp10x4 "Displacement (10 bits)" ((ISA media)) 19 10 INT
+ ((value pc) (sra SI value 2))
+ ((value pc) (sll SI value 2)))
+
+(df f-disp10x2 "Displacement (10 bits)" ((ISA media)) 19 10 INT
+ ((value pc) (sra SI value 1))
+ ((value pc) (sll SI value 1)))
+
+(df f-disp16 "Displacement (16 bits)" ((ISA media) PCREL-ADDR) 25 16 INT
+ ((value pc) (sra DI value 2))
+ ((value pc) (add DI (sll DI value 2) pc)))
+
+
+; Operands.
+
+(dshmop rm "Left general purpose reg" () h-gr f-left)
+(dshmop rn "Right general purpose reg" () h-gr f-right)
+(dshmop rd "Destination general purpose reg" () h-gr f-dest)
+
+(dshmop frg "Left single precision register" () h-fr f-left)
+(dshmop frh "Right single precision register" () h-fr f-right)
+(dshmop frf "Destination single precision reg" () h-fr f-dest)
+(dshmop frgh "Single precision register pair" () h-fr f-left-right)
+
+(dshmop fpf "Pair of single precision registers" () h-fp f-dest)
+
+(dshmop fvg "Left single precision vector" () h-fv f-left)
+(dshmop fvh "Right single precision vector" () h-fv f-right)
+(dshmop fvf "Destination single precision vector" () h-fv f-dest)
+(dshmop mtrxg "Left single precision matrix" () h-fmtx f-left)
+
+(dshmop drg "Left double precision register" () h-dr f-left)
+(dshmop drh "Right double precision register" () h-dr f-right)
+(dshmop drf "Destination double precision reg" () h-dr f-dest)
+(dshmop drgh "Double precision register pair" () h-dr f-left-right)
+
+(dshmop fpscr "Floating point status register" () h-fpscr f-nil)
+(dshmop crj "Control register j" () h-cr f-dest)
+(dshmop crk "Control register k" () h-cr f-left)
+
+(dshmop tra "Target register a" () h-tr f-tra)
+(dshmop trb "Target register b" () h-tr f-trb)
+
+(dshmop disp6 "Displacement (6 bits)" () h-sint f-disp6)
+(dshmop disp6x32 "Displacement (6 bits, scale 32)" () h-sint f-disp6x32)
+(dshmop disp10 "Displacement (10 bits)" () h-sint f-disp10)
+(dshmop disp10x2 "Displacement (10 bits, scale 2)" () h-sint f-disp10x2)
+(dshmop disp10x4 "Displacement (10 bits, scale 4)" () h-sint f-disp10x4)
+(dshmop disp10x8 "Displacement (10 bits, scale 8)" () h-sint f-disp10x8)
+(dshmop disp16 "Displacement (16 bits)" () h-sint f-disp16)
+
+(dshmop imm6 "Immediate (6 bits)" () h-sint f-imm6)
+(dshmop imm10 "Immediate (10 bits)" () h-sint f-imm10)
+(dshmop imm16 "Immediate (16 bits)" () h-sint f-imm16)
+(dshmop uimm6 "Immediate (6 bits)" () h-uint f-uimm6)
+(dshmop uimm16 "Unsigned immediate (16 bits)" () h-uint f-uimm16)
+
+; FIXME: provide these parse/print functions in `sh-media.opc'.
+
+(define-operand (name likely) (comment "Likely branch?") (attrs (ISA media))
+ (type h-uint) (index f-likely) (handlers (parse "likely") (print "likely")))
+
+
+; Instructions.
+
+(dshmi add "Add"
+ ()
+ "add $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 9) rn rd (f-rsvd 0))
+ (set rd (add rm rn)))
+
+(dshmi addl "Add long"
+ ()
+ "add.l $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 8) rn rd (f-rsvd 0))
+ (set rd (add (subword SI rm 1) (subword SI rn 1))))
+
+(dshmi addi "Add immediate"
+ ()
+ "addi $rm, $disp10, $rd"
+ (+ (f-op 52) rm disp10 rd (f-rsvd 0))
+ (set rd (add rm (ext DI disp10))))
+
+(dshmi addil "Add immediate long"
+ ()
+ "addi.l $rm, $disp10, $rd"
+ (+ (f-op 53) rm disp10 rd (f-rsvd 0))
+ (set rd (ext DI (add (ext SI disp10) (subword SI rm 1)))))
+
+(dshmi addzl "Add zero extended long"
+ ()
+ "addz.l $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 12) rn rd (f-rsvd 0))
+ (set rd (zext DI (add (subword SI rm 1) (subword SI rn 1)))))
+
+(dshmi alloco "Allocate operand cache block"
+ ()
+ "alloco $rm, $disp6x32"
+ (+ (f-op 56) rm (f-ext 4) disp6x32 (f-dest 63) (f-rsvd 0))
+ (unimp "alloco"))
+
+(dshmi and "AND"
+ ()
+ "and $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 11) rn rd (f-rsvd 0))
+ (set rd (and rm rn)))
+
+(dshmi andc "AND complement"
+ ()
+ "andc $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 15) rn rd (f-rsvd 0))
+ (set rd (and rm (inv rn))))
+
+(dshmi andi "AND immediate"
+ ()
+ "andi $rm, $disp10, $rd"
+ (+ (f-op 54) rm disp10 rd (f-rsvd 0))
+ (set rd (and rm (ext DI disp10))))
+
+(dshmi beq "Branch if equal"
+ ()
+ "beq$likely $rm, $rn, $tra"
+ (+ (f-op 25) rm (f-ext 1) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (if (eq rm rn)
+ (set pc tra)))
+
+(dshmi beqi "Branch if equal immediate"
+ ()
+ "beqi$likely $rm, $imm6, $tra"
+ (+ (f-op 57) rm (f-ext 1) imm6 likely (f-8-2 0) tra (f-rsvd 0))
+ (if (eq rm (ext DI imm6))
+ (set pc tra)))
+
+(dshmi bge "Branch if greater than or equal"
+ ()
+ "bge$likely $rm, $rn, $tra"
+ (+ (f-op 25) rm (f-ext 3) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (if (ge rm rn)
+ (set pc tra)))
+
+(dshmi bgeu "Branch if greater than or equal (unsigned comparison)"
+ ()
+ "bgeu$likely $rm, $rn, $tra"
+ (+ (f-op 25) rm (f-ext 11) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (if (geu rm rn)
+ (set pc tra)))
+
+(dshmi bgt "Branch greater than"
+ ()
+ "bgt$likely $rm, $rn, $tra"
+ (+ (f-op 25) rm (f-ext 7) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (if (gt rm rn)
+ (set pc tra)))
+
+(dshmi bgtu "Branch greater than (unsigned comparison)"
+ ()
+ "bgtu$likely $rm, $rn, $tra"
+ (+ (f-op 25) rm (f-ext 15) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (if (gtu rm rn)
+ (set pc tra)))
+
+(dshmi blink "Branch and link"
+ ()
+ "blink $trb, $rd"
+ (+ (f-op 17) (f-25 0) trb (f-ext 1) (f-right 63) rd (f-rsvd 0))
+ (sequence ()
+ (set rd (or (add pc 4) 1))
+ (set pc trb)))
+
+(dshmi bne "Branch if not equal"
+ ()
+ "bne$likely $rm, $rn, $tra"
+ (+ (f-op 25) rm (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (if (ne rm rn)
+ (set pc tra)))
+
+(dshmi bnei "Branch if not equal immediate"
+ ()
+ "bnei$likely $rm, $imm6, $tra"
+ (+ (f-op 57) rm (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (if (ne rm (ext DI imm6))
+ (set pc tra)))
+
+(dshmi brk "Breakpoint instruction"
+ ()
+ "brk"
+ (+ (f-op 27) (f-left 63) (f-ext 5) (f-right 63) (f-dest 63) (f-rsvd 0))
+ (c-call "sh64_break" pc))
+
+(define-pmacro (-byterev-step)
+ (sequence ()
+ (set result (or (sll result 8) (and source 255)))
+ (set source (srl source 8)))
+)
+
+(dshmi byterev "Byte reverse"
+ ()
+ "byterev $rm, $rd"
+ (+ (f-op 0) rm (f-ext 15) (f-right 63) rd (f-rsvd 0))
+ (sequence ((DI source) (DI result))
+ (set source rm)
+ (set result 0)
+ (-byterev-step)
+ (-byterev-step)
+ (-byterev-step)
+ (-byterev-step)
+ (-byterev-step)
+ (-byterev-step)
+ (-byterev-step)
+ (-byterev-step)
+ (set rd result)))
+
+(dshmi cmpeq "Compare equal"
+ ()
+ "cmpeq $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 1) rn rd (f-rsvd 0))
+ (set rd (if DI (eq rm rn) 1 0)))
+
+(dshmi cmpgt "Compare greater than"
+ ()
+ "cmpgt $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 3) rn rd (f-rsvd 0))
+ (set rd (if DI (gt rm rn) 1 0)))
+
+(dshmi cmpgtu "Compare greater than (unsigned comparison)"
+ ()
+ "cmpgtu $rm,$rn, $rd"
+ (+ (f-op 0) rm (f-ext 7) rn rd (f-rsvd 0))
+ (set rd (if DI (gtu rm rn) 1 0)))
+
+(dshmi cmveq "Conditional move if equal to zero"
+ ()
+ "cmveq $rm, $rn, $rd"
+ (+ (f-op 8) rm (f-ext 1) rn rd (f-rsvd 0))
+ (if (eq rm 0)
+ (set rd rn)))
+
+(dshmi cmvne "Conditional move if not equal to zero"
+ ()
+ "cmvne $rm, $rn, $rd"
+ (+ (f-op 8) rm (f-ext 5) rn rd (f-rsvd 0))
+ (if (ne rm 0)
+ (set rd rn)))
+
+(dshmi fabsd "Floating point absolute (double)"
+ ()
+ "fabs.d $drgh, $drf"
+ (+ (f-op 6) drgh (f-ext 1) drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_fabsd" drgh)))
+
+(dshmi fabss "Floating point absolute (single)"
+ ()
+ "fabs.s $frgh, $frf"
+ (+ (f-op 6) frgh (f-ext 0) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fabss" frgh)))
+
+(dshmi faddd "Floating point add (double)"
+ ()
+ "fadd.d $drg, $drh, $drf"
+ (+ (f-op 13) drg (f-ext 1) drh drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_faddd" drg drh)))
+
+(dshmi fadds "Floating point add (single)"
+ ()
+ "fadd.s $frg, $frh, $frf"
+ (+ (f-op 13) frg (f-ext 0) frh frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fadds" frg frh)))
+
+(dshmi fcmpeqd "Floating point compare if equal (double)"
+ ()
+ "fcmpeq.d $drg, $drh, $rd"
+ (+ (f-op 12) drg (f-ext 9) drh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpeqd" drg drh))))
+
+(dshmi fcmpeqs "Floating point compare if equal (single)"
+ ()
+ "fcmpeq.s $frg, $frh, $rd"
+ (+ (f-op 12) frg (f-ext 8) frh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpeqs" frg frh))))
+
+(dshmi fcmpged "Floating compare compare if greater than or equal (double)"
+ ()
+ "fcmpge.d $drg, $drh, $rd"
+ (+ (f-op 12) drg (f-ext 15) drh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpged" drg drh))))
+
+(dshmi fcmpges "Floating point compare if greater than or equal (single)"
+ ()
+ "fcmpge.s $frg, $frh, $rd"
+ (+ (f-op 12) frg (f-ext 14) frh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpges" frg frh))))
+
+(dshmi fcmpgtd "Floating point compare if greater than (double)"
+ ()
+ "fcmpgt.d $drg, $drh, $rd"
+ (+ (f-op 12) drg (f-ext 13) drh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpgtd" drg drh))))
+
+(dshmi fcmpgts "Floating point compare if greater than (single)"
+ ()
+ "fcmpgt.s $frg, $frh, $rd"
+ (+ (f-op 12) frg (f-ext 12) frh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpgts" frg frh))))
+
+(dshmi fcmpund "Floating point unordered comparison (double)"
+ ()
+ "fcmpun.d $drg, $drh, $rd"
+ (+ (f-op 12) drg (f-ext 11) drh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpund" drg drh))))
+
+(dshmi fcmpuns "Floating point unordered comparison (single)"
+ ()
+ "fcmpun.s $frg, $frh, $rd"
+ (+ (f-op 12) frg (f-ext 10) frh rd (f-rsvd 0))
+ (set rd (zext DI (c-call BI "sh64_fcmpuns" frg frh))))
+
+(dshmi fcnvds "Floating point coversion (double to single)"
+ ()
+ "fcnv.ds $drgh, $frf"
+ (+ (f-op 14) drgh (f-ext 7) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fcnvds" drgh)))
+
+(dshmi fcnvsd "Floating point conversion (single to double)"
+ ()
+ "fcnv.sd $frgh, $drf"
+ (+ (f-op 14) frgh (f-ext 6) drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_fcnvsd" frgh)))
+
+(dshmi fdivd "Floating point divide (double)"
+ ()
+ "fdiv.d $drg, $drh, $drf"
+ (+ (f-op 13) drg (f-ext 5) drh drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_fdivd" drg drh)))
+
+(dshmi fdivs "Floating point divide (single)"
+ ()
+ "fdiv.s $frg, $frh, $frf"
+ (+ (f-op 13) frg (f-ext 4) frh frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fdivs" frg frh)))
+
+(dshmi fgetscr "Floating point get from FPSCR"
+ ()
+ "fgetscr $frf"
+ (+ (f-op 7) (f-left 63) (f-ext 2) (f-right 63) frf (f-rsvd 0))
+ (unimp "fputscr"))
+ ; FIXME: this should work!
+ ; (set frf fpscr))
+
+(dshmi fiprs "Floating point inner product (single)"
+ ()
+ "fipr.s $fvg, $fvh, $frf"
+ (+ (f-op 5) fvg (f-ext 6) fvh frf (f-rsvd 0))
+ (sequence ((UQI g) (UQI h) (SF temp))
+ (set g (index-of fvg))
+ (set h (index-of fvh))
+ (set temp (c-call SF "sh64_fmuls" (reg h-fr g) (reg h-fr h)))
+ (set temp (c-call SF "sh64_fadds" temp
+ (c-call SF "sh64_fmuls" (reg h-fr (add g 1)) (reg h-fr (add h 1)))))
+ (set temp (c-call SF "sh64_fadds" temp
+ (c-call SF "sh64_fmuls" (reg h-fr (add g 2)) (reg h-fr (add h 2)))))
+ (set temp (c-call SF "sh64_fadds" temp
+ (c-call SF "sh64_fmuls" (reg h-fr (add g 3)) (reg h-fr (add h 3)))))
+ (set frf temp)))
+
+(dshmi fldd "Floating point load (double)"
+ ()
+ "fld.d $rm, $disp10x8, $drf"
+ (+ (f-op 39) rm disp10x8 drf (f-rsvd 0))
+ (set drf (mem DF (add rm disp10x8))))
+
+(dshmi fldp "Floating point load (pair of singles)"
+ ()
+ "fld.p $rm, $disp10x8, $fpf"
+ (+ (f-op 38) rm disp10x8 fpf (f-rsvd 0))
+ (sequence ((QI f))
+ (set f (index-of fpf))
+ (set (reg h-fr f) (mem SF (add rm disp10x8)))
+ (set (reg h-fr (add f 1)) (mem SF (add rm (add disp10x8 4))))))
+
+(dshmi flds "Floating point load (single)"
+ ()
+ "fld.s $rm, $disp10x4, $frf"
+ (+ (f-op 37) rm disp10x4 frf (f-rsvd 0))
+ (set frf (mem SF (add rm disp10x4))))
+
+(dshmi fldxd "Floating point extended load (double)"
+ ()
+ "fldx.d $rm, $rn, $drf"
+ (+ (f-op 7) rm (f-ext 9) rn frf (f-rsvd 0))
+ (set drf (mem DF (add rm rn))))
+
+(dshmi fldxp "Floating point extended load (pair of singles)"
+ ()
+ "fldx.p $rm, $rn, $fpf"
+ (+ (f-op 7) rm (f-ext 13) rn fpf (f-rsvd 0))
+ (sequence ((QI f))
+ (set f (index-of fpf))
+ (set (reg h-fr f) (mem SF (add rm rn)))
+ (set (reg h-fr (add f 1)) (mem SF (add rm (add rn 4))))))
+
+(dshmi fldxs "Floating point extended load (single)"
+ ()
+ "fldx.s $rm, $rn, $frf"
+ (+ (f-op 7) rm (f-ext 8) rn frf (f-rsvd 0))
+ (set frf (mem SF (add rm rn))))
+
+(dshmi floatld "Floating point conversion (long to double)"
+ ()
+ "float.ld $frgh, $drf"
+ (+ (f-op 14) frgh (f-ext 14) drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_floatld" frgh)))
+
+(dshmi floatls "Floating point conversion (long to single)"
+ ()
+ "float.ls $frgh, $frf"
+ (+ (f-op 14) frgh (f-ext 12) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_floatls" frgh)))
+
+(dshmi floatqd "Floating point conversion (quad to double)"
+ ()
+ "float.qd $drgh, $drf"
+ (+ (f-op 14) drgh (f-ext 13) drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_floatqd" drgh)))
+
+(dshmi floatqs "Floating point conversion (quad to single)"
+ ()
+ "float.qs $drgh, $frf"
+ (+ (f-op 14) drgh (f-ext 15) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_floatqs" drgh)))
+
+(dshmi fmacs "Floating point multiply and accumulate (single)"
+ ()
+ "fmac.s $frg, $frh, $frf"
+ (+ (f-op 13) frg (f-ext 14) frh frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fadds" frf (c-call SF "sh64_fmuls" frg frh))))
+
+(dshmi fmovd "Floating point move double"
+ ()
+ "fmov.d $drgh, $drf"
+ (+ (f-op 14) drgh (f-ext 1) drf (f-rsvd 0))
+ (set drf drgh))
+
+(dshmi fmovdq "Floating point move (double to quad integer)"
+ ()
+ "fmov.dq $drgh, $rd"
+ (+ (f-op 12) drgh (f-ext 1) rd (f-rsvd 0))
+ (set rd (subword DI drgh 0)))
+
+(dshmi fmovls "Floating point move (lower to single)"
+ ()
+ "fmov.ls $rm, $frf"
+ (+ (f-op 7) rm (f-ext 0) (f-right 63) frf (f-rsvd 0))
+ (set frf (subword SF (subword SI rm 1) 0)))
+
+(dshmi fmovqd "Floating point move (quad to double)"
+ ()
+ "fmov.qd $rm, $drf"
+ (+ (f-op 7) rm (f-ext 1) (f-right 63) frf (f-rsvd 0))
+ (set drf (subword DF rm 0)))
+
+(dshmi fmovs "Floating point move (single)"
+ ()
+ "fmov.s $frgh, $frf"
+ (+ (f-op 14) frgh (f-ext 0) frf (f-rsvd 0))
+ (set frf frgh))
+
+(dshmi fmovsl "Floating point move (single to lower)"
+ ()
+ "fmov.sl $frgh, $rd"
+ (+ (f-op 12) frgh (f-ext 0) rd (f-rsvd 0))
+ (set rd (ext DI (subword SI frgh 1))))
+
+(dshmi fmuld "Floating point multiply (double)"
+ ()
+ "fmul.d $drg, $drh, $drf"
+ (+ (f-op 13) drg (f-ext 7) drh drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_fmuld" drg drh)))
+
+(dshmi fmuls "Floating point multiply (single)"
+ ()
+ "fmul.s $frg, $frh, $frf"
+ (+ (f-op 13) frg (f-ext 6) frh frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fmuls" frg frh)))
+
+(dshmi fnegd "Floating point negate (double)"
+ ()
+ "fneg.d $drgh, $drf"
+ (+ (f-op 6) drgh (f-ext 3) drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_fnegd" drgh)))
+
+(dshmi fnegs "Floating point negate (single)"
+ ()
+ "fneg.s $frgh, $frf"
+ (+ (f-op 6) frgh (f-ext 2) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fnegs" frgh)))
+
+(dshmi fputscr "Floating point put to FPSCR"
+ ()
+ "fputscr $frgh"
+ (+ (f-op 12) frgh (f-ext 2) (f-dest 63) (f-rsvd 0))
+ (unimp "fputscr"))
+ ; FIXME: this should work!
+ ; (set fpscr (subword SI frgh 0)))
+
+(dshmi fsqrtd "Floating point square root (double)"
+ ()
+ "fsqrt.d $drgh, $drf"
+ (+ (f-op 14) drgh (f-ext 5) drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_fsqrtd" drgh)))
+
+(dshmi fsqrts "Floating point squart root (single)"
+ ()
+ "fsqrt.s $frgh, $frf"
+ (+ (f-op 14) frgh (f-ext 4) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fsqrts" frgh)))
+
+(dshmi fstd "Floating point store (double)"
+ ()
+ "fst.d $rm, $disp10x8, $drf"
+ (+ (f-op 47) rm disp10x8 drf (f-rsvd 0))
+ (set (mem DF (add rm disp10x8)) drf))
+
+(dshmi fstp "Floating point store (pair of singles)"
+ ()
+ "fst.p $rm, $disp10x8, $fpf"
+ (+ (f-op 46) rm disp10x8 fpf (f-rsvd 0))
+ (sequence ((QI f))
+ (set f (index-of fpf))
+ (set (mem SF (add rm disp10x8)) (reg h-fr f))
+ (set (mem SF (add rm (add disp10x8 4))) (reg h-fr (add f 1)))))
+
+(dshmi fsts "Floating point store (single)"
+ ()
+ "fst.s $rm, $disp10x4, $frf"
+ (+ (f-op 45) rm disp10x4 frf (f-rsvd 0))
+ (set (mem SF (add rm disp10x4)) frf))
+
+(dshmi fstxd "Floating point extended store (double)"
+ ()
+ "fstx.d $rm, $rn, $drf"
+ (+ (f-op 15) rm (f-ext 9) rn drf (f-rsvd 0))
+ (set (mem DF (add rm rn)) drf))
+
+(dshmi fstxp "Floating point extended store (pair of singles)"
+ ()
+ "fstx.p $rm, $rn, $fpf"
+ (+ (f-op 15) rm (f-ext 13) rn fpf (f-rsvd 0))
+ (sequence ((QI f))
+ (set f (index-of fpf))
+ (set (mem SF (add rm rn)) (reg h-fr f))
+ (set (mem SF (add rm (add rn 4))) (reg h-fr (add f 1)))))
+
+(dshmi fstxs "Floating point extended store (single)"
+ ()
+ "fstx.s $rm, $rn, $frf"
+ (+ (f-op 15) rm (f-ext 8) rn frf (f-rsvd 0))
+ (set (mem SF (add rm rn)) frf))
+
+(dshmi fsubd "Floating point subtract (double)"
+ ()
+ "fsub.d $drg, $drh, $drf"
+ (+ (f-op 13) frg (f-ext 3) frh frf (f-rsvd 0))
+ (set drf (c-call DF "sh64_fsubd" drg drh)))
+
+(dshmi fsubs "Floating point subtract (single)"
+ ()
+ "fsub.s $frg, $frh, $frf"
+ (+ (f-op 13) frg (f-ext 2) frh frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_fsubs" frg frh)))
+
+(dshmi ftrcdl "Floating point conversion (double to long)"
+ ()
+ "ftrc.dl $drgh, $frf"
+ (+ (f-op 14) drgh (f-ext 11) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_ftrcdl" drgh)))
+
+(dshmi ftrcsl "Floating point conversion (single to long)"
+ ()
+ "ftrc.sl $frgh, $frf"
+ (+ (f-op 14) frgh (f-ext 8) frf (f-rsvd 0))
+ (set frf (c-call SF "sh64_ftrcsl" frgh)))
+
+(dshmi ftrcdq "Floating point conversion (double to quad)"
+ ()
+ "ftrc.dq $drgh, $drf"
+ (+ (f-op 14) drgh (f-ext 9) frf (f-rsvd 0))
+ (set drf (c-call DF "sh64_ftrcdq" drgh)))
+
+(dshmi ftrcsq "Floating point conversion (single to quad)"
+ ()
+ "ftrc.sq $frgh, $drf"
+ (+ (f-op 14) frgh (f-ext 10) drf (f-rsvd 0))
+ (set drf (c-call DF "sh64_ftrcsq" frgh)))
+
+(dshmi ftrvs "Floating point matrix multiply"
+ ()
+ "ftrv.s $mtrxg, $fvh, $fvf"
+ (+ (f-op 5) mtrxg (f-ext 14) fvh fvf (f-rsvd 0))
+ (c-call "sh64_ftrvs" (index-of mtrxg) (index-of fvh) (index-of fvf)))
+
+(dshmi getcfg "Get configuration register"
+ ()
+ "getcfg $rm, $disp6, $rd"
+ (+ (f-op 48) rm (f-ext 15) disp6 rd (f-rsvd 0))
+ (unimp "getcfg"))
+
+(dshmi getcon "Get control register"
+ ()
+ "getcon $crk, $rd"
+ (+ (f-op 9) crk (f-ext 15) (f-right 63) rd (f-rsvd 0))
+ (set rd crk))
+
+(dshmi gettr "Get target register"
+ ()
+ "gettr $trb, $rd"
+ (+ (f-op 17) (f-25 0) trb (f-ext 5) (f-right 63) rd (f-rsvd 0))
+ (set rd trb))
+
+(dshmi icbi "Invalidate instruction cache block"
+ ()
+ "icbi $rm, $disp6x32"
+ (+ (f-op 56) rm (f-ext 5) disp6x32 (f-dest 63) (f-rsvd 0))
+ (unimp "icbi"))
+
+(dshmi ldb "Load byte"
+ ()
+ "ld.b $rm, $disp10, $rd"
+ (+ (f-op 32) rm disp10 rd (f-rsvd 0))
+ (set rd (ext DI (mem QI (add rm (ext DI disp10))))))
+
+(dshmi ldl "Load long word"
+ ()
+ "ld.l $rm, $disp10x4, $rd"
+ (+ (f-op 34) rm disp10x4 rd (f-rsvd 0))
+ (set rd (ext DI (mem SI (add rm (ext DI disp10x4))))))
+
+(dshmi ldq "Load quad word"
+ ()
+ "ld.q $rm, $disp10x8, $rd"
+ (+ (f-op 35) rm disp10x8 rd (f-rsvd 0))
+ (set rd (mem DI (add rm (ext DI disp10x8)))))
+
+(dshmi ldub "Load unsigned byte"
+ ()
+ "ld.ub $rm, $disp10, $rd"
+ (+ (f-op 36) rm disp10 rd (f-rsvd 0))
+ (set rd (zext DI (mem QI (add rm (ext DI disp10))))))
+
+(dshmi lduw "Load unsigned word"
+ ()
+ "ld.uw $rm, $disp10x2, $rd"
+ (+ (f-op 44) rm disp10 rd (f-rsvd 0))
+ (set rd (zext DI (mem HI (add rm (ext DI disp10x2))))))
+
+(dshmi ldw "Load word"
+ ()
+ "ld.w $rm, $disp10x2, $rd"
+ (+ (f-op 33) rm disp10 rd (f-rsvd 0))
+ (set rd (ext DI (mem HI (add rm (ext DI disp10x2))))))
+
+(dshmi ldhil "Load high part (long word)"
+ ()
+ "ldhi.l $rm, $disp6, $rd"
+ (+ (f-op 48) rm (f-ext 6) disp6 rd (f-rsvd 0))
+ ; FIXME.
+ (unimp "ldhil"))
+
+(dshmi ldhiq "Load high part (quad word)"
+ ()
+ "ldhi.q $rm, $disp6, $rd"
+ (+ (f-op 48) rm (f-ext 7) disp6 rd (f-rsvd 0))
+ ; FIXME.
+ (unimp "ldhiq"))
+
+(dshmi ldlol "Load low part (long word)"
+ ()
+ "ldlo.l $rm, $disp6, $rd"
+ (+ (f-op 48) rm (f-ext 2) disp6 rd (f-rsvd 0))
+ ; FIXME.
+ (unimp "ldlol"))
+
+(dshmi ldloq "Load low part (quad word)"
+ ()
+ "ldlo.q $rm, $disp6, $rd"
+ (+ (f-op 48) rm (f-ext 3) disp6 rd (f-rsvd 0))
+ ; FIXME;
+ (unimp "ldloq"))
+
+(dshmi ldxb "Load byte (extended displacement)"
+ ()
+ "ldx.b $rm, $rn, $rd"
+ (+ (f-op 16) rm (f-ext 0) rn rd (f-rsvd 0))
+ (set rd (ext DI (mem QI (add rm rn)))))
+
+(dshmi ldxl "Load long word (extended displacement)"
+ ()
+ "ldx.l $rm, $rn, $rd"
+ (+ (f-op 16) rm (f-ext 2) rn rd (f-rsvd 0))
+ (set rd (ext DI (mem SI (add rm rn)))))
+
+(dshmi ldxq "Load quad word (extended displacement)"
+ ()
+ "ldx.q $rm, $rn, $rd"
+ (+ (f-op 16) rm (f-ext 3) rn rd (f-rsvd 0))
+ (set rd (mem DI (add rm rn))))
+
+(dshmi ldxub "Load unsigned byte (extended displacement)"
+ ()
+ "ldx.ub $rm, $rn, $rd"
+ (+ (f-op 16) rm (f-ext 4) rn rd (f-rsvd 0))
+ (set rd (zext DI (mem UQI (add rm rn)))))
+
+(dshmi ldxuw "Load unsigned word (extended displacement)"
+ ()
+ "ldx.uw $rm, $rn, $rd"
+ (+ (f-op 16) rm (f-ext 5) rn rd (f-rsvd 0))
+ (set rd (zext DI (mem UHI (add rm rn)))))
+
+(dshmi ldxw "Load word (extended displacement)"
+ ()
+ "ldx.w $rm, $rn, $rd"
+ (+ (f-op 16) rm (f-ext 1) rn rd (f-rsvd 0))
+ (set rd (ext DI (mem HI (add rm rn)))))
+
+
+; Macros to facilitate multimedia instructions.
+
+(define-pmacro (slice-byte expr)
+ (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+ (QI result3) (QI result2) (QI result1) (QI result0))
+ (set result0 (expr (subword QI rm 7) (subword QI rn 7)))
+ (set result1 (expr (subword QI rm 6) (subword QI rn 6)))
+ (set result2 (expr (subword QI rm 5) (subword QI rn 5)))
+ (set result3 (expr (subword QI rm 4) (subword QI rn 4)))
+ (set result4 (expr (subword QI rm 3) (subword QI rn 3)))
+ (set result5 (expr (subword QI rm 2) (subword QI rn 2)))
+ (set result6 (expr (subword QI rm 1) (subword QI rn 1)))
+ (set result7 (expr (subword QI rm 0) (subword QI rn 0)))
+ (set rd (-join-qi result7 result6 result5 result4 result3 result2
+ result1 result0))))
+
+(define-pmacro (slice-word expr)
+ (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+ (set result0 (expr (subword HI rm 3) (subword HI rn 3)))
+ (set result1 (expr (subword HI rm 2) (subword HI rn 2)))
+ (set result2 (expr (subword HI rm 1) (subword HI rn 1)))
+ (set result3 (expr (subword HI rm 0) (subword HI rn 0)))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(define-pmacro (slice-word-unop expr)
+ (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+ (set result0 (expr (subword HI rm 3)))
+ (set result1 (expr (subword HI rm 2)))
+ (set result2 (expr (subword HI rm 1)))
+ (set result3 (expr (subword HI rm 0)))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(define-pmacro (slice-long expr)
+ (sequence ((SI result1) (SI result0))
+ (set result0 (expr (subword SI rm 1) (subword SI rn 1)))
+ (set result1 (expr (subword SI rm 0) (subword SI rn 0)))
+ (set rd (-join-si result1 result0))))
+
+(define-pmacro (slice-long-unop expr)
+ (sequence ((SI result1) (SI result0))
+ (set result0 (expr (subword SI rm 1)))
+ (set result1 (expr (subword SI rm 0)))
+ (set rd (-join-si result1 result0))))
+
+; Multimedia instructions.
+
+(dshmi mabsl "Multimedia absolute value (long word)"
+ ()
+ "mabs.l $rm, $rd"
+ (+ (f-op 10) rm (f-ext 10) (f-right 63) rd (f-rsvd 0))
+ (slice-long-unop abs))
+
+(dshmi mabsw "Multimedia absolute value (word)"
+ ()
+ "mabs.w $rm, $rd"
+ (+ (f-op 10) rm (f-ext 9) (f-right 63) rd (f-rsvd 0))
+ (slice-word-unop abs))
+
+(dshmi maddl "Multimedia add (long word)"
+ ()
+ "madd.l $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 2) rn rd (f-rsvd 0))
+ (slice-long add))
+
+(dshmi maddw "Multimedia add (word)"
+ ()
+ "madd.w $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 1) rn rd (f-rsvd 0))
+ (slice-word add))
+
+(define-pmacro (-maddsl arg1 arg2) (saturate SI 32 (add arg1 arg2)))
+(dshmi maddsl "Multimedia add (saturating, long word)"
+ ()
+ "madds.l $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 6) rn rd (f-rsvd 0))
+ (slice-long -maddsl))
+
+(define-pmacro (-maddsub arg1 arg2) (usaturate QI 8 (add arg1 arg2)))
+(dshmi maddsub "Multimedia add (saturating, unsigned byte)"
+ ()
+ "madds.ub $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 4) rn rd (f-rsvd 0))
+ (slice-byte -maddsub))
+
+(define-pmacro (-maddsw arg1 arg2) (saturate HI 16 (add arg1 arg2)))
+(dshmi maddsw "Multimedia add (saturating, word)"
+ ()
+ "madds.w $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 5) rn rd (f-rsvd 0))
+ (slice-word -maddsw))
+
+(define-pmacro (-mcmpeq mode arg1 arg2)
+ (if mode (eq arg1 arg2) (inv mode 0) (const mode 0)))
+
+(define-pmacro (-mcmpeqb arg1 arg2) (-mcmpeq QI arg1 arg2))
+(dshmi mcmpeqb "Multimedia compare equal (byte)"
+ ()
+ "mcmpeq.b $rm, $rn, $rd"
+ (+ (f-op 10) rm (f-ext 0) rn rd (f-rsvd 0))
+ (slice-byte -mcmpeqb))
+
+(define-pmacro (-mcmpeql arg1 arg2) (-mcmpeq SI arg1 arg2))
+(dshmi mcmpeql "Multimedia compare equal (long word)"
+ ()
+ "mcmpeq.l $rm, $rn, $rd"
+ (+ (f-op 10) rm (f-ext 2) rn rd (f-rsvd 0))
+ (slice-long -mcmpeql))
+
+(define-pmacro (-mcmpeqw arg1 arg2) (-mcmpeq HI arg1 arg2))
+(dshmi mcmpeqw "Multimedia compare equal (word)"
+ ()
+ "mcmpeq.w $rm, $rn, $rd"
+ (+ (f-op 10) rm (f-ext 1) rn rd (f-rsvd 0))
+ (slice-word -mcmpeqw))
+
+(define-pmacro (-mcmpgt mode arg1 arg2)
+ (if mode (gt arg1 arg2) (inv mode 0) (const mode 0)))
+(define-pmacro (-mcmpgtu mode arg1 arg2)
+ (if mode (gtu arg1 arg2) (inv mode 0) (const mode 0)))
+
+(define-pmacro (-mcmpgtl arg1 arg2) (-mcmpgt SI arg1 arg2))
+(dshmi mcmpgtl "Multimedia compare greater than (long word)"
+ ()
+ "mcmpgt.l $rm, $rn, $rd"
+ (+ (f-op 10) rm (f-ext 6) rn rd (f-rsvd 0))
+ (slice-long -mcmpgtl))
+
+(define-pmacro (-mcmpgtub arg1 arg2) (-mcmpgtu QI arg1 arg2))
+(dshmi mcmpgtub "Multimediate compare unsigned greater than (byte)"
+ ()
+ "mcmpgt.ub $rm, $rn, $rd"
+ (+ (f-op 10) rm (f-ext 4) rn rd (f-rsvd 0))
+ (slice-byte -mcmpgtub))
+
+(define-pmacro (-mcmpgtw arg1 arg2) (-mcmpgt HI arg1 arg2))
+(dshmi mcmpgtw "Multimedia compare greater than (word)"
+ ()
+ "mcmpgt.w $rm, $rn, $rd"
+ (+ (f-op 10) rm (f-ext 5) rn rd (f-rsvd 0))
+ (slice-word -mcmpgtw))
+
+(dshmi mcmv "Multimedia conditional move"
+ ()
+ "mcmv $rm, $rn, $rd"
+ (+ (f-op 18) rm (f-ext 3) rn rd (f-rsvd 0))
+ (set rd (or (and rm rn) (and rd (inv rn)))))
+
+(dshmi mcnvslw "Multimedia convert/saturate (long to word)"
+ ()
+ "mcnvs.lw $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 13) rn rd (f-rsvd 0))
+ (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+ (set result0 (saturate HI 16 (subword SI rm 0)))
+ (set result1 (saturate HI 16 (subword SI rm 1)))
+ (set result2 (saturate HI 16 (subword SI rn 0)))
+ (set result3 (saturate HI 16 (subword SI rn 1)))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mcnvswb "Multimedia convert/saturate (word to byte)"
+ ()
+ "mcnvs.wb $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 8) rn rd (f-rsvd 0))
+ (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+ (QI result3) (QI result2) (QI result1) (QI result0))
+ (set result0 (saturate QI 8 (subword HI rm 0)))
+ (set result1 (saturate QI 8 (subword HI rm 1)))
+ (set result2 (saturate QI 8 (subword HI rm 2)))
+ (set result3 (saturate QI 8 (subword HI rm 3)))
+ (set result4 (saturate QI 8 (subword HI rn 0)))
+ (set result5 (saturate QI 8 (subword HI rn 1)))
+ (set result6 (saturate QI 8 (subword HI rn 2)))
+ (set result7 (saturate QI 8 (subword HI rn 3)))
+ (set rd (-join-qi result7 result6 result5 result4
+ result3 result2 result1 result0))))
+
+(dshmi mcnvswub "Multimedia convert/saturate (word to unsigned byte)"
+ ()
+ "mcnvs.wub $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 12) rn rd (f-rsvd 0))
+ (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+ (QI result3) (QI result2) (QI result1) (QI result0))
+ (set result0 (usaturate QI 8 (subword HI rm 0)))
+ (set result1 (usaturate QI 8 (subword HI rm 1)))
+ (set result2 (usaturate QI 8 (subword HI rm 2)))
+ (set result3 (usaturate QI 8 (subword HI rm 3)))
+ (set result4 (usaturate QI 8 (subword HI rn 0)))
+ (set result5 (usaturate QI 8 (subword HI rn 1)))
+ (set result6 (usaturate QI 8 (subword HI rn 2)))
+ (set result7 (usaturate QI 8 (subword HI rn 3)))
+ (set rd (-join-qi result7 result6 result5 result4 result3
+ result2 result1 result0))))
+
+; mexter -- generate an mexterN instruction, where:
+; op = primary opcode
+; extop = extended opcode
+
+(define-pmacro (make-mextr n op extop)
+ (dshmi (.sym mextr n)
+ (.str "Multimedia extract 64-bit slice (from byte " n ")")
+ ()
+ (.str "mextr" n " $rm, $rn, $rd")
+ (+ (f-op op) rm (f-ext extop) rn rd (f-rsvd 0))
+ (sequence ((QI count) (DI mask) (DI rhs))
+ (set count (mul QI 8 (sub QI 8 n)))
+ (set mask (sll DI (inv 0) count))
+ (set rhs (srl (and rm mask) count))
+ (set count (mul QI 8 n))
+ (set mask (srl DI (inv 0) count))
+ (set rd (or DI rhs (sll DI (and rn mask) count))))))
+
+(make-mextr 1 10 7)
+(make-mextr 2 10 11)
+(make-mextr 3 10 15)
+(make-mextr 4 11 3)
+(make-mextr 5 11 7)
+(make-mextr 6 11 11)
+(make-mextr 7 11 15)
+
+(dshmi mmacfxwl "Multimedia fractional multiply (word to long)"
+ ()
+ "mmacfx.wl $rm, $rn, $rd"
+ (+ (f-op 18) rm (f-ext 1) rn rd (f-rsvd 0))
+ (sequence ((SI temp) (SI result1) (SI result0))
+ (set result0 (subword SI rd 0))
+ (set result1 (subword SI rd 1))
+ (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+ (set temp (saturate SI 32 (sll temp 1)))
+ (set result0 (saturate SI 32 (add result0 temp)))
+ (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+ (set temp (saturate SI 32 (sll temp 1)))
+ (set result1 (saturate SI 32 (add result1 temp)))
+ (set rd (-join-si result1 result0))))
+
+(dshmi mmacnfx.wl "Multimedia fractional multiple (word to long)"
+ ()
+ "mmacnfx.wl $rm, $rn, $rd"
+ (+ (f-op 18) rn (f-ext 5) rn rd (f-rsvd 0))
+ (sequence ((SI temp) (SI result1) (SI result0))
+ (set result0 (subword SI rd 0))
+ (set result1 (subword SI rd 1))
+ (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+ (set temp (saturate SI 32 (sll temp 1)))
+ (set result0 (saturate SI 32 (sub result0 temp)))
+ (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+ (set temp (saturate SI 32 (sll temp 1)))
+ (set result1 (saturate SI 32 (sub result1 temp)))
+ (set rd (-join-si result1 result0))))
+
+(dshmi mmull "Multimedia multiply (long word)"
+ ()
+ "mmul.l $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 2) rn rd (f-rsvd 0))
+ (slice-long mul))
+
+(dshmi mmulw "Multimedia multiply (word)"
+ ()
+ "mmul.w $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 1) rn rd (f-rsvd 0))
+ (slice-word mul))
+
+(dshmi mmulfxl "Multimedia fractional multiply (long word)"
+ ()
+ "mmulfx.l $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 6) rn rd (f-rsvd 0))
+ (sequence ((DI temp) (SI result0) (SI result1))
+ (set temp (mul (zext DI (subword SI rm 0)) (zext DI (subword SI rn 0))))
+ (set result0 (saturate SI 32 (sra temp 31)))
+ (set temp (mul (zext DI (subword SI rm 1)) (zext DI (subword SI rn 1))))
+ (set result1 (saturate SI 32 (sra temp 31)))
+ (set rd (-join-si result1 result0))))
+
+(dshmi mmulfxw "Multimedia fractional multiply (word)"
+ ()
+ "mmulfx.w $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 5) rn rd (f-rsvd 0))
+ (sequence ((SI temp) (HI result0) (HI result1) (HI result2) (HI result3))
+ (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+ (set result0 (saturate HI 16 (sra temp 15)))
+ (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+ (set result1 (saturate HI 16 (sra temp 15)))
+ (set temp (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2))))
+ (set result2 (saturate HI 16 (sra temp 15)))
+ (set temp (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3))))
+ (set result3 (saturate HI 16 (sra temp 15)))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mmulfxrpw "Multimedia fractional multiply round positive (word op)"
+ ()
+ "mmulfxrp.w $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 9) rn rd (f-rsvd 0))
+ (sequence ((SI temp) (HI result0) (HI result1) (HI result2) (HI result3) (HI c))
+ (set c (sll 1 14))
+ (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+ (set result0 (saturate HI 16 (sra (add temp c) 15)))
+ (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+ (set result1 (saturate HI 16 (sra (add temp c) 15)))
+ (set temp (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2))))
+ (set result2 (saturate HI 16 (sra (add temp c) 15)))
+ (set temp (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3))))
+ (set result3 (saturate HI 16 (sra (add temp c) 15)))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mmulhiwl "Multimedia multiply higher halves (word to long)"
+ ()
+ "mmulhi.wl $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 14) rn rd (f-rsvd 0))
+ (sequence ((SI result1) (SI result0))
+ (set result0 (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2))))
+ (set result1 (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3))))
+ (set rd (-join-si result1 result0))))
+
+(dshmi mmullowl "Multimedia multiply lower halves (word to long)"
+ ()
+ "mmullo.wl $rm, $rn, $rd"
+ (+ (f-op 19) rm (f-ext 10) rn rd (f-rsvd 0))
+ (sequence ((SI result1) (SI result0))
+ (set result0 (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+ (set result1 (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))
+ (set rd (-join-si result1 result0))))
+
+(dshmi mmulsumwq "Multimedia multiply and accumulate (word to quad)"
+ ()
+ "mmulsum.wq $rm, $rn, $rd"
+ (+ (f-op 18) rm (f-ext 9) rn rd (f-rsvd 0))
+ (sequence ((DI acc))
+ (set acc (mul SI (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0))))
+ (set acc (add acc (mul SI (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))))
+ (set acc (add acc (mul SI (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2)))))
+ (set acc (add acc (mul SI (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3)))))
+ (set rd (add rd acc))))
+
+(dshmi movi "Move immediate"
+ ()
+ "movi $imm16, $rd"
+ (+ (f-op 51) imm16 rd (f-rsvd 0))
+ (set rd (ext DI imm16)))
+
+(dshmi mpermw "Multimedia permutate word"
+ ()
+ "mperm.w $rm, $rn, $rd"
+ (+ (f-op 10) rm (f-ext 13) rn rd (f-rsvd 0))
+ (sequence ((QI control) (HI result3) (HI result2) (HI result1) (HI result0))
+ (set control (and QI rn #x3f))
+ (set result0 (subword HI rm (sub 3 (and control 3))))
+ (set result1 (subword HI rm (sub 3 (and (srl control 2) 3))))
+ (set result2 (subword HI rm (sub 3 (and (srl control 4) 3))))
+ (set result3 (subword HI rm (sub 3 (and (srl control 6) 3))))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi msadubq "Multimedia absolute difference (byte)"
+ ()
+ "msad.ubq $rm, $rn, $rd"
+ (+ (f-op 18) rm (f-ext 0) rn rd (f-rsvd 0))
+ (sequence ((DI acc))
+ (set acc (abs DI (sub (subword QI rm 0) (subword QI rn 1))))
+ (set acc (add DI acc (abs (sub (subword QI rm 1) (subword QI rn 1)))))
+ (set acc (add DI acc (abs (sub (subword QI rm 2) (subword QI rn 2)))))
+ (set acc (add DI acc (abs (sub (subword QI rm 3) (subword QI rn 3)))))
+ (set acc (add DI acc (abs (sub (subword QI rm 4) (subword QI rn 4)))))
+ (set acc (add DI acc (abs (sub (subword QI rm 5) (subword QI rn 5)))))
+ (set acc (add DI acc (abs (sub (subword QI rm 6) (subword QI rn 6)))))
+ (set acc (add DI acc (abs (sub (subword QI rm 7) (subword QI rn 7)))))
+ (set rd (add rd acc))))
+
+(define-pmacro (-mshaldsl arg) (saturate SI 32 (sll arg (and rn 31))))
+(dshmi mshaldsl "Multimedia saturating arithmetic left shift (long word)"
+ ()
+ "mshalds.l $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 6) rn rd (f-rsvd 0))
+ (slice-long-unop -mshaldsl))
+
+(define-pmacro (-mshaldsw arg) (saturate HI 16 (sll arg (and rn 15))))
+(dshmi mshaldsw "Multimedia saturating arithmetic left shift (word)"
+ ()
+ "mshalds.w $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 5) rn rd (f-rsvd 0))
+ (slice-word-unop -mshaldsw))
+
+(define-pmacro (-mshardl arg) (sra arg (and rn 31)))
+(dshmi mshardl "Multimedia arithmetic right shift (long)"
+ ()
+ "mshard.l $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 10) rn rd (f-rsvd 0))
+ (slice-long-unop -mshardl))
+
+(define-pmacro (-mshardw arg) (sra arg (and rn 15)))
+(dshmi mshardw "Multimedia arithmetic right shift (word)"
+ ()
+ "mshard.w $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 9) rn rd (f-rsvd 0))
+ (slice-word-unop -mshardw))
+
+(dshmi mshardsq "Multimedia saturating arithmetic right shift (quad word)"
+ ()
+ "mshards.q $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 11) rn rd (f-rsvd 0))
+ (set rd (saturate DI 16 (sra rm (and rn 63)))))
+
+(dshmi mshfhib "Multimedia shuffle higher-half (byte)"
+ ()
+ "mshfhi.b $rm, $rn, $rd"
+ (+ (f-op 11) rm (f-ext 4) rn rd (f-rsvd 0))
+ (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+ (QI result3) (QI result2) (QI result1) (QI result0))
+ (set result0 (subword QI rm 4))
+ (set result1 (subword QI rn 4))
+ (set result2 (subword QI rm 5))
+ (set result3 (subword QI rn 5))
+ (set result4 (subword QI rm 6))
+ (set result5 (subword QI rn 6))
+ (set result6 (subword QI rm 7))
+ (set result7 (subword QI rn 7))
+ (set rd (-join-qi result7 result6 result5 result4 result3
+ result2 result1 result0))))
+
+(dshmi mshfhil "Multimedia shuffle higher-half (long)"
+ ()
+ "mshfhi.l $rm, $rn, $rd"
+ (+ (f-op 11) rm (f-ext 6) rn rd (f-rsvd 0))
+ (sequence ((SI result1) (SI result0))
+ (set result0 (subword SI rm 1))
+ (set result1 (subword SI rn 1))
+ (set rd (-join-si result1 result0))))
+
+(dshmi mshfhiw "Multimedia shuffle higher-half (word)"
+ ()
+ "mshfhi.w $rm, $rn, $rd"
+ (+ (f-op 11) rm (f-ext 5) rn rd (f-rsvd 0))
+ (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+ (set result0 (subword HI rm 2))
+ (set result1 (subword HI rn 2))
+ (set result2 (subword HI rm 3))
+ (set result3 (subword HI rn 3))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(dshmi mshflob "Multimedia shuffle lower-half (byte)"
+ ()
+ "mshflo.b $rm, $rn, $rd"
+ (+ (f-op 11) rm (f-ext 0) rn rd (f-rsvd 0))
+ (sequence ((QI result7) (QI result6) (QI result5) (QI result4)
+ (QI result3) (QI result2) (QI result1) (QI result0))
+ (set result0 (subword QI rm 0))
+ (set result1 (subword QI rn 0))
+ (set result2 (subword QI rm 1))
+ (set result3 (subword QI rn 1))
+ (set result4 (subword QI rm 2))
+ (set result5 (subword QI rn 2))
+ (set result6 (subword QI rm 3))
+ (set result7 (subword QI rn 3))
+ (set rd (-join-qi result7 result6 result5 result4 result3
+ result2 result1 result0))))
+
+(dshmi mshflol "Multimedia shuffle lower-half (long)"
+ ()
+ "mshflo.l $rm, $rn, $rd"
+ (+ (f-op 11) rm (f-ext 2) rn rd (f-rsvd 0))
+ (sequence ((SI result1) (SI result0))
+ (set result0 (subword SI rm 0))
+ (set result1 (subword SI rn 0))
+ (set rd (-join-si result1 result0))))
+
+(dshmi mshflow "Multimedia shuffle lower-half (word)"
+ ()
+ "mshflo.w $rm, $rn, $rd"
+ (+ (f-op 11) rm (f-ext 1) rn rd (f-rsvd 0))
+ (sequence ((HI result3) (HI result2) (HI result1) (HI result0))
+ (set result0 (subword HI rm 0))
+ (set result1 (subword HI rn 0))
+ (set result2 (subword HI rm 1))
+ (set result3 (subword HI rn 1))
+ (set rd (-join-hi result3 result2 result1 result0))))
+
+(define-pmacro (-mshlldl arg) (sll arg (and rn 31)))
+(dshmi mshlldl "Multimedia logical left shift (long word)"
+ ()
+ "mshlld.l $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 2) rn rd (f-rsvd 0))
+ (slice-long-unop -mshlldl))
+
+(define-pmacro (-mshlldw arg) (sll arg (and rn 15)))
+(dshmi mshlldw "Multimedia logical left shift (word)"
+ ()
+ "mshlld.w $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 1) rn rd (f-rsvd 0))
+ (slice-word-unop -mshlldw))
+
+(define-pmacro (-mshlrdl arg) (srl arg (and rn 31)))
+(dshmi mshlrdl "Multimedia logical right shift (long word)"
+ ()
+ "mshlrd.l $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 14) rn rd (f-rsvd 0))
+ (slice-long-unop -mshlrdl))
+
+(define-pmacro (-mshlrdw arg) (srl arg (and rn 15)))
+(dshmi mshlrdw "Multimedia logical right shift (word)"
+ ()
+ "mshlrd.w $rm, $rn, $rd"
+ (+ (f-op 3) rm (f-ext 13) rn rd (f-rsvd 0))
+ (slice-word-unop -mshlrdw))
+
+(dshmi msubl "Multimedia subtract (long word)"
+ ()
+ "msub.l $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 10) rn rd (f-rsvd 0))
+ (slice-long sub))
+
+(dshmi msubw "Multimedia add (word)"
+ ()
+ "msub.w $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 9) rn rd (f-rsvd 0))
+ (slice-word sub))
+
+(define-pmacro (-msubsl arg1 arg2) (saturate SI 32 (sub arg1 arg2)))
+(dshmi msubsl "Multimedia subtract (saturating long)"
+ ()
+ "msubs.l $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 14) rn rd (f-rsvd 0))
+ (slice-long -msubsl))
+
+(define-pmacro (-msubsub arg1 arg2) (usaturate QI 8 (sub arg1 arg2)))
+(dshmi msubsub "Multimedia subtract (saturating byte)"
+ ()
+ "msubs.ub $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 12) rn rd (f-rsvd 0))
+ (slice-byte -msubsub))
+
+(define-pmacro (-msubsw arg1 arg2) (saturate HI 16 (sub arg1 arg2)))
+(dshmi msubsw "Multimedia subtract (saturating word)"
+ ()
+ "msubs.w $rm, $rn, $rd"
+ (+ (f-op 2) rm (f-ext 13) rn rd (f-rsvd 0))
+ (slice-byte -msubsw))
+
+(dshmi mulsl "Multiply signed long"
+ ()
+ "muls.l $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 14) rn rd (f-rsvd 0))
+ (set rd (mul (ext DI (subword SI rm 1)) (ext DI (subword SI rn 1)))))
+
+(dshmi mulul "Multiply unsigned long"
+ ()
+ "mulu.l $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 14) rn rd (f-rsvd 0))
+ (set rd (mul (zext DI (subword SI rm 1)) (zext DI (subword SI rn 1)))))
+
+(dshmi nop "No operation"
+ ()
+ "nop"
+ (+ (f-op 27) (f-left 63) (f-ext 0) (f-right 63) (f-dest 63) (f-rsvd 0))
+ (nop))
+
+(dshmi nsb "Number of consecutive sign bits"
+ ()
+ "nsb $rm, $rd"
+ (+ (f-op 0) rm (f-ext 13) (f-right 63) rd (f-rsvd 0))
+ ; Semantics requires a loop construct, so punt to C.
+ (set rd (c-call DI "sh64_nsb" rm)))
+
+(dshmi ocbi "Invalidate operand cache block"
+ ()
+ "ocbi $rm, $disp6x32"
+ (+ (f-op 56) rm (f-ext 9) disp6x32 (f-dest 63) (f-rsvd 0))
+ (unimp "ocbi"))
+
+(dshmi ocbp "Purge operand cache block"
+ ()
+ "ocbp $rm, $disp6x32"
+ (+ (f-op 56) rm (f-ext 8) disp6x32 (f-dest 63) (f-rsvd 0))
+ (unimp "ocbp"))
+
+(dshmi ocbwb "Write-back operand cache block"
+ ()
+ "ocbwb $rm, $disp6x32"
+ (+ (f-op 56) rm (f-ext 12) disp6x32 (f-dest 63) (f-rsvd 0))
+ (unimp "ocbwb"))
+
+(dshmi or "OR"
+ ()
+ "or $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 9) rn rd (f-rsvd 0))
+ (set rd (or rm rn)))
+
+(dshmi ori "OR immediate"
+ ()
+ "ori $rm, $imm10, $rd"
+ (+ (f-op 55) rm imm10 rd (f-rsvd 0))
+ (set rd (or rm (ext DI imm10))))
+
+(dshmi prefi "Prefetch instruction"
+ ()
+ "prefi $rm, $disp6x32"
+ (+ (f-op 56) rm (f-ext 1) disp6x32 (f-right 63) (f-rsvd 0))
+ (unimp "prefi"))
+
+(dshmi pta "Prepare target register for SHmedia target"
+ ()
+ "pta$likely $disp16, $tra"
+ (+ (f-op 58) disp16 likely (f-8-2 0) tra (f-rsvd 0))
+ (set tra (add disp16 1)))
+
+(dshmi ptabs "Prepare target register with absolute value from register"
+ ()
+ "ptabs$likely $rn, $tra"
+ (+ (f-op 26) (f-left 63) (f-ext 1) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (set tra rn))
+
+(dshmi ptb "Prepare target register for SHcompact target"
+ ()
+ "ptb$likely $disp16, $tra"
+ (+ (f-op 59) disp16 likely (f-8-2 0) tra (f-rsvd 0))
+ (set tra disp16))
+
+(dshmi ptrel "Prepare target register with relative value from register"
+ ()
+ "ptrel$likely $rn, $tra"
+ (+ (f-op 26) (f-left 63) (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0))
+ (set tra (add pc rn)))
+
+(dshmi putcfg "Put configuration register"
+ ()
+ "putcfg $rm, $disp6, $rd"
+ (+ (f-op 56) rm (f-ext 15) disp6 rd (f-rsvd 0))
+ (unimp "putcfg"))
+
+(dshmi putcon "Put control register"
+ ()
+ "putcon $rm, $crj"
+ (+ (f-op 27) rm (f-ext 15) (f-right 63) crj (f-rsvd 0))
+ (set crj rm))
+
+(dshmi rte "Return from exception"
+ ()
+ "rte"
+ (+ (f-op 27) (f-left 63) (f-ext 3) (f-right 63) (f-dest 63) (f-rsvd 0))
+ (unimp "rte"))
+
+(dshmi shard "Arithmetic right shift"
+ ()
+ "shard $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 7) rn rd (f-rsvd 0))
+ (set rd (sra rm (and rn 63))))
+
+(dshmi shardl "Arithmetic right shift (long word)"
+ ()
+ "shard.l $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 6) rn rd (f-rsvd 0))
+ (set rd (ext DI (sra (subword SI rm 1) (and rn 63)))))
+
+(dshmi shari "Arithmetic right shift (immediate count)"
+ ()
+ "shari $rm, $uimm6, $rd"
+ (+ (f-op 49) rm (f-ext 7) uimm6 rd (f-rsvd 0))
+ (set rd (sra rm uimm6)))
+
+(dshmi sharil "Arithmetic right shift (long word, immediate count)"
+ ()
+ "shari.l $rm, $uimm6, $rd"
+ (+ (f-op 49) rm (f-ext 6) uimm6 rd (f-rsvd 0))
+ (set rd (ext DI (sra (subword SI rm 1) (and uimm6 63)))))
+
+(dshmi shlld "Logical left shift"
+ ()
+ "shlld $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 1) rn rd (f-rsvd 0))
+ (set rd (sll rm (and rn 63))))
+
+(dshmi shlldl "Logical left shift (long word)"
+ ()
+ "shlld.l $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 0) rn rd (f-rsvd 0))
+ (set rd (ext DI (sll (subword SI rm 1) (and rn 63)))))
+
+(dshmi shlli "Logical left shift (immediate count)"
+ ()
+ "shlli $rm, $uimm6, $rd"
+ (+ (f-op 49) rm (f-ext 1) uimm6 rd (f-rsvd 0))
+ (set rd (sll rm uimm6)))
+
+(dshmi shllil "Logical left shift (long word, immediate count)"
+ ()
+ "shlli.l $rm, $uimm6, $rd"
+ (+ (f-op 49) rm (f-ext 0) uimm6 rd (f-rsvd 0))
+ (set rd (ext DI (sll (subword SI rm 1) (and uimm6 63)))))
+
+(dshmi shlrd "Logical right shift"
+ ()
+ "shlrd $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 3) rn rd (f-rsvd 0))
+ (set rd (srl rm (and rn 63))))
+
+(dshmi shlrdl "Logical right shift (long word)"
+ ()
+ "shlrd.l $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 2) rn rd (f-rsvd 0))
+ (set rd (ext DI (srl (subword SI rm 1) (and rn 63)))))
+
+(dshmi shlri "Logical right shift (immediate count)"
+ ()
+ "shlri $rm, $uimm6, $rd"
+ (+ (f-op 49) rm (f-ext 3) uimm6 rd (f-rsvd 0))
+ (set rd (srl rm uimm6)))
+
+(dshmi shlril "Logical right shift (long word, immediate count)"
+ ()
+ "shlri.l $rm, $uimm6, $rd"
+ (+ (f-op 49) rm (f-ext 2) uimm6 rd (f-rsvd 0))
+ (set rd (ext DI (srl (subword SI rm 1) (and uimm6 63)))))
+
+(dshmi shori "Shift-or immediate"
+ ()
+ "shori $uimm16, $rd"
+ (+ (f-op 50) uimm16 rd (f-rsvd 0))
+ (set rd (or (sll rd 16) (zext DI uimm16))))
+
+(dshmi sleep "Sleep"
+ ()
+ "sleep"
+ (+ (f-op 27) (f-left 63) (f-ext 7) (f-right 63) (f-dest 63) (f-rsvd 0))
+ (unimp "sleep"))
+
+(dshmi stb "Store byte"
+ ()
+ "st.b $rm, $disp10, $rd"
+ (+ (f-op 40) rm disp10 rd (f-rsvd 0))
+ (set (mem UQI (add rm (ext DI disp10))) (and QI rd #xff)))
+
+(dshmi stl "Store long word"
+ ()
+ "st.l $rm, $disp10x4, $rd"
+ (+ (f-op 42) rm disp10x4 rd (f-rsvd 0))
+ (set (mem SI (add rm (ext DI disp10x4))) (and SI rd #xffffffff)))
+
+(dshmi stq "Store quad word"
+ ()
+ "st.q $rm, $disp10x8, $rd"
+ (+ (f-op 43) rm disp10x8 rd (f-rsvd 0))
+ (set (mem DI (add rm (ext DI disp10x8))) rd))
+
+(dshmi stw "Store word"
+ ()
+ "st.w $rm, $disp10x2, $rd"
+ (+ (f-op 41) rm disp10x2 rd (f-rsvd 0))
+ (set (mem HI (add rm (ext DI disp10x2))) (and HI rd #xffff)))
+
+(define-pmacro (-sthi-byte)
+ (sequence ()
+ (set (mem UQI addr) (and QI val #xff))
+ (set val (srl val 8))
+ (set addr (add addr 1))))
+
+(dshmi sthil "Store high part (long word)"
+ ()
+ "sthi.l $rm, $disp6, $rd"
+ (+ (f-op 56) rm (f-ext 6) disp6 rd (f-rsvd 0))
+ (sequence ((DI addr) (QI bytecount) (DI val))
+ (set addr (add rm disp6))
+ (set bytecount (add (and addr 3) 1))
+ (if endian
+ (set val rd)
+ (set val (srl rd (sub 32 (mul 8 bytecount)))))
+ (set addr (add (sub addr bytecount) 1))
+ (if (gt bytecount 3)
+ (-sthi-byte))
+ (if (gt bytecount 2)
+ (-sthi-byte))
+ (if (gt bytecount 1)
+ (-sthi-byte))
+ (if (gt bytecount 0)
+ (-sthi-byte))))
+
+(dshmi sthiq "Store high part (quad word)"
+ ()
+ "sthi.q $rm, $disp6, $rd"
+ (+ (f-op 56) rm (f-ext 7) disp6 rd (f-rsvd 0))
+ (sequence ((DI addr) (QI bytecount) (DI val))
+ (set addr (add rm disp6))
+ (set bytecount (add (and addr 7) 1))
+ (if endian
+ (set val rd)
+ (set val (srl rd (sub 64 (mul 8 bytecount)))))
+ (set addr (add (sub addr bytecount) 1))
+ (if (gt bytecount 7)
+ (-sthi-byte))
+ (if (gt bytecount 6)
+ (-sthi-byte))
+ (if (gt bytecount 5)
+ (-sthi-byte))
+ (if (gt bytecount 4)
+ (-sthi-byte))
+ (if (gt bytecount 3)
+ (-sthi-byte))
+ (if (gt bytecount 2)
+ (-sthi-byte))
+ (if (gt bytecount 1)
+ (-sthi-byte))
+ (if (gt bytecount 0)
+ (-sthi-byte))))
+
+(dshmi stlol "Store low part (long word)"
+ ()
+ "stlo.l $rm, $disp6, $rd"
+ (+ (f-op 56) rm (f-ext 2) disp6 rd (f-rsvd 0))
+ ; FIXME.
+ (unimp "stlol"))
+
+(dshmi stloq "Store low part (quad word)"
+ ()
+ "stlo.q $rm, $disp6, $rd"
+ (+ (f-op 56) rm (f-ext 3) disp6 rd (f-rsvd 0))
+ ; FIXME.
+ (unimp "stloq"))
+
+(dshmi stxb "Store byte (extended displacement)"
+ ()
+ "stx.b $rm, $rn, $rd"
+ (+ (f-op 24) rm (f-ext 0) rn rd (f-rsvd 0))
+ (set (mem UQI (add rm rn)) (subword QI rd 7)))
+
+(dshmi stxl "Store long (extended displacement)"
+ ()
+ "stx.l $rm, $rn, $rd"
+ (+ (f-op 24) rm (f-ext 2) rn rd (f-rsvd 0))
+ (set (mem SI (add rm rn)) (subword SI rd 1)))
+
+(dshmi stxq "Store quad word (extended displacement)"
+ ()
+ "stx.q $rm, $rn, $rd"
+ (+ (f-op 24) rm (f-ext 3) rn rd (f-rsvd 0))
+ (set (mem DI (add rm rn)) rd))
+
+(dshmi stxw "Store word (extended displacement)"
+ ()
+ "stx.w $rm, $rn, $rd"
+ (+ (f-op 24) rm (f-ext 1) rn rd (f-rsvd 0))
+ (set (mem HI (add rm rn)) (subword HI rd 3)))
+
+(dshmi sub "Subtract"
+ ()
+ "sub $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 11) rn rd (f-rsvd 0))
+ (set rd (sub rm rn)))
+
+(dshmi subl "Subtract long"
+ ()
+ "sub.l $rm, $rn, $rd"
+ (+ (f-op 0) rm (f-ext 10) rn rd (f-rsvd 0))
+ (set rd (ext DI (sub (subword SI rm 1) (subword SI rn 1)))))
+
+(dshmi swapq "Swap quad words"
+ ()
+ "swap.q $rm, $rn, $rd"
+ (+ (f-op 8) rm (f-ext 3) rn rd (f-rsvd 0))
+ (sequence ((DI addr) (DI temp))
+ (set addr (add rm rn))
+ (set temp (mem DI addr))
+ (set (mem DI addr) rd)
+ (set rd temp)))
+
+(dshmi synci "Synchronise instruction fetch"
+ ()
+ "synci"
+ (+ (f-op 27) (f-left 63) (f-ext 2) (f-right 63) (f-dest 63) (f-rsvd 0))
+ (unimp "synci"))
+
+(dshmi synco "Synchronise data operations"
+ ()
+ "synco"
+ (+ (f-op 27) (f-left 63) (f-ext 6) (f-right 63) (f-dest 63) (f-rsvd 0))
+ (unimp "synco"))
+
+(dshmi trapa "Trap"
+ ()
+ "trapa $rm"
+ (+ (f-op 27) rm (f-ext 1) (f-right 63) (f-dest 63) (f-rsvd 0))
+ (c-call "sh64_trapa" rm pc))
+
+(dshmi xor "Exclusive OR"
+ ()
+ "xor $rm, $rn, $rd"
+ (+ (f-op 1) rm (f-ext 13) rn rd (f-rsvd 0))
+ (set rd (xor rm rn)))
+
+(dshmi xori "Exclusive OR immediate"
+ ()
+ "xori $rm, $imm6, $rd"
+ (+ (f-op 49) rm (f-ext 13) rn rd (f-rsvd 0))
+ (set rd (xor rm (ext DI imm6))))