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PATCH : Update description about Floating point behavior of SH family
- From: "Nutan" <Nutan at KPITCummins dot com>
- To: <binutils at sources dot redhat dot com>
- Date: Wed, 24 Dec 2003 14:51:01 +0530
- Subject: PATCH : Update description about Floating point behavior of SH family
Hi,
Section "8.2.3 Floating Point" in as manual says:
The SH family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.
This statement is not correct. SH2E, SH3E and SH4 have hardware support for floating point.
Patch given below modifies the text.
----------------------------------------------------------------
gas/ChangeLog
2003-12-24 Nutan Singh <nutan@kpitcummins.com>
* gas/doc/c-sh.texi: Description about Floating point behavior of SH family.
Patch for /gas/doc/c-sh.texi
--- gas/doc/c-sh.texi Wed Dec 24 19:27:42 2003
+++ gas/doc/c-sh-new.texi Wed Dec 24 19:28:04 2003
@@ -164,9 +164,23 @@ Immediate data
@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
-The SH family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
+SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
+SH groups can use @code{.float} directive to generate @sc{ieee}
+floating-point numbers.
+
+SH2E and SH3E support single-precision floating point calculations as
+well as entirely PCAPI compatible emulation of double-precision
+floating point calculations. SH2E and SH3E instructions are a subset of
+the floating point calculations conforming to the IEEE754 standard.
+
+In addition to single-precision and double-precision floating-point
+operation capability, the on-chip FPU of SH4 has a 128-bit graphic
+engine that enables 32-bit floating-point data to be processed 128
+bits at a time. It also supports 4 * 4 array operations and inner
+product operations. Also, a superscalar architecture is employed that
+enables simultaneous execution of two instructions (including FPU
+instructions), providing performance of up to twice that of
+conventional architectures at the same frequency.
@node SH Directives
@section SH Machine Directives