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Allow signed overflow in cgen relocs

From: Nick Clifton <nickc at redhat dot com>
To: binutils at sources dot redhat dot com
Date: 08 Apr 2003 13:43:43 +0100
Subject: Allow signed overflow in cgen relocs
Hi Guys,

  I am applying the patch below to make the -J switch for GAS work
  with cgen based toolchains.  The switch allows signed overflow of
  constants inside relocs to be ignored, but the cgen function to
  enable this was not being triggered.

  Rather than just call the function directly however, the code adds a
  new function to gas/cgen.c called 'gas_cgen_begin()'.  This function
  is responsible for performing any cgen specific initialisation once
  the command line has been parsed and gas_cgen_cpu_desc has been
  created.

  The patch also includes a new test for the M32R gas testsuite, which
  checks that the fix works, and which was the motivation for this
  change.

Cheers
        Nick

gas/ChangeLog
2003-04-08  Nick Clifton  <nickc at redhat dot com>

	* as.c (perform_an_assembly_pass): If using cgen, call
	gas_cgen_begin.
	* cgen.c (gas_cgen_begin): New function.  If
	flag_signed_overflow_ok is set call cgen_set_signed_overflow_ok
	otherwise call cgen_clear_signed_overflow_ok.
	* cgen.h: Prototype gas_cgen_begin.

gas/testsuite/ChangeLog
2003-04-08  Nick Clifton  <nickc at redhat dot com>

	* gas/m32r/m32r.exp: Run signed-relocs test.
        * gas/m32r/signed-relocs.s: New file: Test signed relocs.
        * gas/m32r/signed-relocs.d: New file: Expected results

Index: as.c
===================================================================
RCS file: /cvs/src/src/gas/as.c,v
retrieving revision 1.41
diff -c -3 -p -w -r1.41 as.c
*** as.c	17 Dec 2002 12:02:41 -0000	1.41
--- as.c	8 Apr 2003 12:38:59 -0000
*************** static void parse_args PARAMS ((int *, c
*** 65,70 ****
--- 65,74 ----
  static void dump_statistics PARAMS ((void));
  static void perform_an_assembly_pass PARAMS ((int argc, char **argv));
  static int macro_expr PARAMS ((const char *, int, sb *, int *));
+ #ifdef USING_CGEN
+ /* Perform any cgen specific initialisation for gas.  */
+ extern void gas_cgen_begin PARAMS ((void));
+ #endif
  
  /* True if a listing is wanted.  */
  int listing;
*************** perform_an_assembly_pass (argc, argv)
*** 1064,1069 ****
--- 1068,1076 ----
       and sections already created, in BFD_ASSEMBLER mode.  */
    md_begin ();
  
+ #ifdef USING_CGEN
+   gas_cgen_begin ();
+ #endif
  #ifdef obj_begin
    obj_begin ();
  #endif

Index: cgen.c
===================================================================
RCS file: /cvs/src/src/gas/cgen.c,v
retrieving revision 1.20
diff -c -3 -p -w -r1.20 cgen.c
*** cgen.c	20 Feb 2003 18:59:31 -0000	1.20
--- cgen.c	8 Apr 2003 12:39:00 -0000
*************** gas_cgen_tc_gen_reloc (section, fixP)
*** 716,718 ****
--- 716,730 ----
    reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
    return reloc;
  }
+ 
+ /* Perform any cgen specific initialisation.
+    Called after gas_cgen_cpu_desc has been created.  */
+ 
+ void
+ gas_cgen_begin ()
+ {
+   if (flag_signed_overflow_ok)
+     cgen_set_signed_overflow_ok (gas_cgen_cpu_desc);
+   else
+     cgen_clear_signed_overflow_ok (gas_cgen_cpu_desc);
+ }

Index: cgen.h
===================================================================
RCS file: /cvs/src/src/gas/cgen.h,v
retrieving revision 1.11
diff -c -3 -p -w -r1.11 cgen.h
*** cgen.h	3 May 2002 02:25:33 -0000	1.11
--- cgen.h	8 Apr 2003 12:39:00 -0000
*************** md_cgen_record_fixup_exp PARAMS ((fragS 
*** 98,101 ****
--- 98,104 ----
  
  extern void gas_cgen_md_operand PARAMS ((expressionS *));
  
+ /* Perform any cgen specific initialisation for gas.  */
+ extern void gas_cgen_begin PARAMS ((void));
+ 
  #endif /* GAS_CGEN_H */

Index: testsuite/gas/m32r/m32r.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/m32r/m32r.exp,v
retrieving revision 1.1.1.1
diff -c -3 -p -w -r1.1.1.1 m32r.exp
*** testsuite/gas/m32r/m32r.exp	3 May 1999 07:28:51 -0000	1.1.1.1
--- testsuite/gas/m32r/m32r.exp	8 Apr 2003 12:39:01 -0000
*************** if [istarget m32r*-*-*] {
*** 5,8 ****
--- 5,9 ----
      run_dump_test "relax-1"
      run_dump_test "uppercase"
      run_dump_test "fslot"
+     run_dump_test "signed-relocs"
  }

*** /dev/null	Sat Aug 31 00:31:37 2002
--- testsuite/gas/m32r/signed-relocs.s	Tue Apr  8 13:25:21 2003
***************
*** 0 ****
--- 1,80 ----
+ ; check:	 not case sensitive for special operand modifier
+ ; check:	 shigh, high, low
+ 	.text
+ relocs:
+ 	seth	r0, #shigh(0x87654321)
+ 	add3	r0, r0, #low(0x87654321)
+ 	seth	r0, #SHIGH(0x87654321)
+ 	add3	r0, r0, #LOW(0x87654321)
+ 	seth	r0, #shigh(0x1234ffff)
+ 	add3	r0, r0, #low(0x1234ffff)
+ 	seth	r0, #SHIGH(0x1234ffff)
+ 	add3	r0, r0, #LOW(0x1234ffff)
+ 
+ 	seth	r0, #high(0x87654321)
+ 	or3	r0, r0, #low(0x87654321)
+ 	seth	r0, #HIGH(0x87654321)
+ 	or3	r0, r0, #LOW(0x87654321)
+ 	seth	r0, #high(0x1234ffff)
+ 	or3	r0, r0, #low(0x1234ffff)
+ 	seth	r0, #HIGH(0x1234ffff)
+ 	or3	r0, r0, #LOW(0x1234ffff)
+ 
+ 	seth	r0, #shigh(0x87654320)
+ 	ld	r0, @(#low(0x87654320),r0)
+ 	seth	r0, #shigh(0x87654320)
+ 	ldh	r0, @(#low(0x87654320),r0)
+ 	seth	r0, #shigh(0x87654320)
+ 	lduh	r0, @(#low(0x87654320),r0)
+ 	seth	r0, #shigh(0x87654320)
+ 	ldb	r0, @(#low(0x87654320),r0)
+ 	seth	r0, #shigh(0x87654320)
+ 	ldub	r0, @(#low(0x87654320),r0)
+ 
+ 	seth	r0, #shigh(0x1234fff0)
+ 	ld	r0, @(#low(0x1234fff0),r0)
+ 	seth	r0, #shigh(0x1234fff0)
+ 	ldh	r0, @(#low(0x1234fff0),r0)
+ 	seth	r0, #shigh(0x1234fff0)
+ 	lduh	r0, @(#low(0x1234fff0),r0)
+ 	seth	r0, #shigh(0x1234fff0)
+ 	ldb	r0, @(#low(0x1234fff0),r0)
+ 	seth	r0, #shigh(0x1234fff0)
+ 	ldub	r0, @(#low(0x1234fff0),r0)
+ 
+ 	seth	r0, #SHIGH(0x87654320)
+ 	ld	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x87654320)
+ 	ldh	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x87654320)
+ 	lduh	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x87654320)
+ 	ldb	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x87654320)
+ 	ldub	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x1234fff0)
+ 	ld	r0, @(#LOW(0x1234fff0),r0)
+ 
+ 	seth	r0, #shigh(0x87654320)
+ 	st	r0, @(#low(0x87654320),r0)
+ 	seth	r0, #shigh(0x87654320)
+ 	sth	r0, @(#low(0x87654320),r0)
+ 	seth	r0, #shigh(0x87654320)
+ 	stb	r0, @(#low(0x87654320),r0)
+ 
+ 	seth	r0, #shigh(0x1234fff0)
+ 	st	r0, @(#low(0x1234fff0),r0)
+ 	seth	r0, #shigh(0x1234fff0)
+ 	sth	r0, @(#low(0x1234fff0),r0)
+ 	seth	r0, #shigh(0x1234fff0)
+ 	stb	r0, @(#low(0x1234fff0),r0)
+ 
+ 	seth	r0, #SHIGH(0x87654320)
+ 	st	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x87654320)
+ 	sth	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x87654320)
+ 	stb	r0, @(#LOW(0x87654320),r0)
+ 	seth	r0, #SHIGH(0x1234fff0)
+ 	st	r0, @(#LOW(0x1234fff0),r0)
+ 

*** /dev/null	Sat Aug 31 00:31:37 2002
--- testsuite/gas/m32r/signed-relocs.d	Tue Apr  8 13:31:47 2003
***************
*** 0 ****
--- 1,77 ----
+ #as: -J
+ #objdump: -dr
+ #name: Signed relocs
+ 
+ .*: +file format .*
+ 
+ Disassembly of section .text:
+ 
+ 0+0000 <relocs>:
+    0:	d0 c0 87 65 	seth r0,#0x8765
+    4:	80 a0 43 21 	add3 r0,r0,#17185
+    8:	d0 c0 87 65 	seth r0,#0x8765
+    c:	80 a0 43 21 	add3 r0,r0,#17185
+   10:	d0 c0 12 35 	seth r0,#0x1235
+   14:	80 a0 ff ff 	add3 r0,r0,#-1
+   18:	d0 c0 12 35 	seth r0,#0x1235
+   1c:	80 a0 ff ff 	add3 r0,r0,#-1
+   20:	d0 c0 87 65 	seth r0,#0x8765
+   24:	80 e0 43 21 	or3 r0,r0,#0x4321
+   28:	d0 c0 87 65 	seth r0,#0x8765
+   2c:	80 e0 43 21 	or3 r0,r0,#0x4321
+   30:	d0 c0 12 34 	seth r0,#0x1234
+   34:	80 e0 ff ff 	or3 r0,r0,#0xffff
+   38:	d0 c0 12 34 	seth r0,#0x1234
+   3c:	80 e0 ff ff 	or3 r0,r0,#0xffff
+   40:	d0 c0 87 65 	seth r0,#0x8765
+   44:	a0 c0 43 20 	ld r0,@\(17184,r0\)
+   48:	d0 c0 87 65 	seth r0,#0x8765
+   4c:	a0 a0 43 20 	ldh r0,@\(17184,r0\)
+   50:	d0 c0 87 65 	seth r0,#0x8765
+   54:	a0 b0 43 20 	lduh r0,@\(17184,r0\)
+   58:	d0 c0 87 65 	seth r0,#0x8765
+   5c:	a0 80 43 20 	ldb r0,@\(17184,r0\)
+   60:	d0 c0 87 65 	seth r0,#0x8765
+   64:	a0 90 43 20 	ldub r0,@\(17184,r0\)
+   68:	d0 c0 12 35 	seth r0,#0x1235
+   6c:	a0 c0 ff f0 	ld r0,@\(-16,r0\)
+   70:	d0 c0 12 35 	seth r0,#0x1235
+   74:	a0 a0 ff f0 	ldh r0,@\(-16,r0\)
+   78:	d0 c0 12 35 	seth r0,#0x1235
+   7c:	a0 b0 ff f0 	lduh r0,@\(-16,r0\)
+   80:	d0 c0 12 35 	seth r0,#0x1235
+   84:	a0 80 ff f0 	ldb r0,@\(-16,r0\)
+   88:	d0 c0 12 35 	seth r0,#0x1235
+   8c:	a0 90 ff f0 	ldub r0,@\(-16,r0\)
+   90:	d0 c0 87 65 	seth r0,#0x8765
+   94:	a0 c0 43 20 	ld r0,@\(17184,r0\)
+   98:	d0 c0 87 65 	seth r0,#0x8765
+   9c:	a0 a0 43 20 	ldh r0,@\(17184,r0\)
+   a0:	d0 c0 87 65 	seth r0,#0x8765
+   a4:	a0 b0 43 20 	lduh r0,@\(17184,r0\)
+   a8:	d0 c0 87 65 	seth r0,#0x8765
+   ac:	a0 80 43 20 	ldb r0,@\(17184,r0\)
+   b0:	d0 c0 87 65 	seth r0,#0x8765
+   b4:	a0 90 43 20 	ldub r0,@\(17184,r0\)
+   b8:	d0 c0 12 35 	seth r0,#0x1235
+   bc:	a0 c0 ff f0 	ld r0,@\(-16,r0\)
+   c0:	d0 c0 87 65 	seth r0,#0x8765
+   c4:	a0 40 43 20 	st r0,@\(17184,r0\)
+   c8:	d0 c0 87 65 	seth r0,#0x8765
+   cc:	a0 20 43 20 	sth r0,@\(17184,r0\)
+   d0:	d0 c0 87 65 	seth r0,#0x8765
+   d4:	a0 00 43 20 	stb r0,@\(17184,r0\)
+   d8:	d0 c0 12 35 	seth r0,#0x1235
+   dc:	a0 40 ff f0 	st r0,@\(-16,r0\)
+   e0:	d0 c0 12 35 	seth r0,#0x1235
+   e4:	a0 20 ff f0 	sth r0,@\(-16,r0\)
+   e8:	d0 c0 12 35 	seth r0,#0x1235
+   ec:	a0 00 ff f0 	stb r0,@\(-16,r0\)
+   f0:	d0 c0 87 65 	seth r0,#0x8765
+   f4:	a0 40 43 20 	st r0,@\(17184,r0\)
+   f8:	d0 c0 87 65 	seth r0,#0x8765
+   fc:	a0 20 43 20 	sth r0,@\(17184,r0\)
+  100:	d0 c0 87 65 	seth r0,#0x8765
+  104:	a0 00 43 20 	stb r0,@\(17184,r0\)
+  108:	d0 c0 12 35 	seth r0,#0x1235
+  10c:	a0 40 ff f0 	st r0,@\(-16,r0\)
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