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[PATCH] speedup ppc disassembly (+ questions)
- From: Segher Boessenkool <segher at koffie dot nl>
- To: binutils at sources dot redhat dot com
- Date: Mon, 18 Nov 2002 04:08:49 +0100
- Subject: [PATCH] speedup ppc disassembly (+ questions)
This patch speeds up PowerPC disassembly by about 2x. Low
hanging fruit.
I would like to add in disassembler flags so that it can decode
for _one specific_ cpu core, optionally without using extended
mnemonics, and maybe automatically keyed from the architecture
flag (-mpowerpc:7400 etc.)
Do you think this is a good idea? Currently I get bogus decodes
for some insns that are only in the POWER architecture, and some
very misleading results for some MSR's it doesn't know about but
it _does_ know about an extended mnemonic for a different cpu's
MSR that happens to have the same number (the G4+'s L3CR is one
example, iirc. This isn't the only case, though).
Also, this would require either further (much more intrusive)
change to the table structure or an opcode flags overhaul.
What would you like best? (if you think it's a good idea at all).
Cheers,
Segher
2002-11-18 Segher Boessenkool <segher@koffie.nl>
* include/opcode/ppc.h (powerpc_opcodes): Divide into
sub-tables indexed by major opcode.
* opcodes/ppc-opc.c (powerpc_opcodes): Same.
* opcodes/ppc-dis.c (print_insn_powerpc): Use it.
* gas/config/tc-ppc.c (md_begin): Adapt.
diff -cpr binutils-2.13/gas/config/tc-ppc.c binutils-mijn/gas/config/tc-ppc.c
*** binutils-2.13/gas/config/tc-ppc.c Fri Jul 26 06:23:02 2002
--- binutils-mijn/gas/config/tc-ppc.c Mon Nov 18 03:03:07 2002
*************** md_begin ()
*** 1147,1152 ****
--- 1147,1153 ----
const struct powerpc_macro *macro;
const struct powerpc_macro *macro_end;
boolean dup_insn = false;
+ int major;
ppc_set_cpu ();
*************** md_begin ()
*** 1159,1191 ****
/* Insert the opcodes into a hash table. */
ppc_hash = hash_new ();
! op_end = powerpc_opcodes + powerpc_num_opcodes;
! for (op = powerpc_opcodes; op < op_end; op++)
{
! know ((op->opcode & op->mask) == op->opcode);
!
! if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
! && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
! || ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
! == (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
! || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
! && ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
! || ((op->flags & PPC_OPCODE_POWER4)
! == (ppc_cpu & PPC_OPCODE_POWER4))))
{
! const char *retval;
! retval = hash_insert (ppc_hash, op->name, (PTR) op);
! if (retval != (const char *) NULL)
{
! /* Ignore Power duplicates for -m601. */
! if ((ppc_cpu & PPC_OPCODE_601) != 0
! && (op->flags & PPC_OPCODE_POWER) != 0)
! continue;
!
! as_bad (_("Internal assembler error for instruction %s"),
! op->name);
! dup_insn = true;
}
}
}
--- 1160,1195 ----
/* Insert the opcodes into a hash table. */
ppc_hash = hash_new ();
! for (major = 0; major < 64; major++)
{
! op_end = powerpc_opcodes[major].table + powerpc_opcodes[major].n;
! for (op = powerpc_opcodes[major].table; op < op_end; op++)
{
! know ((op->opcode & op->mask) == op->opcode);
! if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
! && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
! || ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
! == (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
! || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
! && ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
! || ((op->flags & PPC_OPCODE_POWER4)
! == (ppc_cpu & PPC_OPCODE_POWER4))))
{
! const char *retval;
!
! retval = hash_insert (ppc_hash, op->name, (PTR) op);
! if (retval != (const char *) NULL)
! {
! /* Ignore Power duplicates for -m601. */
! if ((ppc_cpu & PPC_OPCODE_601) != 0
! && (op->flags & PPC_OPCODE_POWER) != 0)
! continue;
!
! as_bad (_("Internal assembler error for instruction %s"),
! op->name);
! dup_insn = true;
! }
}
}
}
diff -cpr binutils-2.13/include/opcode/ppc.h binutils-mijn/include/opcode/ppc.h
*** binutils-2.13/include/opcode/ppc.h Mon Feb 25 04:42:59 2002
--- binutils-mijn/include/opcode/ppc.h Mon Nov 18 02:33:43 2002
*************** struct powerpc_opcode
*** 50,60 ****
unsigned char operands[8];
};
! /* The table itself is sorted by major opcode number, and is otherwise
! in the order in which the disassembler should consider
! instructions. */
! extern const struct powerpc_opcode powerpc_opcodes[];
! extern const int powerpc_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
--- 50,64 ----
unsigned char operands[8];
};
! /* The table per major entry is in the order in which the disassembler
! should consider instructions. */
!
! struct powerpc_entry {
! const struct powerpc_opcode *table;
! const int n;
! };
!
! extern const struct powerpc_entry powerpc_opcodes[];
/* Values defined for the flags field of a struct powerpc_opcode. */
diff -cpr binutils-2.13/opcodes/ppc-dis.c binutils-mijn/opcodes/ppc-dis.c
*** binutils-2.13/opcodes/ppc-dis.c Mon Feb 25 04:43:46 2002
--- binutils-mijn/opcodes/ppc-dis.c Mon Nov 18 03:22:17 2002
*************** print_insn_powerpc (memaddr, info, bigen
*** 131,140 ****
/* Get the major opcode of the instruction. */
op = PPC_OP (insn);
! /* Find the first match in the opcode table. We could speed this up
! a bit by doing a binary search on the major opcode. */
! opcode_end = powerpc_opcodes + powerpc_num_opcodes;
! for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
{
unsigned long table_op;
const unsigned char *opindex;
--- 146,155 ----
/* Get the major opcode of the instruction. */
op = PPC_OP (insn);
! /* Find the first match in the opcode table. We have a first
! index on major opcode. */
! opcode_end = powerpc_opcodes[op].table + powerpc_opcodes[op].n;
! for (opcode = powerpc_opcodes[op].table; opcode < opcode_end; opcode++)
{
unsigned long table_op;
const unsigned char *opindex;
*************** print_insn_powerpc (memaddr, info, bigen
*** 143,154 ****
int need_comma;
int need_paren;
- table_op = PPC_OP (opcode->opcode);
- if (op < table_op)
- break;
- if (op > table_op)
- continue;
-
if ((insn & opcode->mask) != opcode->opcode
|| (opcode->flags & dialect) == 0)
continue;
--- 158,163 ----
diff -cpr binutils-2.13/opcodes/ppc-opc.c binutils-mijn/opcodes/ppc-opc.c
*** binutils-2.13/opcodes/ppc-opc.c Thu May 9 13:15:47 2002
--- binutils-mijn/opcodes/ppc-opc.c Mon Nov 18 03:25:14 2002
*************** extract_tbr (insn, dialect, invalid)
*** 1626,1634 ****
The disassembler reads the table in order and prints the first
instruction which matches, so this table is sorted to put more
specific instructions before more general instructions. It is also
! sorted by major opcode. */
! const struct powerpc_opcode powerpc_opcodes[] = {
{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
--- 1626,1637 ----
The disassembler reads the table in order and prints the first
instruction which matches, so this table is sorted to put more
specific instructions before more general instructions. It is also
! divided by major opcode, for higher speed. */
! const struct powerpc_opcode powerpc_opcodes_undef[] = {
! };
!
! const struct powerpc_opcode powerpc_opcodes_2[] = {
{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
*************** const struct powerpc_opcode powerpc_opco
*** 1644,1650 ****
--- 1647,1655 ----
{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_3[] = {
{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
*************** const struct powerpc_opcode powerpc_opco
*** 1675,1681 ****
--- 1680,1688 ----
{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_4[] = {
{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 1917,1967 ****
--- 1924,1994 ----
{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_7[] = {
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_8[] = {
{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_9[] = {
{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_10[] = {
{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_11[] = {
{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_12[] = {
{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_13[] = {
{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_14[] = {
{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_15[] = {
{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_16[] = {
{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
*************** const struct powerpc_opcode powerpc_opco
*** 2226,2243 ****
--- 2253,2276 ----
{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_17[] = {
{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_18[] = {
{ "b", B(18,0,0), B_MASK, COM, { LI } },
{ "bl", B(18,0,1), B_MASK, COM, { LI } },
{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_19[] = {
{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
*************** const struct powerpc_opcode powerpc_opco
*** 2646,2658 ****
--- 2679,2695 ----
{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_20[] = {
{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_21[] = {
{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
*************** const struct powerpc_opcode powerpc_opco
*** 2661,2667 ****
--- 2698,2706 ----
{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_22[] = {
{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
*************** const struct powerpc_opcode powerpc_opco
*** 2669,2701 ****
--- 2708,2756 ----
{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_23[] = {
{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_24[] = {
{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_25[] = {
{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_26[] = {
{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_27[] = {
{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_28[] = {
{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_29[] = {
{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_30[] = {
{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
*************** const struct powerpc_opcode powerpc_opco
*** 2719,2725 ****
--- 2774,2782 ----
{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_31[] = {
{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3767,3831 ****
--- 3824,3942 ----
{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_32[] = {
{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_33[] = {
{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_34[] = {
{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_35[] = {
{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_36[] = {
{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_37[] = {
{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_38[] = {
{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_39[] = {
{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_40[] = {
{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_41[] = {
{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_42[] = {
{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_43[] = {
{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_44[] = {
{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_45[] = {
{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_46[] = {
{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_47[] = {
{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_48[] = {
{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_49[] = {
{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_50[] = {
{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_51[] = {
{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_52[] = {
{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_53[] = {
{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_54[] = {
{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_55[] = {
{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_56[] = {
{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_57[] = {
{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_58[] = {
{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 3846,3852 ****
--- 3957,3965 ----
{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_59[] = {
{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3876,3886 ****
--- 3989,4005 ----
{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_60[] = {
{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_61[] = {
{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_62[] = {
{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 3897,3903 ****
--- 4016,4024 ----
{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
+ };
+ const struct powerpc_opcode powerpc_opcodes_63[] = {
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
*************** const struct powerpc_opcode powerpc_opco
*** 4004,4011 ****
};
! const int powerpc_num_opcodes =
! sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
/* The macro table. This is only used by the assembler. */
--- 4125,4198 ----
};
! #define POWERPC_ENTRY(x) { x, sizeof (x) / sizeof (x[0]) }
!
! const struct powerpc_entry powerpc_opcodes[64] = {
! POWERPC_ENTRY(powerpc_opcodes_undef),
! POWERPC_ENTRY(powerpc_opcodes_undef),
! POWERPC_ENTRY(powerpc_opcodes_2),
! POWERPC_ENTRY(powerpc_opcodes_3),
! POWERPC_ENTRY(powerpc_opcodes_4),
! POWERPC_ENTRY(powerpc_opcodes_undef),
! POWERPC_ENTRY(powerpc_opcodes_undef),
! POWERPC_ENTRY(powerpc_opcodes_7),
! POWERPC_ENTRY(powerpc_opcodes_8),
! POWERPC_ENTRY(powerpc_opcodes_9),
! POWERPC_ENTRY(powerpc_opcodes_10),
! POWERPC_ENTRY(powerpc_opcodes_11),
! POWERPC_ENTRY(powerpc_opcodes_12),
! POWERPC_ENTRY(powerpc_opcodes_13),
! POWERPC_ENTRY(powerpc_opcodes_14),
! POWERPC_ENTRY(powerpc_opcodes_15),
! POWERPC_ENTRY(powerpc_opcodes_16),
! POWERPC_ENTRY(powerpc_opcodes_17),
! POWERPC_ENTRY(powerpc_opcodes_18),
! POWERPC_ENTRY(powerpc_opcodes_19),
! POWERPC_ENTRY(powerpc_opcodes_20),
! POWERPC_ENTRY(powerpc_opcodes_21),
! POWERPC_ENTRY(powerpc_opcodes_22),
! POWERPC_ENTRY(powerpc_opcodes_23),
! POWERPC_ENTRY(powerpc_opcodes_24),
! POWERPC_ENTRY(powerpc_opcodes_25),
! POWERPC_ENTRY(powerpc_opcodes_26),
! POWERPC_ENTRY(powerpc_opcodes_27),
! POWERPC_ENTRY(powerpc_opcodes_28),
! POWERPC_ENTRY(powerpc_opcodes_29),
! POWERPC_ENTRY(powerpc_opcodes_30),
! POWERPC_ENTRY(powerpc_opcodes_31),
! POWERPC_ENTRY(powerpc_opcodes_32),
! POWERPC_ENTRY(powerpc_opcodes_33),
! POWERPC_ENTRY(powerpc_opcodes_34),
! POWERPC_ENTRY(powerpc_opcodes_35),
! POWERPC_ENTRY(powerpc_opcodes_36),
! POWERPC_ENTRY(powerpc_opcodes_37),
! POWERPC_ENTRY(powerpc_opcodes_38),
! POWERPC_ENTRY(powerpc_opcodes_39),
! POWERPC_ENTRY(powerpc_opcodes_40),
! POWERPC_ENTRY(powerpc_opcodes_41),
! POWERPC_ENTRY(powerpc_opcodes_42),
! POWERPC_ENTRY(powerpc_opcodes_43),
! POWERPC_ENTRY(powerpc_opcodes_44),
! POWERPC_ENTRY(powerpc_opcodes_45),
! POWERPC_ENTRY(powerpc_opcodes_46),
! POWERPC_ENTRY(powerpc_opcodes_47),
! POWERPC_ENTRY(powerpc_opcodes_48),
! POWERPC_ENTRY(powerpc_opcodes_49),
! POWERPC_ENTRY(powerpc_opcodes_50),
! POWERPC_ENTRY(powerpc_opcodes_51),
! POWERPC_ENTRY(powerpc_opcodes_52),
! POWERPC_ENTRY(powerpc_opcodes_53),
! POWERPC_ENTRY(powerpc_opcodes_54),
! POWERPC_ENTRY(powerpc_opcodes_55),
! POWERPC_ENTRY(powerpc_opcodes_56),
! POWERPC_ENTRY(powerpc_opcodes_57),
! POWERPC_ENTRY(powerpc_opcodes_58),
! POWERPC_ENTRY(powerpc_opcodes_59),
! POWERPC_ENTRY(powerpc_opcodes_60),
! POWERPC_ENTRY(powerpc_opcodes_61),
! POWERPC_ENTRY(powerpc_opcodes_62),
! POWERPC_ENTRY(powerpc_opcodes_63),
! };
/* The macro table. This is only used by the assembler. */