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RFA: PPC opcodes patch
- From: Nick Clifton <nickc at redhat dot com>
- To: geoffk at redhat dot com
- Cc: binutils at sources dot redhat dot com
- Date: 29 Aug 2002 10:18:27 +0100
- Subject: RFA: PPC opcodes patch
Hi Geoff,
Do you have any objections to my applying the following patch ?
It was developed by Motorola and submitted to Red Hat for us to push
out to the FSF. I do not believe that there are any copyright
issues here as we already have several assignments on file from
Motorola.
The patch fixes several small problems with the PPC opcodes library.
Cheers
Nick
2002-08-29 Nick Clifton <nickc@redhat.com>
* ppc-dis.c (print_insn_powerpc): Skip Altivec instructions
when searching for SPE instructions.
* ppc-opc.c (RAB): Add operand.
(PMR): Alias for SPR operand.
(insert_rab): Insert an RAB operand.
(extract_rab): Extract an RAB operand.
(evsubw, evsubiw, evmr, evnot): New mnemonics.
(evfsneg): Fix opcode value.
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.9
diff -c -3 -p -w -r1.9 ppc-dis.c
*** opcodes/ppc-dis.c 19 Aug 2002 20:59:09 -0000 1.9
--- opcodes/ppc-dis.c 29 Aug 2002 08:53:48 -0000
*************** print_insn_powerpc (memaddr, info, bigen
*** 176,181 ****
--- 176,184 ----
continue;
if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC))
+ continue;
+
+ if ((dialect & PPC_OPCODE_SPE) && (opcode->flags & PPC_OPCODE_ALTIVEC))
continue;
/* Make two passes over the operands. First see if any of them
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.35
diff -c -3 -p -w -r1.35 ppc-opc.c
*** opcodes/ppc-opc.c 19 Aug 2002 20:59:10 -0000 1.35
--- opcodes/ppc-opc.c 29 Aug 2002 08:53:49 -0000
*************** static unsigned long insert_pmrn
*** 104,109 ****
--- 104,113 ----
PARAMS ((unsigned long, long, int, const char **));
static long extract_pmrn
PARAMS ((unsigned long, int, int *));
+ static unsigned long insert_rab
+ PARAMS ((unsigned long, long, int, const char **));
+ static long extract_rab
+ PARAMS ((unsigned long, int, int *));
static unsigned long insert_ral
PARAMS ((unsigned long, long, int, const char **));
static unsigned long insert_ram
*************** const struct powerpc_operand powerpc_ope
*** 431,440 ****
#define RBS RB + 1
{ 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
/* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
instruction or the RT field in a D, DS, X, XFX or XO form
instruction. */
! #define RS RBS + 1
#define RT RS
#define RT_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_GPR },
--- 435,447 ----
#define RBS RB + 1
{ 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
+ #define RAB RBS + 1
+ { 5, 1, insert_rab, extract_rab, PPC_OPERAND_FAKE },
+
/* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
instruction or the RT field in a D, DS, X, XFX or XO form
instruction. */
! #define RS RAB + 1
#define RT RS
#define RT_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_GPR },
*************** const struct powerpc_operand powerpc_ope
*** 461,466 ****
--- 468,474 ----
/* The SPR field in an XFX form instruction. This is flipped--the
lower 5 bits are stored in the upper 5 and vice- versa. */
#define SPR SISIGNOPT + 1
+ #define PMR SPR
#define SPR_MASK (0x3ff << 11)
{ 10, 11, insert_spr, extract_spr, 0 },
*************** extract_pmrn (insn, dialect, invalid)
*** 1251,1256 ****
--- 1259,1292 ----
return ((insn >> 16) & 0x1f) | ((insn >> 11) & 0x3e);
}
+ /* The RB field in an X form instruction when it must be the same as
+ the RA field in the instruction. This is used for extended
+ mnemonics like evmr. This operand is marked FAKE. The insertion
+ function just copies the RA field into the RB field, and the
+ extraction function just checks that the fields are the same. */
+
+ static unsigned long
+ insert_rab (insn, value, dialect, errmsg)
+ unsigned long insn;
+ long value ATTRIBUTE_UNUSED;
+ int dialect ATTRIBUTE_UNUSED;
+ const char **errmsg ATTRIBUTE_UNUSED;
+ {
+ return insn | (((insn >> 16) & 0x1f) << 11);
+ }
+
+ static long
+ extract_rab (insn, dialect, invalid)
+ unsigned long insn;
+ int dialect ATTRIBUTE_UNUSED;
+ int *invalid;
+ {
+ if (invalid != (int *) NULL
+ && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
+ *invalid = 1;
+ return 0;
+ }
+
/* The RA field in a D or X form instruction which is an updating
load, which means that the RA field may not be zero and may not
equal the RT field. */
*************** const struct powerpc_opcode powerpc_opco
*** 2089,2095 ****
--- 2126,2134 ----
{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RD, RB, UIMM } },
{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RD, RA, RB } },
+ { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RD, RB, RA } },
{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RD, UIMM, RB } },
+ { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RD, RB, UIMM } },
{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RD, RA } },
{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RD, RA } },
{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RD, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 2102,2113 ****
--- 2141,2154 ----
{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RD, RA, RB } },
+ { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RD, RA, RAB } },
{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RD, RA, RB } },
+ { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RD, RA, RAB } },
{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
*************** const struct powerpc_opcode powerpc_opco
*** 2171,2177 ****
{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RD, RA } },
! { "evfsneg", VX(4, 656), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RD, RA, RB } },
--- 2212,2218 ----
{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RD, RA } },
! { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RD, RA } },
{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RD, RA, RB } },
{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RD, RA, RB } },