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[applied 2.12-branch mips patch] [was Re: merge to branch]
At Tue, 30 Apr 2002 19:54:09 +0000 (UTC), cgd@broadcom.com wrote:
> At Mon, 29 Apr 2002 19:48:40 +0000 (UTC), cgd@broadcom.com wrote:
> > The ones in:
> >
> > http://sources.redhat.com/ml/binutils/2002-03/msg00136.html
> > http://sources.redhat.com/ml/binutils/2002-03/msg00202.html
>
> Building and testing, I also found that:
>
> http://sources.redhat.com/ml/binutils/2002-03/msg00271.html
>
> was useful. (it gets mipsisa32-elf down to 0 failures. 8-)
What I pulled up is included below.
For sanity's sake, I verified that I didn't break anything obvious via
gmake && gmake check of binutils for 9 MIPS ELF targets, hosted on
x86 linux. 8-)
cgd
==============================================================================
[ opcodes/ChangeLog ]
2002-04-29 Chris Demetriou <cgd@broadcom.com>
Merge from mainline:
2002-03-06 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Mark "pref" as being
present on I4.
Merge from mainline:
2002-03-06 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps".
Merge from mainline:
2002-03-15 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (is_newabi): Fix ABI decoding.
[ gas/testsuite/ChangeLog ]
2002-04-30 Chris Demetriou <cgd@broadcom.com>
Merge from mainline:
2002-03-15 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/mips.exp: Use elf-rel2 and elfel-rel2 for
mipsisa32*-*-* targets, rather than e32-rel2 and e32el-rel2.
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.24
diff -u -p -r1.24 mips-dis.c
--- opcodes/mips-dis.c 5 Nov 2001 03:07:51 -0000 1.24
+++ opcodes/mips-dis.c 30 Apr 2002 21:36:34 -0000
@@ -397,10 +397,14 @@ static int
is_newabi (header)
Elf_Internal_Ehdr *header;
{
- if ((header->e_flags
- & (E_MIPS_ABI_EABI32 | E_MIPS_ABI_EABI64 | EF_MIPS_ABI2)) != 0
- || (header->e_ident[EI_CLASS] == ELFCLASS64
- && (header->e_flags & E_MIPS_ABI_O64) == 0))
+ /* There are no old-style ABIs which use 64-bit ELF. */
+ if (header->e_ident[EI_CLASS] == ELFCLASS64)
+ return 1;
+
+ /* If a 32-bit ELF file, N32, EABI32, and EABI64 are new-style ABIs. */
+ if ((header->e_flags & EF_MIPS_ABI2) != 0
+ || (header->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32
+ || (header->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI64)
return 1;
return 0;
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.28
diff -u -p -r1.28 mips-opc.c
--- opcodes/mips-opc.c 23 Oct 2001 19:20:27 -0000 1.28
+++ opcodes/mips-opc.c 30 Apr 2002 21:36:35 -0000
@@ -114,7 +114,7 @@ const struct mips_opcode mips_builtin_op
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, membership */
-{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I32|G3 },
+{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
{"ssnop", "", 0x00000040, 0xffffffff, 0, I32 },
@@ -583,6 +583,7 @@ const struct mips_opcode mips_builtin_op
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
+{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 },
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
@@ -591,6 +592,7 @@ const struct mips_opcode mips_builtin_op
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
+{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
/* move is at the top of the table. */
{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.28.2.1
diff -u -p -r1.28.2.1 mips.exp
--- gas/testsuite/gas/mips/mips.exp 26 Feb 2002 22:24:46 -0000 1.28.2.1
+++ gas/testsuite/gas/mips/mips.exp 30 Apr 2002 21:36:36 -0000
@@ -179,14 +179,17 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mips-abi32-pic"
run_dump_test "elf${el}-rel"
- if [istarget mips64*-*-*] {
+ if {[istarget mips64*-*-*] || [istarget mipsisa32*-*-*]} {
run_dump_test "elf${el}-rel2"
- run_dump_test "elf-rel4"
- } {
+ } else {
run_dump_test "e32${el}-rel2"
- run_dump_test "e32-rel4"
}
run_dump_test "elf${el}-rel3"
+ if {[istarget mips64*-*-*]} {
+ run_dump_test "elf-rel4"
+ } else {
+ run_dump_test "e32-rel4"
+ }
run_dump_test "elf-rel5"
run_dump_test "${tmips}${el}empic"
run_dump_test "empic2"