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Software workaround for buggy MIPS CPU
- From: "Kris Warkentin" <kewarken at qnx dot com>
- To: <binutils at sources dot redhat dot com>, <gcc at gcc dot gnu dot org>
- Date: Mon, 15 Apr 2002 12:32:17 -0400
- Subject: Software workaround for buggy MIPS CPU
[Cross posted to binutils and gcc since it may be easier to solve in one
rather than the other]
We are trying to code a temporary workaround for a buggy CPU that only needs
to last until they can fix the hardware.
The simplified version is that a certain class of floating point assembly
instructions, say FBAD1, cause problems when followed by another class,
for example, sequences of the form:
FBAD1 $1, $f2
FBAD2 $2, $f3
cause problems. I'd love to tell you more but I'm not a hardware guy so
most of the explaination of what the 'problems' are went over my head.
What I did understand is that as long as they put a 'mfc1 $0, $f1' in
between these instructions, everything is okay. I gather a 'nop' isn't
sufficient since they not only need timing delay in the pipeline but
something else that happens with an mfc1.
Essentially it looks like we need a filter to recognize the invalid
construct and insert the extra instruction. I had thought about putting
some script or something in between the compiler and the assembler which
would do this but there are obviously performance issues involved in that.
I was hoping that someone might be able to tell me:
a) Is it easier to insert an arbitrary filter into the compiler or the
b) Given the answer to a), can you offer any hints/suggestions as to where I
Thank you very much.