This is the mail archive of the
binutils@sources.redhat.com
mailing list for the binutils project.
Re: [PATCH] a couple of tweaks to opcodes/mips.h
"Eric M. Christopher" <echristo@redhat.com> writes:
> On Wed, 2001-10-17 at 12:11, cgd@broadcom.com wrote:
> > How about these tweaks to opcodes/mips.h:
> >
> > 2001-10-17 Chris Demetriou <cgd@broadcom.com>
> >
> > * mips.h: Sort coprocessor instruction argument characters.
> > (OPCODE_IS_MEMBER): Add no-op term to the expression, for
> > easier source code merging.
> >
> > (I don't know that the latter is "OK" by the coding standards, but it
> > sure is a pain to have to have to slightly tweak the OPCODE_IS_MEMBER
> > changes at almost every source code merge. I'm sure others feel this
> > pain. 8-)
> >
>
> I doubt it's ok, but I'll let Nick Clifton, Style Nazi, comment on it.
> :)
Heh. OK, well, I'm not planning on adding any more new CPUs for a
while, so if he comments i'll add that bit, but if not i'm not going
to worry about it. 8-)
Anyway, I've committed the following as obvious.
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h: Sort coprocessor instruction argument characters
in comment, add a few more words of description for "H".
Index: mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.20
diff -u -r1.20 mips.h
--- mips.h 2001/10/18 01:42:16 1.20
+++ mips.h 2001/10/18 01:48:38
@@ -209,8 +209,8 @@
Coprocessor instructions:
"E" 5 bit target register (OP_*_RT)
"G" 5 bit destination register (OP_*_RD)
+ "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
- "H" 3 bit sel field (OP_*_SEL)
Macro instructions:
"A" General 32 bit expression