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Re: binutils patches for Cirrus/arm9e/maverick support
- To: Aldy Hernandez <aldyh at redhat dot com>
- Subject: Re: binutils patches for Cirrus/arm9e/maverick support
- From: Richard Earnshaw <rearnsha at arm dot com>
- Date: Thu, 11 Oct 2001 16:26:57 +0100
- cc: Richard dot Earnshaw at arm dot com, Nick Clifton <nickc at cambridge dot redhat dot com>, binutils <binutils at sources dot redhat dot com>
- Organization: ARM Ltd.
- Reply-To: Richard dot Earnshaw at arm dot com
>
> > True, provided I can work out what is supposed to be correct and what
> > isn't. Without the specs it's going to be much more work than I'd planned
> > for, which is going to delay me feeding back my changes... :-(
>
> well, lemme see if i can help you out:
>
> the testsuite should have all the combinations (i think).
>
> cfldr* CIRRUS_REG, [ARM_REG, offset]*
> cfldr* CIRRUS_REG, [ARM_REG]*
> (same for cfstr*)
>
> cfmvsr CIRRUS_REG, ARM_REG (and cfmvdlr, cfmvdhr, cfmv64lr, cfmv64hr,
>
> cfmvrs ARM_REG, CIRRUS_REG (and cfmvrdh, cfmvr64l, cfmvr64h
>
> shit, this is going to take forever.
It shouldn't be that bad, provided the original insns are classified
adequately. For example, we already have the classifications
do_c_binops_[123], do_c_triple_[45], do_c_quad_6, do_c_dspsc_[12],
do_c_shift_[12] and do_c_ldst_[1234]; so all we need is to know how each
of these is broken down. In all cases they must map onto appropriate ARM
co-processor instructions (so for example, all load/store operations can
probably be handled with cp_address_required_here for the address bits).
R.