Re: binutils patches for Cirrus/arm9e/maverick support

[Richard Earnshaw <rearnsha at arm dot com>]

> Hi Richard,
> 
> > I'm going to have to rewrite cirrus_reg_required_here, since in my
> > new parser there is no single hash table containing all the
> > registers; instead there is a hash table for each class of register
> > and the assembler must look up the register name in the appropriate
> > class.  Which leads to the above function.  There are several places
> > where the above is called with CIRRUS_REGTYPE_ANY.  That wouldn't be
> > too bad, but why on earth would an ARM register name be valid at the
> > same position in the syntax as a CIRRUS register?
> 
> It wouldn't.  But the code has already ascertained that the register
> *is* a Cirrus register, it just needs to make sure that it is a Cirrus
> register of the correct type.  (Of course in the case of
> CIRRUS_REGTYPE_ANY, this test is a no-op).  ie before
> cirrus_reg_required_here() is called, cirrurs_register() has been
> called to check the register number.

No it hasn't.  The code also accepts int_register(), which is true if it 
is an ARM core register.

  if ((reg = arm_reg_parse (str)) != FAIL
      && (int_register (reg)
<<< Accept an ARM reg >>>

	  || cirrus_register (reg)))
<<< or a cirrus reg >>>
    {
      int orig_reg = reg;

      /* Calculate actual register # for opcode.  */
      if (cirrus_register (reg)
	  && !ARM_EXT_MAVERICKsc_register (reg)) /* Leave this one as is.  */
	{
<<< if it's a cirrus reg, map it down >>>

	}

      if (!cirrus_valid_reg (orig_reg, regtype))
	{
<<< if it isn't a reg of the right type >>>
	  sprintf (buff, _("invalid register type at '%.100s'"), start);
	  inst.error = buff;
	  return FAIL;
	}

      if (shift >= 0)
	inst.instruction |= reg << shift;
<<< stuff the bits into the opcode >>>

      return orig_reg;

Note that cirrus_valid_reg() returns true for *ANY* register if passed 
CIRRUS_REGTYPE_ANY, so it doesn't reject integer regs here.

Let's take for example "cfmvsr".  As far as I can tell from the testsuite 
code, this is an operation of the form

	cfmvsr<cond>  <mvfreg>, <armreg>

But, from reading the code, I'm sure if you put in

	cfmvsr	r0, mvf5
or
	cfmvsr	mvdx0, r1
or
	cfmvsr	dspsc, r0

or a number of other invalid operations, then the assembler will fail to 
diagnose the mistake.

R.