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D30v patch to fix decoding of pc-relative operands
- To: binutils at sourceware dot cygnus dot com
- Subject: D30v patch to fix decoding of pc-relative operands
- From: Nick Clifton <nickc at cygnus dot com>
- Date: Thu, 2 Mar 2000 15:01:08 -0800
- CC: amylaar at cygnus dot com
Hi Guys,
I am checking in the following patch to fix the decoding of d30v
instructions which have pc relative operands. This patch was
developed by J"orn Rennecke.
Cheers
Nick
2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
* d30v.h:
(SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
(SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
(SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
(SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
(SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
(LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
(LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
Index: include/opcode/d30v.h
===================================================================
RCS file: /cvs/src//src/include/opcode/d30v.h,v
retrieving revision 1.3
diff -p -r1.3 d30v.h
*** d30v.h 2000/02/22 20:52:14 1.3
--- d30v.h 2000/03/02 22:53:52
*************** struct d30v_opcode
*** 85,124 ****
#define SHORT_A 9
#define SHORT_B1 11
#define SHORT_B2 12
! #define SHORT_B3 13
! #define SHORT_B3b 15
! #define SHORT_D1 17
! #define SHORT_D2 19
! #define SHORT_D2B 21
! #define SHORT_U 23 /* unary SHORT_A. ABS for example */
! #define SHORT_F 25 /* SHORT_A with flag registers */
! #define SHORT_AF 27 /* SHORT_A with only the first register a flag register */
! #define SHORT_T 29 /* for trap instruction */
! #define SHORT_A5 30 /* SHORT_A with a 5-bit immediate instead of 6 */
! #define SHORT_CMP 32 /* special form for CMPcc */
! #define SHORT_CMPU 34 /* special form for CMPUcc */
! #define SHORT_A1 36 /* special form of SHORT_A for MACa opcodes where a=1 */
! #define SHORT_AA 38 /* SHORT_A with the first register an accumulator */
! #define SHORT_RA 40 /* SHORT_A with the second register an accumulator */
! #define SHORT_MODINC 42
! #define SHORT_MODDEC 43
! #define SHORT_C1 44
! #define SHORT_C2 45
! #define SHORT_UF 46
! #define SHORT_A2 47
! #define SHORT_A5S 49
! #define SHORT_NONE 51 /* no operands */
! #define LONG 52
! #define LONG_U 53 /* unary LONG */
! #define LONG_AF 54 /* LONG with the first register a flag register */
! #define LONG_CMP 55 /* special form for CMPcc and CMPUcc */
! #define LONG_M 56 /* Memory long for ldb, stb */
! #define LONG_M2 57 /* Memory long for ld2w, st2w */
! #define LONG_2 58 /* LONG with 2 operands; bratnz */
! #define LONG_2b 59 /* LONG_2 with modifier of 3 */
! #define LONG_D 60 /* for DBRAI*/
! #define LONG_Db 61 /* for repeati*/
! #define SHORT_AR 62 /* like SHORT_AA but only accept register as third parameter */
/* the execution unit(s) used */
int unit;
--- 85,130 ----
#define SHORT_A 9
#define SHORT_B1 11
#define SHORT_B2 12
! #define SHORT_B2r 13
! #define SHORT_B3 14
! #define SHORT_B3r 16
! #define SHORT_B3b 18
! #define SHORT_B3br 20
! #define SHORT_D1r 22
! #define SHORT_D2 24
! #define SHORT_D2r 26
! #define SHORT_D2Br 28
! #define SHORT_U 30 /* unary SHORT_A. ABS for example */
! #define SHORT_F 31 /* SHORT_A with flag registers */
! #define SHORT_AF 33 /* SHORT_A with only the first register a flag register */
! #define SHORT_T 35 /* for trap instruction */
! #define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */
! #define SHORT_CMP 38 /* special form for CMPcc */
! #define SHORT_CMPU 40 /* special form for CMPUcc */
! #define SHORT_A1 48 /* special form of SHORT_A for MACa opcodes where a=1 */
! #define SHORT_AA 44 /* SHORT_A with the first register an accumulator */
! #define SHORT_RA 46 /* SHORT_A with the second register an accumulator */
! #define SHORT_MODINC 48
! #define SHORT_MODDEC 49
! #define SHORT_C1 50
! #define SHORT_C2 51
! #define SHORT_UF 52
! #define SHORT_A2 53
! #define SHORT_NONE 55 /* no operands */
! #define LONG 56
! #define LONG_U 57 /* unary LONG */
! #define LONG_Ur 58 /* LONG pc-relative */
! #define LONG_CMP 59 /* special form for CMPcc and CMPUcc */
! #define LONG_M 60 /* Memory long for ldb, stb */
! #define LONG_M2 61 /* Memory long for ld2w, st2w */
! #define LONG_2 62 /* LONG with 2 operands; jmptnz */
! #define LONG_2r 63 /* LONG with 2 operands; bratnz */
! #define LONG_2b 64 /* LONG_2 with modifier of 3 */
! #define LONG_2br 65 /* LONG_2r with modifier of 3 */
! #define LONG_D 66 /* for DJMPI*/
! #define LONG_Dr 67 /* for DBRAI*/
! #define LONG_Dbr 68 /* for repeati*/
! #define SHORT_AR 69 /* like SHORT_AA but only accept register as third parameter */
/* the execution unit(s) used */
int unit;
*************** extern const struct d30v_operand d30v_op
*** 248,253 ****
--- 254,263 ----
/* let the optimizer know that two registers are affected */
#define OPERAND_2REG (0x10000)
+
+ /* This operand is pc-relative. Note that repeati can have two immediate
+ operands, one of which is pcrel, the other (the IMM6U one) is not. */
+ #define OPERAND_PCREL (0x20000)
/* The format table is an array of struct d30v_format. */
struct d30v_format
2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
* d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand
flag to determine if operand is pc-relative.
* d30v-opc.c:
(d30v_format_table):
(REL6S3): Renamed from IMM6S3.
Added flag OPERAND_PCREL.
(REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with
added flag OPERAND_PCREL.
(IMM12S3U): Replaced with REL12S3.
(SHORT_D2, LONG_D): Delay target is pc-relative.
(SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r):
Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r,
using the REL* operands.
(LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D.
(SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B,
LONG_Db, using REL* operands.
(SHORT_U, SHORT_A5S): Removed stray alternatives.
(d30v_opcode_table): Use new *r formats.
Index: opcodes/d30v-opc.c
===================================================================
RCS file: /cvs/src//src/opcodes/d30v-opc.c,v
retrieving revision 1.3
diff -p -r1.3 d30v-opc.c
*** d30v-opc.c 2000/02/22 20:44:14 1.3
--- d30v-opc.c 2000/03/02 22:53:52
*************** const struct d30v_opcode d30v_opcode_tab
*** 222,241 ****
{ "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
{ "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
{ "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
! { "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL },
! { "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL },
! { "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL },
{ "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
! { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL },
! { "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL },
! { "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL },
{ "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
{ "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
{ "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
! { "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
! { "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
! { "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
! { "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
{ "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 },
{ "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
{ "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
--- 222,241 ----
{ "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
{ "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
{ "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
! { "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL },
! { "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL },
! { "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL },
{ "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
! { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL },
! { "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL },
! { "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL },
{ "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
{ "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
{ "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
! { "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
! { "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
! { "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
! { "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
{ "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 },
{ "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
{ "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
*************** const struct d30v_opcode d30v_opcode_tab
*** 290,297 ****
{ "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
{ "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
{ "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 },
! { "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
! { "repeati", BRA, 0x1a, { SHORT_D2B, LONG_Db }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
{ "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
{ "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
{ "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 },
--- 290,297 ----
{ "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
{ "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
{ "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 },
! { "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
! { "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
{ "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
{ "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
{ "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 },
*************** const struct d30v_operand d30v_operand_t
*** 357,381 ****
{ 6, 1, 6, OPERAND_ACC|OPERAND_REG },
#define IMM5 (Ab + 1)
{ 6, 5, 12, OPERAND_NUM },
! #define IMM5U (IMM5 + 1)
! { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
! #define IMM5S3 (IMM5U + 1)
! { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED },
! #define IMM6 (IMM5S3 + 1)
{ 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
! #define IMM6U (IMM6 + 1)
{ 6, 6, 0, OPERAND_NUM },
! #define IMM6U2 (IMM6U + 1)
{ 6, 6, 12, OPERAND_NUM },
! #define IMM6S3 (IMM6U2 + 1)
! { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT },
! #define IMM12S3 (IMM6S3 + 1)
{ 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
! #define IMM12S3U (IMM12S3 + 1)
! { 12, 12, 12, OPERAND_NUM|OPERAND_SHIFT },
! #define IMM18S3 (IMM12S3U + 1)
{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
! #define IMM32 (IMM18S3 + 1)
{ 32, 32, 0, OPERAND_NUM },
#define Fa (IMM32 + 1)
{ 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
--- 357,385 ----
{ 6, 1, 6, OPERAND_ACC|OPERAND_REG },
#define IMM5 (Ab + 1)
{ 6, 5, 12, OPERAND_NUM },
! #define IMM5U (IMM5 + 1)
! { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
! #define IMM5S3 (IMM5U + 1)
! { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */
! #define IMM6 (IMM5S3 + 1)
{ 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED },
! #define IMM6U (IMM6 + 1)
{ 6, 6, 0, OPERAND_NUM },
! #define IMM6U2 (IMM6U + 1)
{ 6, 6, 12, OPERAND_NUM },
! #define REL6S3 (IMM6U2 + 1)
! { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT|OPERAND_PCREL },
! #define REL12S3 (REL6S3 + 1)
! { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
! #define IMM12S3 (REL12S3 + 1)
{ 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
! #define REL18S3 (IMM12S3 + 1)
! { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL },
! #define IMM18S3 (REL18S3 + 1)
{ 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT },
! #define REL32 (IMM18S3 + 1)
! { 32, 32, 0, OPERAND_NUM|OPERAND_PCREL },
! #define IMM32 (REL32 + 1)
{ 32, 32, 0, OPERAND_NUM },
#define Fa (IMM32 + 1)
{ 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
*************** const struct d30v_format d30v_format_tab
*** 414,438 ****
{ SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
{ SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
{ SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
! { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
{ SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
! { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
{ SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
{ SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
{ SHORT_B1, 0, { Rc } }, /* Rc */
{ SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
{ SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */
{ SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */
{ SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */
{ SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */
! { SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */
! { SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */
! { SHORT_D2, 0, { IMM6S3, Rc } }, /* imm6s3,Rc */
! { SHORT_D2, 2, { IMM6S3, IMM12S3 } }, /* imm6s3,imm12s3 */
! { SHORT_D2B, 0, { IMM6U, Rc } }, /* imm6u,Rc */
! { SHORT_D2B, 2, { IMM6U, IMM12S3U } }, /* imm6u,imm12s3u */
{ SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
- { SHORT_U, 2, { Ra, IMM12S3 } }, /* Ra,imm12 (repeat) */
{ SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
{ SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
{ SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
--- 418,448 ----
{ SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
{ SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */
{ SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
! { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */
{ SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
! { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */
{ SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
{ SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */
{ SHORT_B1, 0, { Rc } }, /* Rc */
{ SHORT_B2, 2, { IMM18S3 } }, /* imm18 */
+ { SHORT_B2r, 2, { REL18S3 } }, /* rel18 */
{ SHORT_B3, 0, { Ra3, Rc } }, /* Ra,Rc */
{ SHORT_B3, 2, { Ra3, IMM12S3 } }, /* Ra,imm12 */
+ { SHORT_B3r, 0, { Ra3, Rc } }, /* Ra,Rc */
+ { SHORT_B3r, 2, { Ra3, REL12S3 } }, /* Ra,rel12 */
{ SHORT_B3b, 1, { Ra3, Rc } }, /* Ra,Rc */
{ SHORT_B3b, 3, { Ra3, IMM12S3 } }, /* Ra,imm12 */
! { SHORT_B3br, 1, { Ra3, Rc } }, /* Ra,Rc */
! { SHORT_B3br, 3, { Ra3, REL12S3 } }, /* Ra,rel12 */
! { SHORT_D1r, 0, { Ra, Rc } }, /* Ra,Rc */
! { SHORT_D1r, 2, { Ra, REL12S3 } }, /* Ra,rel12s3 */
! { SHORT_D2, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
! { SHORT_D2, 2, { REL6S3, IMM12S3 } }, /* rel6s3,imm12s3 */
! { SHORT_D2r, 0, { REL6S3, Rc } }, /* rel6s3,Rc */
! { SHORT_D2r, 2, { REL6S3, REL12S3 } }, /* rel6s3,rel12s3 */
! { SHORT_D2Br, 0, { IMM6U, Rc } }, /* imm6u,Rc */
! { SHORT_D2Br, 2, { IMM6U, REL12S3 } }, /* imm6u,rel12s3 */
{ SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */
{ SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */
{ SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */
{ SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */
*************** const struct d30v_format d30v_format_tab
*** 457,475 ****
{ SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
{ SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */
{ SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */
- { SHORT_A5S, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */
- { SHORT_A5S, 2, { Ra, Rb, IMM5U } }, /* Ra,Rb,imm5u (shifts) */
{ SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
{ LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
{ LONG_U, 2, { IMM32 } }, /* imm32 */
! { LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */
{ LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
{ LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
{ LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
{ LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */
{ LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */
! { LONG_D, 2, { IMM6S3, IMM32 } }, /* imm6s3,imm32 */
! { LONG_Db, 2, { IMM6U, IMM32 } }, /* imm6,imm32 */
{ SHORT_AR, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
{ 0, 0, { 0 } },
};
--- 467,486 ----
{ SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */
{ SHORT_A2, 0, { Ra2, Rb, Rc } }, /* Ra2,Rb,Rc */
{ SHORT_A2, 2, { Ra2, Rb, IMM6 } }, /* Ra2,Rb,imm6 */
{ SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */
{ LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */
{ LONG_U, 2, { IMM32 } }, /* imm32 */
! { LONG_Ur, 2, { REL32 } }, /* rel32 */
{ LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */
{ LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
{ LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */
{ LONG_2, 2, { Ra3, IMM32 } }, /* Ra,imm32 */
+ { LONG_2r, 2, { Ra3, REL32 } }, /* Ra,rel32 */
{ LONG_2b, 3, { Ra3, IMM32 } }, /* Ra,imm32 */
! { LONG_2br, 3, { Ra3, REL32 } }, /* Ra,rel32 */
! { LONG_D, 2, { REL6S3, IMM32 } }, /* rel6s3,imm32 */
! { LONG_Dr, 2, { REL6S3, REL32 } }, /* rel6s3,rel32 */
! { LONG_Dbr, 2, { IMM6U, REL32 } }, /* imm6,rel32 */
{ SHORT_AR, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */
{ 0, 0, { 0 } },
};
Index: opcodes/d30v-dis.c
===================================================================
RCS file: /cvs/src//src/opcodes/d30v-dis.c,v
retrieving revision 1.1.1.1
diff -p -r1.1.1.1 d30v-dis.c
*** d30v-dis.c 1999/05/03 07:28:59 1.1.1.1
--- d30v-dis.c 2000/03/02 22:53:52
*************** print_insn ( info, memaddr, num, insn, i
*** 305,342 ****
(info->stream, _("<unknown register %d>"), val & 0x3F);
}
}
! else if (insn->op->reloc_flag == RELOC_PCREL ||
! (opind == 1 && (insn->form->form == SHORT_D2 || insn->form->form == LONG_D)))
! {
! long max;
! int neg=0;
! max = (1 << (bits - 1));
! if (val & max)
{
! if (bits == 32)
! val = -val;
! else
! val = -val & ((1 << bits)-1);
! neg = 1;
}
! if (opind == 1 && (insn->form->form == SHORT_D2 || insn->form->form == LONG_D))
{
! (*info->fprintf_func) (info->stream, "%x",val);
}
- else {
- if (neg)
- {
- (*info->fprintf_func) (info->stream, "-%x\t(",val);
- (*info->print_address_func) ((memaddr - val) & PC_MASK, info);
- (*info->fprintf_func) (info->stream, ")");
- }
- else
- {
- (*info->fprintf_func) (info->stream, "%x\t(",val);
- (*info->print_address_func) ((memaddr + val) & PC_MASK, info);
- (*info->fprintf_func) (info->stream, ")");
- }
- }
}
else if (insn->op->reloc_flag == RELOC_ABS)
{
--- 305,345 ----
(info->stream, _("<unknown register %d>"), val & 0x3F);
}
}
! /* repeati has a relocation, but its first argument is a plain
! immediate. OTOH instructions like djsri have a pc-relative
! delay target, but a absolute jump target. Therefore, a test
! of insn->op->reloc_flag is not specific enough; we must test
! if the actual operand we are handling now is pc-relative. */
! else if (oper->flags & OPERAND_PCREL)
! {
! int neg = 0;
!
! /* IMM6S3 is unsigned. */
! if (oper->flags & OPERAND_SIGNED || bits == 32)
! {
! long max;
! max = (1 << (bits - 1));
! if (val & max)
! {
! if (bits == 32)
! val = -val;
! else
! val = -val & ((1 << bits)-1);
! neg = 1;
! }
! }
! if (neg)
{
! (*info->fprintf_func) (info->stream, "-%x\t(",val);
! (*info->print_address_func) ((memaddr - val) & PC_MASK, info);
! (*info->fprintf_func) (info->stream, ")");
}
! else
{
! (*info->fprintf_func) (info->stream, "%x\t(",val);
! (*info->print_address_func) ((memaddr + val) & PC_MASK, info);
! (*info->fprintf_func) (info->stream, ")");
}
}
else if (insn->op->reloc_flag == RELOC_ABS)
{