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[binutils-gdb] x86: fix Disp8 handling for AVX512VL VPCMP*{B, W} variants
- From: Jan Beulich <jbeulich at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 10 Jan 2018 13:53:59 -0000
- Subject: [binutils-gdb] x86: fix Disp8 handling for AVX512VL VPCMP*{B, W} variants
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c9e9227878d172d93bcbef51dfc76d96f027751d
commit c9e9227878d172d93bcbef51dfc76d96f027751d
Author: Jan Beulich <jbeulich@novell.com>
Date: Wed Jan 10 14:53:05 2018 +0100
x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants
In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W}
pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL
variants.
Diff:
---
gas/ChangeLog | 10 ++++
gas/testsuite/gas/i386/avx512bw-intel.d | 4 ++
gas/testsuite/gas/i386/avx512bw.d | 4 ++
gas/testsuite/gas/i386/avx512bw.s | 4 ++
gas/testsuite/gas/i386/avx512bw_vl-intel.d | 8 +++
gas/testsuite/gas/i386/avx512bw_vl.d | 8 +++
gas/testsuite/gas/i386/avx512bw_vl.s | 8 +++
opcodes/ChangeLog | 10 ++++
opcodes/i386-opc.tbl | 96 +++++++++++++++---------------
opcodes/i386-tbl.h | 96 +++++++++++++++---------------
10 files changed, 152 insertions(+), 96 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4ab6fa3..07952a6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2018-01-10 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/avx512bw.s,
+ testsuite/gas/i386/avx512bw_vl.s: Add VPCMP* tests with memory
+ operands.
+ * testsuite/gas/i386/avx512bw-intel.d,
+ testsuite/gas/i386/avx512bw.d,
+ testsuite/gas/i386/avx512bw_vl-intel.d.
+ testsuite/gas/i386/avx512bw_vl.d: Adjust expectations.
+
2018-01-09 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/auipc-x0.d: New.
diff --git a/gas/testsuite/gas/i386/avx512bw-intel.d b/gas/testsuite/gas/i386/avx512bw-intel.d
index 932a295..635458d 100644
--- a/gas/testsuite/gas/i386/avx512bw-intel.d
+++ b/gas/testsuite/gas/i386/avx512bw-intel.d
@@ -779,6 +779,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f aa c0 df ff ff 7b[ ]*vpcmpb k5,zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 00[ ]*vpcmpeqb k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 02[ ]*vpcmpleb k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f 68 7f 02[ ]*vpcmpleb k5,zmm6,ZMMWORD PTR \[eax\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f a8 00 20 00 00 02[ ]*vpcmpleb k5,zmm6,ZMMWORD PTR \[eax\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 01[ ]*vpcmpltb k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 04[ ]*vpcmpneqb k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 06[ ]*vpcmpnleb k5,zmm6,zmm5
@@ -794,6 +796,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f aa c0 df ff ff 7b[ ]*vpcmpw k5,zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 00[ ]*vpcmpeqw k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 02[ ]*vpcmplew k5,zmm6,zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f 68 7f 02[ ]*vpcmplew k5,zmm6,ZMMWORD PTR \[eax\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f a8 00 20 00 00 02[ ]*vpcmplew k5,zmm6,ZMMWORD PTR \[eax\+0x2000\]
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 01[ ]*vpcmpltw k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 04[ ]*vpcmpneqw k5,zmm6,zmm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 06[ ]*vpcmpnlew k5,zmm6,zmm5
diff --git a/gas/testsuite/gas/i386/avx512bw.d b/gas/testsuite/gas/i386/avx512bw.d
index 6c65c9e..51967bc 100644
--- a/gas/testsuite/gas/i386/avx512bw.d
+++ b/gas/testsuite/gas/i386/avx512bw.d
@@ -779,6 +779,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f aa c0 df ff ff 7b[ ]*vpcmpb \$0x7b,-0x2040\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 00[ ]*vpcmpeqb %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 02[ ]*vpcmpleb %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f 68 7f 02[ ]*vpcmpleb 0x1fc0\(%eax\),%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f a8 00 20 00 00 02[ ]*vpcmpleb 0x2000\(%eax\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 01[ ]*vpcmpltb %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 04[ ]*vpcmpneqb %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 48 3f ed 06[ ]*vpcmpnleb %zmm5,%zmm6,%k5
@@ -794,6 +796,8 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f aa c0 df ff ff 7b[ ]*vpcmpw \$0x7b,-0x2040\(%edx\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 00[ ]*vpcmpeqw %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 02[ ]*vpcmplew %zmm5,%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f 68 7f 02[ ]*vpcmplew 0x1fc0\(%eax\),%zmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f a8 00 20 00 00 02[ ]*vpcmplew 0x2000\(%eax\),%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 01[ ]*vpcmpltw %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 04[ ]*vpcmpneqw %zmm5,%zmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 48 3f ed 06[ ]*vpcmpnlew %zmm5,%zmm6,%k5
diff --git a/gas/testsuite/gas/i386/avx512bw.s b/gas/testsuite/gas/i386/avx512bw.s
index 82161d1..3101cfc 100644
--- a/gas/testsuite/gas/i386/avx512bw.s
+++ b/gas/testsuite/gas/i386/avx512bw.s
@@ -773,6 +773,8 @@ _start:
vpcmpb $123, -8256(%edx), %zmm6, %k5 # AVX512BW
vpcmpb $0, %zmm5, %zmm6, %k5 # AVX512BW
vpcmpleb %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmpleb 0x1fc0(%eax), %zmm6, %k5 # AVX512{BW,VL} Disp8
+ vpcmpleb 0x2000(%eax), %zmm6, %k5 # AVX512{BW,VL}
vpcmpltb %zmm5, %zmm6, %k5 # AVX512BW
vpcmpneqb %zmm5, %zmm6, %k5 # AVX512BW
vpcmpnleb %zmm5, %zmm6, %k5 # AVX512BW
@@ -788,6 +790,8 @@ _start:
vpcmpw $123, -8256(%edx), %zmm6, %k5 # AVX512BW
vpcmpw $0, %zmm5, %zmm6, %k5 # AVX512BW
vpcmplew %zmm5, %zmm6, %k5 # AVX512BW
+ vpcmplew 0x1fc0(%eax), %zmm6, %k5 # AVX512{BW,VL} Disp8
+ vpcmplew 0x2000(%eax), %zmm6, %k5 # AVX512{BW,VL}
vpcmpltw %zmm5, %zmm6, %k5 # AVX512BW
vpcmpneqw %zmm5, %zmm6, %k5 # AVX512BW
vpcmpnlew %zmm5, %zmm6, %k5 # AVX512BW
diff --git a/gas/testsuite/gas/i386/avx512bw_vl-intel.d b/gas/testsuite/gas/i386/avx512bw_vl-intel.d
index d4672e7..3d26879 100644
--- a/gas/testsuite/gas/i386/avx512bw_vl-intel.d
+++ b/gas/testsuite/gas/i386/avx512bw_vl-intel.d
@@ -1274,7 +1274,11 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 00[ ]*vpcmpeqb k5,xmm6,xmm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 00[ ]*vpcmpeqb k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 02[ ]*vpcmpleb k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f 68 7f 02[ ]*vpcmpleb k5,xmm6,XMMWORD PTR \[eax\+0x7f0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f a8 00 08 00 00 02[ ]*vpcmpleb k5,xmm6,XMMWORD PTR \[eax\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 02[ ]*vpcmpleb k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f 68 7f 02[ ]*vpcmpleb k5,ymm6,YMMWORD PTR \[eax\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f a8 00 10 00 00 02[ ]*vpcmpleb k5,ymm6,YMMWORD PTR \[eax\+0x1000\]
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 01[ ]*vpcmpltb k5,xmm6,xmm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 01[ ]*vpcmpltb k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 04[ ]*vpcmpneqb k5,xmm6,xmm5
@@ -1302,7 +1306,11 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 00[ ]*vpcmpeqw k5,xmm6,xmm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 00[ ]*vpcmpeqw k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 02[ ]*vpcmplew k5,xmm6,xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f 68 7f 02[ ]*vpcmplew k5,xmm6,XMMWORD PTR \[eax\+0x7f0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f a8 00 08 00 00 02[ ]*vpcmplew k5,xmm6,XMMWORD PTR \[eax\+0x800\]
[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 02[ ]*vpcmplew k5,ymm6,ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f 68 7f 02[ ]*vpcmplew k5,ymm6,YMMWORD PTR \[eax\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f a8 00 10 00 00 02[ ]*vpcmplew k5,ymm6,YMMWORD PTR \[eax\+0x1000\]
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 01[ ]*vpcmpltw k5,xmm6,xmm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 01[ ]*vpcmpltw k5,ymm6,ymm5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 04[ ]*vpcmpneqw k5,xmm6,xmm5
diff --git a/gas/testsuite/gas/i386/avx512bw_vl.d b/gas/testsuite/gas/i386/avx512bw_vl.d
index 32a949c..0b9815e 100644
--- a/gas/testsuite/gas/i386/avx512bw_vl.d
+++ b/gas/testsuite/gas/i386/avx512bw_vl.d
@@ -1274,7 +1274,11 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 00[ ]*vpcmpeqb %xmm5,%xmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 00[ ]*vpcmpeqb %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 02[ ]*vpcmpleb %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f 68 7f 02[ ]*vpcmpleb 0x7f0\(%eax\),%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f a8 00 08 00 00 02[ ]*vpcmpleb 0x800\(%eax\),%xmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 02[ ]*vpcmpleb %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f 68 7f 02[ ]*vpcmpleb 0xfe0\(%eax\),%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f a8 00 10 00 00 02[ ]*vpcmpleb 0x1000\(%eax\),%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 01[ ]*vpcmpltb %xmm5,%xmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 28 3f ed 01[ ]*vpcmpltb %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 3f ed 04[ ]*vpcmpneqb %xmm5,%xmm6,%k5
@@ -1302,7 +1306,11 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 00[ ]*vpcmpeqw %xmm5,%xmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 00[ ]*vpcmpeqw %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 02[ ]*vpcmplew %xmm5,%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f 68 7f 02[ ]*vpcmplew 0x7f0\(%eax\),%xmm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f a8 00 08 00 00 02[ ]*vpcmplew 0x800\(%eax\),%xmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 02[ ]*vpcmplew %ymm5,%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f 68 7f 02[ ]*vpcmplew 0xfe0\(%eax\),%ymm6,%k5
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f a8 00 10 00 00 02[ ]*vpcmplew 0x1000\(%eax\),%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 01[ ]*vpcmpltw %xmm5,%xmm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 28 3f ed 01[ ]*vpcmpltw %ymm5,%ymm6,%k5
[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 3f ed 04[ ]*vpcmpneqw %xmm5,%xmm6,%k5
diff --git a/gas/testsuite/gas/i386/avx512bw_vl.s b/gas/testsuite/gas/i386/avx512bw_vl.s
index dabe5e7..14e9882 100644
--- a/gas/testsuite/gas/i386/avx512bw_vl.s
+++ b/gas/testsuite/gas/i386/avx512bw_vl.s
@@ -1268,7 +1268,11 @@ _start:
vpcmpb $0, %xmm5, %xmm6, %k5 # AVX512{BW,VL}
vpcmpb $0, %ymm5, %ymm6, %k5 # AVX512{BW,VL}
vpcmpleb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmpleb 0x7f0(%eax), %xmm6, %k5 # AVX512{BW,VL} Disp8
+ vpcmpleb 0x800(%eax), %xmm6, %k5 # AVX512{BW,VL}
vpcmpleb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmpleb 0xfe0(%eax), %ymm6, %k5 # AVX512{BW,VL} Disp8
+ vpcmpleb 0x1000(%eax), %ymm6, %k5 # AVX512{BW,VL}
vpcmpltb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
vpcmpltb %ymm5, %ymm6, %k5 # AVX512{BW,VL}
vpcmpneqb %xmm5, %xmm6, %k5 # AVX512{BW,VL}
@@ -1296,7 +1300,11 @@ _start:
vpcmpw $0, %xmm5, %xmm6, %k5 # AVX512{BW,VL}
vpcmpw $0, %ymm5, %ymm6, %k5 # AVX512{BW,VL}
vpcmplew %xmm5, %xmm6, %k5 # AVX512{BW,VL}
+ vpcmplew 0x7f0(%eax), %xmm6, %k5 # AVX512{BW,VL} Disp8
+ vpcmplew 0x800(%eax), %xmm6, %k5 # AVX512{BW,VL}
vpcmplew %ymm5, %ymm6, %k5 # AVX512{BW,VL}
+ vpcmplew 0xfe0(%eax), %ymm6, %k5 # AVX512{BW,VL} Disp8
+ vpcmplew 0x1000(%eax), %ymm6, %k5 # AVX512{BW,VL}
vpcmpltw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
vpcmpltw %ymm5, %ymm6, %k5 # AVX512{BW,VL}
vpcmpneqw %xmm5, %xmm6, %k5 # AVX512{BW,VL}
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 24d1101..e6aa05c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2018-01-10 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
+ vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
+ vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
+ vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
+ vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
+ Disp8MemShift of AVX512VL forms.
+ * i386-tbl.h: Re-generate.
+
2018-01-09 Jim Wilson <jimw@sifive.com>
* riscv-dis.c (maybe_print_address): If base_reg is zero,
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 464add0..b8677a9 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5457,44 +5457,44 @@ vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexV
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpeqb, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpleb, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpltb, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpneqb, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnleb, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnltb, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpequb, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpleub, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpltub, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnequb, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnleub, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnltub, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
@@ -5506,44 +5506,44 @@ vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexV
vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpeqw, 3, 0x663F, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmplew, 3, 0x663F, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpltw, 3, 0x663F, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpneqw, 3, 0x663F, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnlew, 3, 0x663F, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnltw, 3, 0x663F, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpequw, 3, 0x663E, 0, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpleuw, 3, 0x663E, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpltuw, 3, 0x663E, 1, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnequw, 3, 0x663E, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnleuw, 3, 0x663E, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegMask }
-vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
-vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
+vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegMask }
+vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegYMM|YMMword|Unspecified|BaseIndex, RegYMM, RegMask }
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegZMM }
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=3|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, ZMMword|Unspecified|BaseIndex, RegZMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 1c402f5..9decd29 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -45444,7 +45444,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -45464,7 +45464,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -46084,7 +46084,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -46104,7 +46104,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -90721,7 +90721,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -90741,7 +90741,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -90781,7 +90781,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -90801,7 +90801,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -90841,7 +90841,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -90861,7 +90861,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -90901,7 +90901,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -90921,7 +90921,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -90961,7 +90961,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -90981,7 +90981,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91090,7 +91090,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91110,7 +91110,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91150,7 +91150,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91170,7 +91170,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91210,7 +91210,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91230,7 +91230,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91270,7 +91270,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91290,7 +91290,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91330,7 +91330,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91350,7 +91350,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91390,7 +91390,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91410,7 +91410,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 1, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91519,7 +91519,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91539,7 +91539,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91579,7 +91579,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91599,7 +91599,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91639,7 +91639,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91659,7 +91659,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91699,7 +91699,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91719,7 +91719,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91759,7 +91759,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91779,7 +91779,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91888,7 +91888,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91908,7 +91908,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -91948,7 +91948,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -91968,7 +91968,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -92008,7 +92008,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -92028,7 +92028,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -92068,7 +92068,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -92088,7 +92088,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -92128,7 +92128,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -92148,7 +92148,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -92188,7 +92188,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 4, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -92208,7 +92208,7 @@ const insn_template i386_optab[] =
0, 0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 6, 0, 0, 0,
+ 0, 0, 1, 2, 2, 0, 0, 0, 0, 0, 3, 2, 0, 0, 0, 0, 5, 0, 0, 0,
0, 0, 0, 0, 0 },
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,