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[binutils-gdb] RISC-V: Add 2 missing privileged registers.
- From: Jim Wilson <wilson at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 4 Jan 2018 22:18:45 -0000
- Subject: [binutils-gdb] RISC-V: Add 2 missing privileged registers.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=645a2c5b46e18013ac9cb16b66ba7b6b97cd01c5
commit 645a2c5b46e18013ac9cb16b66ba7b6b97cd01c5
Author: Jim Wilson <jimw@sifive.com>
Date: Thu Jan 4 14:17:53 2018 -0800
RISC-V: Add 2 missing privileged registers.
gas/
* testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
* testsuite/gas/riscv/priv-reg.d: Likewise.
include/
* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename
DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL.
(CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry.
Add alias to map mbadaddr to CSR_MTVAL.
Diff:
---
gas/ChangeLog | 5 ++++
gas/testsuite/gas/riscv/priv-reg.d | 50 ++++++++++++++++++++------------------
gas/testsuite/gas/riscv/priv-reg.s | 2 ++
include/ChangeLog | 7 ++++++
include/opcode/riscv-opc.h | 12 ++++++---
5 files changed, 48 insertions(+), 28 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index cf0ac65..85ced2f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-04 Jim Wilson <jimw@sifive.com>
+
+ * testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
+ * testsuite/gas/riscv/priv-reg.d: Likewise.
+
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
index 2a650df..9ec5d97 100644
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ b/gas/testsuite/gas/riscv/priv-reg.d
@@ -90,7 +90,7 @@ Disassembly of section .text:
[ ]+140:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
[ ]+144:[ ]+14102573[ ]+csrr[ ]+a0,sepc
[ ]+148:[ ]+14202573[ ]+csrr[ ]+a0,scause
-[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,sbadaddr
+[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,stval
[ ]+150:[ ]+14402573[ ]+csrr[ ]+a0,sip
[ ]+154:[ ]+18002573[ ]+csrr[ ]+a0,satp
[ ]+158:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
@@ -116,7 +116,7 @@ Disassembly of section .text:
[ ]+1a8:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
[ ]+1ac:[ ]+34102573[ ]+csrr[ ]+a0,mepc
[ ]+1b0:[ ]+34202573[ ]+csrr[ ]+a0,mcause
-[ ]+1b4:[ ]+34302573[ ]+csrr[ ]+a0,mbadaddr
+[ ]+1b4:[ ]+34302573[ ]+csrr[ ]+a0,mtval
[ ]+1b8:[ ]+34402573[ ]+csrr[ ]+a0,mip
[ ]+1bc:[ ]+38002573[ ]+csrr[ ]+a0,mbase
[ ]+1c0:[ ]+38102573[ ]+csrr[ ]+a0,mbound
@@ -227,25 +227,27 @@ Disassembly of section .text:
[ ]+364:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
[ ]+368:[ ]+04302573[ ]+csrr[ ]+a0,utval
[ ]+36c:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
-[ ]+370:[ ]+18002573[ ]+csrr[ ]+a0,satp
-[ ]+374:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
-[ ]+378:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
-[ ]+37c:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
-[ ]+380:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
-[ ]+384:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
-[ ]+388:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
-[ ]+38c:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
-[ ]+390:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
-[ ]+394:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
-[ ]+398:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
-[ ]+39c:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
-[ ]+3a0:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
-[ ]+3a4:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
-[ ]+3a8:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
-[ ]+3ac:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
-[ ]+3b0:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
-[ ]+3b4:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
-[ ]+3b8:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
-[ ]+3bc:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
-[ ]+3c0:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
-[ ]+3c4:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
+[ ]+370:[ ]+14302573[ ]+csrr[ ]+a0,stval
+[ ]+374:[ ]+18002573[ ]+csrr[ ]+a0,satp
+[ ]+378:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
+[ ]+37c:[ ]+34302573[ ]+csrr[ ]+a0,mtval
+[ ]+380:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
+[ ]+384:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
+[ ]+388:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
+[ ]+38c:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
+[ ]+390:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
+[ ]+394:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
+[ ]+398:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
+[ ]+39c:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
+[ ]+3a0:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
+[ ]+3a4:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
+[ ]+3a8:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
+[ ]+3ac:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
+[ ]+3b0:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
+[ ]+3b4:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
+[ ]+3b8:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
+[ ]+3bc:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
+[ ]+3c0:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
+[ ]+3c4:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
+[ ]+3c8:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
+[ ]+3cc:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
index 4774f36..72d97f9 100644
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -241,9 +241,11 @@
csr utval
csr scounteren
+ csr stval
csr satp
csr mcounteren
+ csr mtval
csr pmpcfg0
csr pmpcfg1
diff --git a/include/ChangeLog b/include/ChangeLog
index 2b8e7c5..3105a03 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2018-01-04 Jim Wilson <jimw@sifive.com>
+
+ * opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename
+ DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL.
+ (CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry.
+ Add alias to map mbadaddr to CSR_MTVAL.
+
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 64635e1..f966fb6 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -651,7 +651,7 @@
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
-#define CSR_SBADADDR 0x143
+#define CSR_STVAL 0x143
#define CSR_SIP 0x144
#define CSR_SATP 0x180
#define CSR_MVENDORID 0xf11
@@ -668,7 +668,7 @@
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
-#define CSR_MBADADDR 0x343
+#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
@@ -1192,7 +1192,7 @@ DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
DECLARE_CSR(sscratch, CSR_SSCRATCH)
DECLARE_CSR(sepc, CSR_SEPC)
DECLARE_CSR(scause, CSR_SCAUSE)
-DECLARE_CSR(sbadaddr, CSR_SBADADDR)
+DECLARE_CSR(stval, CSR_STVAL)
DECLARE_CSR(sip, CSR_SIP)
DECLARE_CSR(satp, CSR_SATP)
DECLARE_CSR(mvendorid, CSR_MVENDORID)
@@ -1209,7 +1209,7 @@ DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
DECLARE_CSR(mscratch, CSR_MSCRATCH)
DECLARE_CSR(mepc, CSR_MEPC)
DECLARE_CSR(mcause, CSR_MCAUSE)
-DECLARE_CSR(mbadaddr, CSR_MBADADDR)
+DECLARE_CSR(mtval, CSR_MTVAL)
DECLARE_CSR(mip, CSR_MIP)
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
@@ -1353,8 +1353,12 @@ DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
#ifdef DECLARE_CSR_ALIAS
/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL)
+/* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */
+DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL)
/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */
DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
+/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
+DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)