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[binutils-gdb] Add support for AArch64 system register names IP0, IP1, FP and LR.
- From: Nick Clifton <nickc at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 7 Jun 2017 12:35:15 -0000
- Subject: [binutils-gdb] Add support for AArch64 system register names IP0, IP1, FP and LR.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=62e20ed45e3da5f3ba695e4ee109317668180fe6
commit 62e20ed45e3da5f3ba695e4ee109317668180fe6
Author: Michael Collison <michael.collison@arm.com>
Date: Wed Jun 7 13:34:34 2017 +0100
Add support for AArch64 system register names IP0, IP1, FP and LR.
* config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
IP1, FP, and LR as register aliases of register 16, 17, 29
and 30 respectively.
* testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
prohibiting register 'lr' which is now an alias.
* testsuite/gas/aarch64/diagnostic.s: Remove instruction
utilizing register 'lr' which is now an alias.
Diff:
---
gas/ChangeLog | 10 ++++++++++
gas/config/tc-aarch64.c | 5 +++++
gas/testsuite/gas/aarch64/diagnostic.l | 1 -
gas/testsuite/gas/aarch64/diagnostic.s | 2 +-
4 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d77052a..a1853a4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2017-06-07 Michael Collison <michael.collison@arm.com>
+
+ * config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
+ IP1, FP, and LR as register aliases of register 16, 17, 29
+ and 30 respectively.
+ * testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
+ prohibiting register 'lr' which is now an alias.
+ * testsuite/gas/aarch64/diagnostic.s: Remove instruction
+ utilizing register 'lr' which is now an alias.
+
2017-06-06 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index cdb2903..be01bdd 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6797,6 +6797,11 @@ static const reg_entry reg_names[] = {
REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
+ REGDEF (ip0, 16, R_64), REGDEF (IP0, 16, R_64),
+ REGDEF (ip1, 17, R_64), REGDEF (IP1, 17, R_64),
+ REGDEF (fp, 29, R_64), REGDEF (FP, 29, R_64),
+ REGDEF (lr, 30, R_64), REGDEF (LR, 30, R_64),
+
/* Floating-point single precision registers. */
REGSET (s, FP_S), REGSET (S, FP_S),
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 6a2563e..b749d2e 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -98,7 +98,6 @@
[^:]*:100: Error: operand 3 must be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
[^:]*:101: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
[^:]*:102: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
-[^:]*:105: Error: operand 1 must be an integer register -- `ret lr'
[^:]*:106: Error: operand 1 must be an integer register -- `ret kk'
[^:]*:107: Error: immediate operand required at operand 1 -- `clrex x0'
[^:]*:108: Error: immediate operand required at operand 1 -- `clrex w0'
diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s
index d2b9244..09126e6 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.s
+++ b/gas/testsuite/gas/aarch64/diagnostic.s
@@ -102,7 +102,7 @@
cset w0, nv
# test diagnostic info on optional operand
- ret lr
+
ret kk
clrex x0
clrex w0