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[binutils-gdb] RISC-V: Fix disassemble for c.li, c.andi and c.addiw
- From: Palmer Dabbelt <palmer at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 4 May 2017 10:21:15 -0000
- Subject: [binutils-gdb] RISC-V: Fix disassemble for c.li, c.andi and c.addiw
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f91d48deb29d9e6f4b530f586db0140943ed0d83
commit f91d48deb29d9e6f4b530f586db0140943ed0d83
Author: Kito Cheng <kito.cheng@gmail.com>
Date: Wed Apr 5 20:58:28 2017 +0800
RISC-V: Fix disassemble for c.li, c.andi and c.addiw
ChangeLog
2017-05-03 Kito Cheng <kito.cheng@gmail.com>
* riscv-dis.c (print_insn_args): Handle 'Co' operands.
Diff:
---
opcodes/ChangeLog | 4 ++++
opcodes/riscv-dis.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 355a162..ea0902f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-03 Kito Cheng <kito.cheng@gmail.com>
+
+ * riscv-dis.c (print_insn_args): Handle 'Co' operands.
+
2017-05-01 Michael Clark <michaeljclark@mac.com>
* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d70..bb53463 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'i':
print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
break;
+ case 'o':
case 'j':
print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
break;