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[binutils-gdb] Sanitize RISC-V GAS help text, documentation
- From: Palmer Dabbelt <palmer at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 22 Mar 2017 22:48:24 -0000
- Subject: [binutils-gdb] Sanitize RISC-V GAS help text, documentation
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=19683c0408d66d9e48085fd5af009ad7d83aa3cd
commit 19683c0408d66d9e48085fd5af009ad7d83aa3cd
Author: Palmer Dabbelt <palmer@dabbelt.com>
Date: Tue Mar 21 08:36:44 2017 -0700
Sanitize RISC-V GAS help text, documentation
It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments. I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
Diff:
---
gas/ChangeLog | 7 +++++++
gas/config/tc-riscv.c | 9 ++-------
gas/doc/c-riscv.texi | 8 ++++++++
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 75f6adc..5fda819 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
+
+ * config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
+ -msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
+ print an invalid default ISA string.
+ * doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
+
2017-03-22 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_relax_frag): Change fx_size of the
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ff6d737..68b28f7 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2475,15 +2475,10 @@ md_show_usage (FILE *stream)
{
fprintf (stream, _("\
RISC-V options:\n\
- -m32 assemble RV32 code\n\
- -m64 assemble RV64 code (default)\n\
-fpic generate position-independent code\n\
-fno-pic don't generate position-independent code (default)\n\
- -msoft-float don't use F registers for floating-point values\n\
- -mhard-float use F registers for floating-point values (default)\n\
- -mno-rvc disable the C extension for compressed instructions (default)\n\
- -mrvc enable the C extension for compressed instructions\n\
- -march=ISA set the RISC-V architecture, RV64IMAFD by default\n\
+ -march=ISA set the RISC-V architecture\n\
+ -mabi=ABI set the RISC-V ABI\n\
"));
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 8915db4..01b9931 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -26,6 +26,14 @@ The following table lists all available RISC-V specific options
@c man begin OPTIONS
@table @gcctabopt
+@cindex @samp{-fpic} option, RISC-V
+@item -fpic
+Generate position-independent code
+
+@cindex @samp{-fno-pic} option, RISC-V
+@item -fno-pic
+Don't generate position-independent code (default)
+
@cindex @samp{-march=ISA} option, RISC-V
@item -march=ISA
Select the base isa, as specified by ISA. For example -march=rv32ima.