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[binutils-gdb] Fix spelling mistakes and typos in the GAS sources.
- From: Nick Clifton <nickc at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 23 Jan 2017 15:24:04 -0000
- Subject: [binutils-gdb] Fix spelling mistakes and typos in the GAS sources.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=33eaf5de31b248f84ae108cf0cf4e1664db9ee51
commit 33eaf5de31b248f84ae108cf0cf4e1664db9ee51
Author: Nick Clifton <nickc@redhat.com>
Date: Mon Jan 23 15:23:07 2017 +0000
Fix spelling mistakes and typos in the GAS sources.
PR gas/21072
* asintl.h: Fix spelling mistakes and typos.
* atof-generic.c: Likewise.
* bit_fix.h: Likewise.
* config/atof-ieee.c: Likewise.
* config/bfin-defs.h: Likewise.
* config/bfin-parse.y: Likewise.
* config/obj-coff-seh.h: Likewise.
* config/obj-coff.c: Likewise.
* config/obj-evax.c: Likewise.
* config/obj-macho.c: Likewise.
* config/rx-parse.y: Likewise.
* config/tc-aarch64.c: Likewise.
* config/tc-alpha.c: Likewise.
* config/tc-arc.c: Likewise.
* config/tc-arm.c: Likewise.
* config/tc-avr.c: Likewise.
* config/tc-bfin.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-cris.c: Likewise.
* config/tc-crx.c: Likewise.
* config/tc-d10v.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-dlx.c: Likewise.
* config/tc-epiphany.c: Likewise.
* config/tc-frv.c: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i370.c: Likewise.
* config/tc-i386-intel.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-i960.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mep.c: Likewise.
* config/tc-mep.h: Likewise.
* config/tc-metag.c: Likewise.
* config/tc-microblaze.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-mmix.c: Likewise.
* config/tc-mn10200.c: Likewise.
* config/tc-mn10300.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-msp430.h: Likewise.
* config/tc-nds32.c: Likewise.
* config/tc-nds32.h: Likewise.
* config/tc-nios2.c: Likewise.
* config/tc-nios2.h: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-pdp11.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-pru.c: Likewise.
* config/tc-rx.c: Likewise.
* config/tc-s390.c: Likewise.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sh64.c: Likewise.
* config/tc-sparc.c: Likewise.
* config/tc-tic4x.c: Likewise.
* config/tc-tic54x.c: Likewise.
* config/tc-v850.c: Likewise.
* config/tc-vax.c: Likewise.
* config/tc-visium.c: Likewise.
* config/tc-xgate.c: Likewise.
* config/tc-xtensa.c: Likewise.
* config/tc-z80.c: Likewise.
* config/tc-z8k.c: Likewise.
* config/te-vms.c: Likewise.
* config/xtensa-relax.c: Likewise.
* doc/as.texinfo: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-hppa.texi: Likewise.
* doc/c-i370.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-nds32.texi: Likewise.
* doc/c-ns32k.texi: Likewise.
* doc/c-riscv.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-s390.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-tilegx.texi: Likewise.
* doc/c-tilepro.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-xgate.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* dwarf2dbg.c: Likewise.
* ecoff.c: Likewise.
* itbl-ops.c: Likewise.
* listing.c: Likewise.
* macro.c: Likewise.
* po/gas.pot: Likewise.
* read.c: Likewise.
* struc-symbol.h: Likewise.
* symbols.h: Likewise.
* testsuite/gas/arc/relocs-errors.err: Likewise.
* write.c: Likewise.
Diff:
---
gas/ChangeLog | 106 ++++++++++++++++++++++++++++++++
gas/asintl.h | 2 +-
gas/atof-generic.c | 2 +-
gas/bit_fix.h | 2 +-
gas/config/atof-ieee.c | 2 +-
gas/config/bfin-defs.h | 2 +-
gas/config/bfin-parse.y | 6 +-
gas/config/obj-coff-seh.h | 2 +-
gas/config/obj-coff.c | 10 +--
gas/config/obj-evax.c | 8 +--
gas/config/obj-macho.c | 8 +--
gas/config/rx-parse.y | 2 +-
gas/config/tc-aarch64.c | 30 ++++-----
gas/config/tc-alpha.c | 6 +-
gas/config/tc-arc.c | 20 +++---
gas/config/tc-arm.c | 22 +++----
gas/config/tc-avr.c | 12 ++--
gas/config/tc-bfin.c | 4 +-
gas/config/tc-cr16.c | 26 ++++----
gas/config/tc-cris.c | 2 +-
gas/config/tc-crx.c | 30 ++++-----
gas/config/tc-d10v.c | 2 +-
gas/config/tc-d30v.c | 8 +--
gas/config/tc-dlx.c | 2 +-
gas/config/tc-epiphany.c | 4 +-
gas/config/tc-frv.c | 2 +-
gas/config/tc-hppa.c | 2 +-
gas/config/tc-i370.c | 30 ++++-----
gas/config/tc-i386-intel.c | 2 +-
gas/config/tc-i386.c | 16 ++---
gas/config/tc-i960.c | 8 +--
gas/config/tc-ia64.c | 8 +--
gas/config/tc-m32r.c | 8 +--
gas/config/tc-m68hc11.c | 10 +--
gas/config/tc-m68k.c | 20 +++---
gas/config/tc-mcore.c | 10 +--
gas/config/tc-mep.c | 16 ++---
gas/config/tc-mep.h | 2 +-
gas/config/tc-metag.c | 6 +-
gas/config/tc-microblaze.c | 4 +-
gas/config/tc-mips.c | 10 +--
gas/config/tc-mmix.c | 2 +-
gas/config/tc-mn10200.c | 2 +-
gas/config/tc-mn10300.c | 4 +-
gas/config/tc-msp430.c | 22 +++----
gas/config/tc-msp430.h | 2 +-
gas/config/tc-nds32.c | 60 +++++++++---------
gas/config/tc-nds32.h | 4 +-
gas/config/tc-nios2.c | 6 +-
gas/config/tc-nios2.h | 2 +-
gas/config/tc-ns32k.c | 26 ++++----
gas/config/tc-pdp11.c | 12 ++--
gas/config/tc-ppc.c | 12 ++--
gas/config/tc-pru.c | 2 +-
gas/config/tc-rx.c | 4 +-
gas/config/tc-s390.c | 14 ++---
gas/config/tc-score.c | 70 ++++++++++-----------
gas/config/tc-score7.c | 22 +++----
gas/config/tc-sh.c | 6 +-
gas/config/tc-sh64.c | 2 +-
gas/config/tc-sparc.c | 4 +-
gas/config/tc-tic4x.c | 4 +-
gas/config/tc-tic54x.c | 10 +--
gas/config/tc-v850.c | 14 ++---
gas/config/tc-vax.c | 8 +--
gas/config/tc-visium.c | 6 +-
gas/config/tc-xgate.c | 6 +-
gas/config/tc-xtensa.c | 4 +-
gas/config/tc-z80.c | 6 +-
gas/config/tc-z8k.c | 2 +-
gas/config/te-vms.c | 2 +-
gas/config/xtensa-relax.c | 8 +--
gas/doc/as.texinfo | 10 +--
gas/doc/c-arm.texi | 6 +-
gas/doc/c-hppa.texi | 2 +-
gas/doc/c-i370.texi | 2 +-
gas/doc/c-i386.texi | 2 +-
gas/doc/c-m32r.texi | 8 +--
gas/doc/c-m68k.texi | 2 +-
gas/doc/c-mmix.texi | 2 +-
gas/doc/c-msp430.texi | 2 +-
gas/doc/c-nds32.texi | 2 +-
gas/doc/c-ns32k.texi | 2 +-
gas/doc/c-riscv.texi | 2 +-
gas/doc/c-rx.texi | 2 +-
gas/doc/c-s390.texi | 6 +-
gas/doc/c-tic6x.texi | 2 +-
gas/doc/c-tilegx.texi | 2 +-
gas/doc/c-tilepro.texi | 2 +-
gas/doc/c-v850.texi | 8 +--
gas/doc/c-xgate.texi | 2 +-
gas/doc/c-xtensa.texi | 2 +-
gas/dwarf2dbg.c | 2 +-
gas/ecoff.c | 4 +-
gas/itbl-ops.c | 4 +-
gas/listing.c | 2 +-
gas/macro.c | 4 +-
gas/po/gas.pot | 2 +-
gas/read.c | 4 +-
gas/struc-symbol.h | 4 +-
gas/symbols.h | 2 +-
gas/testsuite/gas/arc/relocs-errors.err | 6 +-
gas/write.c | 2 +-
103 files changed, 516 insertions(+), 410 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2fb2a63..a248b24 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,109 @@
+2017-01-23 Sebastian Rasmussen <sebras@gmail.com>
+
+ PR gas/21072
+ * asintl.h: Fix spelling mistakes and typos.
+ * atof-generic.c: Likewise.
+ * bit_fix.h: Likewise.
+ * config/atof-ieee.c: Likewise.
+ * config/bfin-defs.h: Likewise.
+ * config/bfin-parse.y: Likewise.
+ * config/obj-coff-seh.h: Likewise.
+ * config/obj-coff.c: Likewise.
+ * config/obj-evax.c: Likewise.
+ * config/obj-macho.c: Likewise.
+ * config/rx-parse.y: Likewise.
+ * config/tc-aarch64.c: Likewise.
+ * config/tc-alpha.c: Likewise.
+ * config/tc-arc.c: Likewise.
+ * config/tc-arm.c: Likewise.
+ * config/tc-avr.c: Likewise.
+ * config/tc-bfin.c: Likewise.
+ * config/tc-cr16.c: Likewise.
+ * config/tc-cris.c: Likewise.
+ * config/tc-crx.c: Likewise.
+ * config/tc-d10v.c: Likewise.
+ * config/tc-d30v.c: Likewise.
+ * config/tc-dlx.c: Likewise.
+ * config/tc-epiphany.c: Likewise.
+ * config/tc-frv.c: Likewise.
+ * config/tc-hppa.c: Likewise.
+ * config/tc-i370.c: Likewise.
+ * config/tc-i386-intel.c: Likewise.
+ * config/tc-i386.c: Likewise.
+ * config/tc-i960.c: Likewise.
+ * config/tc-ia64.c: Likewise.
+ * config/tc-m32r.c: Likewise.
+ * config/tc-m68hc11.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-mcore.c: Likewise.
+ * config/tc-mep.c: Likewise.
+ * config/tc-mep.h: Likewise.
+ * config/tc-metag.c: Likewise.
+ * config/tc-microblaze.c: Likewise.
+ * config/tc-mips.c: Likewise.
+ * config/tc-mmix.c: Likewise.
+ * config/tc-mn10200.c: Likewise.
+ * config/tc-mn10300.c: Likewise.
+ * config/tc-msp430.c: Likewise.
+ * config/tc-msp430.h: Likewise.
+ * config/tc-nds32.c: Likewise.
+ * config/tc-nds32.h: Likewise.
+ * config/tc-nios2.c: Likewise.
+ * config/tc-nios2.h: Likewise.
+ * config/tc-ns32k.c: Likewise.
+ * config/tc-pdp11.c: Likewise.
+ * config/tc-ppc.c: Likewise.
+ * config/tc-pru.c: Likewise.
+ * config/tc-rx.c: Likewise.
+ * config/tc-s390.c: Likewise.
+ * config/tc-score.c: Likewise.
+ * config/tc-score7.c: Likewise.
+ * config/tc-sh.c: Likewise.
+ * config/tc-sh64.c: Likewise.
+ * config/tc-sparc.c: Likewise.
+ * config/tc-tic4x.c: Likewise.
+ * config/tc-tic54x.c: Likewise.
+ * config/tc-v850.c: Likewise.
+ * config/tc-vax.c: Likewise.
+ * config/tc-visium.c: Likewise.
+ * config/tc-xgate.c: Likewise.
+ * config/tc-xtensa.c: Likewise.
+ * config/tc-z80.c: Likewise.
+ * config/tc-z8k.c: Likewise.
+ * config/te-vms.c: Likewise.
+ * config/xtensa-relax.c: Likewise.
+ * doc/as.texinfo: Likewise.
+ * doc/c-arm.texi: Likewise.
+ * doc/c-hppa.texi: Likewise.
+ * doc/c-i370.texi: Likewise.
+ * doc/c-i386.texi: Likewise.
+ * doc/c-m32r.texi: Likewise.
+ * doc/c-m68k.texi: Likewise.
+ * doc/c-mmix.texi: Likewise.
+ * doc/c-msp430.texi: Likewise.
+ * doc/c-nds32.texi: Likewise.
+ * doc/c-ns32k.texi: Likewise.
+ * doc/c-riscv.texi: Likewise.
+ * doc/c-rx.texi: Likewise.
+ * doc/c-s390.texi: Likewise.
+ * doc/c-tic6x.texi: Likewise.
+ * doc/c-tilegx.texi: Likewise.
+ * doc/c-tilepro.texi: Likewise.
+ * doc/c-v850.texi: Likewise.
+ * doc/c-xgate.texi: Likewise.
+ * doc/c-xtensa.texi: Likewise.
+ * dwarf2dbg.c: Likewise.
+ * ecoff.c: Likewise.
+ * itbl-ops.c: Likewise.
+ * listing.c: Likewise.
+ * macro.c: Likewise.
+ * po/gas.pot: Likewise.
+ * read.c: Likewise.
+ * struc-symbol.h: Likewise.
+ * symbols.h: Likewise.
+ * testsuite/gas/arc/relocs-errors.err: Likewise.
+ * write.c: Likewise.
+
2017-01-23 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
diff --git a/gas/asintl.h b/gas/asintl.h
index 6d632fb..151ac37 100644
--- a/gas/asintl.h
+++ b/gas/asintl.h
@@ -25,7 +25,7 @@
/* The Solaris version of locale.h always includes libintl.h. If we have
been configured with --disable-nls then ENABLE_NLS will not be defined
and the dummy definitions of bindtextdomain (et al) below will conflict
- with the defintions in libintl.h. So we define these values to prevent
+ with the definitions in libintl.h. So we define these values to prevent
the bogus inclusion of libintl.h. */
# define _LIBINTL_H
# define _LIBGETTEXT_H
diff --git a/gas/atof-generic.c b/gas/atof-generic.c
index ec05f0e..b5070e6 100644
--- a/gas/atof-generic.c
+++ b/gas/atof-generic.c
@@ -452,7 +452,7 @@ atof_generic (/* return pointer to just AFTER number we read. */
{
/*
- * Compute the mantssa (& exponent) of the power of 10.
+ * Compute the mantissa (& exponent) of the power of 10.
* If successful, then multiply the power of 10 by the digits
* giving return_binary_mantissa and return_binary_exponent.
*/
diff --git a/gas/bit_fix.h b/gas/bit_fix.h
index 803ee9e..afa3287 100644
--- a/gas/bit_fix.h
+++ b/gas/bit_fix.h
@@ -21,7 +21,7 @@
/* The bit_fix was implemented to support machines that need variables
to be inserted in bitfields other than 1, 2 and 4 bytes.
Furthermore it gives us a possibility to mask in bits in the symbol
- when it's fixed in the objectcode and check the symbols limits.
+ when it's fixed in the object code and check the symbols limits.
The or-mask is used to set the huffman bits in displacements for the
ns32k port.
diff --git a/gas/config/atof-ieee.c b/gas/config/atof-ieee.c
index 3f2d82b..c1ea508 100644
--- a/gas/config/atof-ieee.c
+++ b/gas/config/atof-ieee.c
@@ -766,7 +766,7 @@ ieee_md_atof (int type,
can come from the .dc.s, .dcb.s, .float or .single pseudo-ops and the
'd' type from the .dc.d, .dbc.d or .double pseudo-ops.
- The 'x' type is not implicitly recongised however, even though it can
+ The 'x' type is not implicitly recognised however, even though it can
be generated by the .dc.x and .dbc.x pseudo-ops because not all targets
can support floating point values that big. ie the target has to
explicitly allow them by putting them into FLT_CHARS. */
diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h
index 4bc6ce0..977e461 100644
--- a/gas/config/bfin-defs.h
+++ b/gas/config/bfin-defs.h
@@ -79,7 +79,7 @@ typedef enum
#define T_REG_A 0x40
/* All registers above this value don't
- belong to a usuable register group. */
+ belong to a usable register group. */
#define T_NOGROUP 0xa0
/* Flags. */
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 627382f..3484448 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -666,7 +666,7 @@ asm: asm_1 SEMICOLON
else if (is_group2 ($3) && is_group1 ($5))
$$ = gen_multi_instr_1 ($1, $5, $3);
else
- return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
+ return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instruction group");
}
else if (($3->value & 0xf800) == 0xc000)
{
@@ -675,7 +675,7 @@ asm: asm_1 SEMICOLON
else if (is_group2 ($1) && is_group1 ($5))
$$ = gen_multi_instr_1 ($3, $5, $1);
else
- return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instruction group");
}
else if (($5->value & 0xf800) == 0xc000)
{
@@ -684,7 +684,7 @@ asm: asm_1 SEMICOLON
else if (is_group2 ($1) && is_group1 ($3))
$$ = gen_multi_instr_1 ($5, $3, $1);
else
- return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instruction group");
}
else
error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
diff --git a/gas/config/obj-coff-seh.h b/gas/config/obj-coff-seh.h
index ae661c2..7ef3f80 100644
--- a/gas/config/obj-coff-seh.h
+++ b/gas/config/obj-coff-seh.h
@@ -38,7 +38,7 @@
The third version has a function entry block of BeginAddress (RVA),
EndAddress (RVA), and UnwindData (RVA). The description of the
- prologue, excepetion-handler, and additional SEH data is stored
+ prologue, exception-handler, and additional SEH data is stored
within the UNWIND_DATA field in the xdata section.
The pseudos:
diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c
index 5913b4a..7d4314c 100644
--- a/gas/config/obj-coff.c
+++ b/gas/config/obj-coff.c
@@ -929,7 +929,7 @@ obj_coff_size (int ignore ATTRIBUTE_UNUSED)
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".size pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".size pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
@@ -944,7 +944,7 @@ obj_coff_scl (int ignore ATTRIBUTE_UNUSED)
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".scl pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".scl pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
@@ -961,7 +961,7 @@ obj_coff_tag (int ignore ATTRIBUTE_UNUSED)
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".tag pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".tag pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
@@ -991,7 +991,7 @@ obj_coff_type (int ignore ATTRIBUTE_UNUSED)
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".type pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".type pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
@@ -1010,7 +1010,7 @@ obj_coff_val (int ignore ATTRIBUTE_UNUSED)
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".val pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".val pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
diff --git a/gas/config/obj-evax.c b/gas/config/obj-evax.c
index d323224..12d4837 100644
--- a/gas/config/obj-evax.c
+++ b/gas/config/obj-evax.c
@@ -216,7 +216,7 @@ evax_frob_file_before_fix (void)
/* The length is computed from the maximum allowable length of 64 less the
4 character ..xx extension that must be preserved (removed before
- krunching and appended back on afterwards). The $<nnn>.. prefix is
+ crunching and appended back on afterwards). The $<nnn>.. prefix is
also removed and prepened back on, but doesn't enter into the length
computation because symbols with that prefix are always resolved
by the assembler and will never appear in the symbol table. At least
@@ -271,7 +271,7 @@ evax_shorten_name (char *id)
}
}
- /* We only need worry about krunching the base symbol. */
+ /* We only need worry about crunching the base symbol. */
base_id = xmemdup0 (&id[prefix_dotdot], suffix_dotdot - prefix_dotdot);
if (strlen (base_id) > MAX_LABEL_LENGTH)
@@ -353,7 +353,7 @@ static const int number_of_codings = sizeof (codings) / sizeof (char);
an integer. */
static char decodings[256];
-/* Table used by the crc32 function to calcuate the checksum. */
+/* Table used by the crc32 function to calculate the checksum. */
static unsigned int crc32_table[256] = {0, 0};
/* Given a string in BUF, calculate a 32-bit CRC for it.
@@ -502,7 +502,7 @@ is_truncated_identifier (char *id)
{
if (ptr[0] == '_' && ptr[1] == 'h')
{
- /* Now see if the sum encoded in the identifer matches. */
+ /* Now see if the sum encoded in the identifier matches. */
int x, sum;
sum = 0;
for (x = 0; x < 5; x++)
diff --git a/gas/config/obj-macho.c b/gas/config/obj-macho.c
index 56a9296..28867bd 100644
--- a/gas/config/obj-macho.c
+++ b/gas/config/obj-macho.c
@@ -181,7 +181,7 @@ obj_mach_o_make_or_get_sect (char * segname, char * sectname,
attributes along with the canonical name. */
xlat = bfd_mach_o_section_data_for_mach_sect (stdoutput, segname, sectname);
- /* TODO: more checking of whether overides are acually allowed. */
+ /* TODO: more checking of whether overrides are actually allowed. */
if (xlat != NULL)
{
@@ -192,7 +192,7 @@ obj_mach_o_make_or_get_sect (char * segname, char * sectname,
if ((sectype == BFD_MACH_O_S_ZEROFILL
|| sectype == BFD_MACH_O_S_GB_ZEROFILL)
&& sectype != usectype)
- as_bad (_("cannot overide zerofill section type for `%s,%s'"),
+ as_bad (_("cannot override zerofill section type for `%s,%s'"),
segname, sectname);
else
sectype = usectype;
@@ -308,7 +308,7 @@ obj_mach_o_section (int ignore ATTRIBUTE_UNUSED)
md_flush_pending_output ();
#endif
- /* Get the User's segment annd section names. */
+ /* Get the User's segment and section names. */
if (! obj_mach_o_get_section_names (segname, sectname, 17, 17))
return;
@@ -449,7 +449,7 @@ obj_mach_o_zerofill (int ignore ATTRIBUTE_UNUSED)
md_flush_pending_output ();
#endif
- /* Get the User's segment annd section names. */
+ /* Get the User's segment and section names. */
if (! obj_mach_o_get_section_names (segname, sectname, 17, 17))
return;
diff --git a/gas/config/rx-parse.y b/gas/config/rx-parse.y
index 0c4d162..4471996 100644
--- a/gas/config/rx-parse.y
+++ b/gas/config/rx-parse.y
@@ -1643,7 +1643,7 @@ zero_expr (void)
static int
immediate (expressionS exp, int type, int pos, int bits)
{
- /* We will emit constants ourself here, so negate them. */
+ /* We will emit constants ourselves here, so negate them. */
if (type == RXREL_NEGATIVE && exp.X_op == O_constant)
exp.X_add_number = - exp.X_add_number;
if (type == RXREL_NEGATIVE_BORROW)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c236df1..f8cda59 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -138,9 +138,9 @@ static aarch64_instruction inst;
static bfd_boolean parse_operands (char *, const aarch64_opcode *);
static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
-/* Diagnostics inline function utilites.
+/* Diagnostics inline function utilities.
- These are lightweight utlities which should only be called by parse_operands
+ These are lightweight utilities which should only be called by parse_operands
and other parsers. GAS processes each assembly line by parsing it against
instruction template(s), in the case of multiple templates (for the same
mnemonic name), those templates are tried one by one until one succeeds or
@@ -151,7 +151,7 @@ static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
the parsing; we don't want to slow down the whole parsing by recording
non-user errors in detail.
- Remember that the objective is to help GAS pick up the most approapriate
+ Remember that the objective is to help GAS pick up the most appropriate
error message in the case of multiple templates, e.g. FMOV which has 8
templates. */
@@ -972,7 +972,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
/* Expect index. In the new scheme we cannot have
Vn.[bhsdq] represent a scalar. Therefore any
Vn.[bhsdq] should have an index following it.
- Except in reglists ofcourse. */
+ Except in reglists of course. */
atype.defined |= NTA_HASINDEX;
else
atype.defined |= NTA_HASTYPE;
@@ -1744,7 +1744,7 @@ add_to_lit_pool (expressionS *exp, int size)
}
/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
+ a later date assign it a value. That's what these functions do. */
static void
symbol_locate (symbolS * symbolP,
@@ -2398,7 +2398,7 @@ aarch64_gas_internal_fixup_p (void)
return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
}
-/* Assign the immediate value to the relavant field in *OPERAND if
+/* Assign the immediate value to the relevant field in *OPERAND if
RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
needs an internal fixup in a later stage.
ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
@@ -2686,7 +2686,7 @@ static struct reloc_table_entry reloc_table[] = {
/* Get to the page containing GOT TLS entry for a symbol.
The same as GD, we allocate two consecutive GOT slots
for module index and module offset, the only difference
- with GD is the module offset should be intialized to
+ with GD is the module offset should be initialized to
zero without any outstanding runtime relocation. */
{"tlsldm", 0,
BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
@@ -4203,7 +4203,7 @@ reset_aarch64_instruction (aarch64_instruction *instruction)
instruction->reloc.type = BFD_RELOC_UNUSED;
}
-/* Data strutures storing one user error in the assembly code related to
+/* Data structures storing one user error in the assembly code related to
operands. */
struct operand_error_record
@@ -4434,7 +4434,7 @@ find_best_match (const aarch64_inst *instr,
return idx;
}
-/* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
+/* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
corresponding operands in *INSTR. */
static inline void
@@ -4684,7 +4684,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
When this function is called, the operand error information had
been collected for an assembly line and there will be multiple
- errors in the case of mulitple instruction templates; output the
+ errors in the case of multiple instruction templates; output the
error message that most closely describes the problem. */
static void
@@ -4713,7 +4713,7 @@ output_operand_error_report (char *str)
}
/* Find the error kind of the highest severity. */
- DEBUG_TRACE ("multiple opcode entres with error kind");
+ DEBUG_TRACE ("multiple opcode entries with error kind");
kind = AARCH64_OPDE_NIL;
for (curr = head; curr != NULL; curr = curr->next)
{
@@ -5133,7 +5133,7 @@ process_movw_reloc_info (void)
return TRUE;
}
-/* A primitive log caculator. */
+/* A primitive log calculator. */
static inline unsigned int
get_logsz (unsigned int size)
@@ -5203,7 +5203,7 @@ ldst_lo12_determine_real_reloc_type (void)
gas_assert (logsz <= 4);
/* In reloc.c, these pseudo relocation types should be defined in similar
- order as above reloc_ldst_lo12 array. Because the array index calcuation
+ order as above reloc_ldst_lo12 array. Because the array index calculation
below relies on this. */
return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
}
@@ -5283,7 +5283,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
backtrack_pos = str;
}
- /* Expect comma between operands; the backtrack mechanizm will take
+ /* Expect comma between operands; the backtrack mechanism will take
care of cases of omitted optional operand. */
if (i > 0 && ! skip_past_char (&str, ','))
{
@@ -6952,7 +6952,7 @@ aarch64_handle_align (fragS * fragP)
Note - despite the name this initialisation is not done when the frag
is created, but only when its type is assigned. A frag can be created
and used a long time before its type is set, so beware of assuming that
- this initialisationis performed first. */
+ this initialisation is performed first. */
#ifndef OBJ_ELF
void
diff --git a/gas/config/tc-alpha.c b/gas/config/tc-alpha.c
index 0f70314..c72d26d 100644
--- a/gas/config/tc-alpha.c
+++ b/gas/config/tc-alpha.c
@@ -706,7 +706,7 @@ alpha_adjust_relocs (bfd *abfd ATTRIBUTE_UNUSED,
present. Not implemented.
Also suppress the optimization if the !literals/!lituses are spread
- in different segments. This can happen with "intersting" uses of
+ in different segments. This can happen with "interesting" uses of
inline assembly; examples are present in the Linux kernel semaphores. */
for (fixp = seginfo->fix_root; fixp; fixp = next)
@@ -3369,7 +3369,7 @@ assemble_tokens (const char *opname,
#ifdef OBJ_EVAX
/* Add sym+addend to link pool.
- Return offset from curent procedure value (pv) to entry in link pool.
+ Return offset from current procedure value (pv) to entry in link pool.
Add new fixup only if offset isn't 16bit. */
@@ -4882,7 +4882,7 @@ s_alpha_gprel32 (int ignore ATTRIBUTE_UNUSED)
}
/* Handle floating point allocation pseudo-ops. This is like the
- generic vresion, but it makes sure the current label, if any, is
+ generic version, but it makes sure the current label, if any, is
correctly aligned. */
static void
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 04ebc37..ec0fb68 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1195,7 +1195,7 @@ tokenize_arguments (char *str,
relocationsym:
- /* A relocation opernad has the following form
+ /* A relocation operand has the following form
@identifier@relocation_type. The identifier is already
in tok! */
if (tok->X_op != O_symbol)
@@ -1612,7 +1612,7 @@ allocate_tok (expressionS *tok, int ntok, int cidx)
return 0; /* No space left. */
if (cidx > ntok)
- return 0; /* Incorect args. */
+ return 0; /* Incorrect args. */
memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
@@ -1938,7 +1938,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
if (val < min || val > max)
goto match_failed;
- /* Check alignmets. */
+ /* Check alignments. */
if ((operand->flags & ARC_OPERAND_ALIGNED32)
&& (val & 0x03))
goto match_failed;
@@ -2341,7 +2341,7 @@ find_special_case (const char *opname,
return entry;
}
-/* Given an opcode name, pre-tockenized set of argumenst and the
+/* Given an opcode name, pre-tokenized set of arguments and the
opcode flags, take it all the way through emission. */
static void
@@ -2412,7 +2412,7 @@ md_assemble (char *str)
opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
opname = xmemdup0 (str, opnamelen);
- /* Signalize we are assmbling the instructions. */
+ /* Signalize we are assembling the instructions. */
assembling_insn = TRUE;
/* Tokenize the flags. */
@@ -2725,7 +2725,7 @@ md_pcrel_from_section (fixS *fixP,
return base;
}
-/* Given a BFD relocation find the coresponding operand. */
+/* Given a BFD relocation find the corresponding operand. */
static const struct arc_operand *
find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
@@ -2902,7 +2902,7 @@ md_apply_fix (fixS *fixP,
case BFD_RELOC_ARC_32_ME:
/* This is a pc-relative value in a LIMM. Adjust it to the
address of the instruction not to the address of the
- LIMM. Note: it is not anylonger valid this afirmation as
+ LIMM. Note: it is not any longer valid this affirmation as
the linker consider ARC_PC32 a fixup to entire 64 bit
insn. */
fixP->fx_offset += fixP->fx_frag->fr_address;
@@ -2971,7 +2971,7 @@ md_apply_fix (fixS *fixP,
return;
}
- /* Addjust the value if we have a constant. */
+ /* Adjust the value if we have a constant. */
value += fx_offset;
/* For hosts with longs bigger than 32-bits make sure that the top
@@ -3892,7 +3892,7 @@ assemble_insn (const struct arc_opcode *opcode,
case O_plt:
if (opcode->insn_class == JUMP)
as_bad_where (frag_now->fr_file, frag_now->fr_line,
- _("Unable to use @plt relocatio for insn %s"),
+ _("Unable to use @plt relocation for insn %s"),
opcode->name);
needGOTSymbol = TRUE;
reloc = find_reloc ("plt", opcode->name,
@@ -4679,7 +4679,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype)
[2]: Value.
[3]+ Name.
- For auxilirary registers:
+ For auxiliary registers:
[2..5]: Value.
[6]+ Name
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 60bda51..7947035 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -2710,7 +2710,7 @@ mapping_state (enum mstate state)
Some Thumb instructions are alignment-sensitive modulo 4 bytes,
but themselves require 2-byte alignment; this applies to some
- PC- relative forms. However, these cases will invovle implicit
+ PC- relative forms. However, these cases will involve implicit
literal pool generation or an explicit .align >=2, both of
which will cause the section to me marked with sufficient
alignment. Thus, we don't handle those cases here. */
@@ -3380,7 +3380,7 @@ tc_start_label_without_colon (void)
}
/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
+ a later date assign it a value. That's what these functions do. */
static void
symbol_locate (symbolS * symbolP,
@@ -6548,7 +6548,7 @@ enum operand_parse_code
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
OP_RRnpc_I0, /* ARM register or literal 0 */
- OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
+ OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
OP_RR_EXi, /* ARM register or expression with imm prefix */
OP_RF_IF, /* FPA register or immediate */
OP_RIWR_RIWC, /* iWMMXt R or C reg */
@@ -9058,9 +9058,9 @@ do_mov16 (void)
top = (inst.instruction & 0x00400000) != 0;
constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
- _(":lower16: not allowed this instruction"));
+ _(":lower16: not allowed in this instruction"));
constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
- _(":upper16: not allowed instruction"));
+ _(":upper16: not allowed in this instruction"));
inst.instruction |= inst.operands[0].reg << 12;
if (inst.reloc.type == BFD_RELOC_UNUSED)
{
@@ -10486,7 +10486,7 @@ do_t_add_sub_w (void)
}
/* Parse an add or subtract instruction. We get here with inst.instruction
- equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
+ equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
static void
do_t_add_sub (void)
@@ -12115,12 +12115,12 @@ do_t_mov16 (void)
top = (inst.instruction & 0x00800000) != 0;
if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
{
- constraint (top, _(":lower16: not allowed this instruction"));
+ constraint (top, _(":lower16: not allowed in this instruction"));
inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
}
else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
{
- constraint (!top, _(":upper16: not allowed this instruction"));
+ constraint (!top, _(":upper16: not allowed in this instruction"));
inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
}
@@ -18007,7 +18007,7 @@ now_it_add_mask (int cond)
set_it_insn_type_last () ditto
in_it_block () ditto
it_fsm_post_encode () from md_assemble ()
- force_automatic_it_block_close () from label habdling functions
+ force_automatic_it_block_close () from label handling functions
Rationale:
1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
@@ -21858,7 +21858,7 @@ arm_frag_align_code (int n, int max)
Note - despite the name this initialisation is not done when the frag
is created, but only when its type is assigned. A frag can be created
and used a long time before its type is set, so beware of assuming that
- this initialisationis performed first. */
+ this initialisation is performed first. */
#ifndef OBJ_ELF
void
@@ -25777,7 +25777,7 @@ static const struct arm_option_fpu_value_table arm_fpus[] =
{"softvfp+vfp", FPU_ARCH_VFP_V2},
{"vfp", FPU_ARCH_VFP_V2},
{"vfp9", FPU_ARCH_VFP_V2},
- {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
+ {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatibility. */
{"vfp10", FPU_ARCH_VFP_V2},
{"vfp10-r0", FPU_ARCH_VFP_V1},
{"vfpxd", FPU_ARCH_VFP_V1xD},
diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c
index 3eb0942..7214c07 100644
--- a/gas/config/tc-avr.c
+++ b/gas/config/tc-avr.c
@@ -72,19 +72,19 @@ struct mcu_type_s
static struct mcu_type_s mcu_types[] =
{
{"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
-/* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
+/* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2,
but set to AVR_ISA_AVR25 for some following version
of GCC (from 4.3) for backward compatibility. */
{"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
{"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
-/* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
+/* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3,
but set to AVR_ISA_AVR3_ALL for some following version
of GCC (from 4.3) for backward compatibility. */
{"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
{"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
{"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
{"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
-/* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
+/* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5,
but set to AVR_ISA_AVR51 for some following version
of GCC (from 4.3) for backward compatibility. */
{"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
@@ -1673,7 +1673,7 @@ md_assemble (char *str)
specifications with same mnemonic who's ISA bits matches.
This requires include/opcode/avr.h to have the instructions with
- same mnenomic to be specified in sequence. */
+ same mnemonic to be specified in sequence. */
while ((opcode->isa & avr_mcu->isa) != opcode->isa)
{
@@ -1819,7 +1819,7 @@ avr_cons_fix_new (fragS *frag,
}
if (bad)
- as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes);
+ as_bad (_("illegal %s relocation size: %d"), pexp_mod_data->error, nbytes);
}
static bfd_boolean
@@ -1843,7 +1843,7 @@ tc_cfi_frame_initial_instructions (void)
cfi_add_CFA_def_cfa (32, return_size);
/* Note that AVR consistently uses post-decrement, which means that things
- do not line up the same way as for targers that use pre-decrement. */
+ do not line up the same way as for targets that use pre-decrement. */
cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
}
diff --git a/gas/config/tc-bfin.c b/gas/config/tc-bfin.c
index 028dbec..b5ecf4a 100644
--- a/gas/config/tc-bfin.c
+++ b/gas/config/tc-bfin.c
@@ -968,13 +968,13 @@ INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc);
INSTR_T
Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
{
- /* Top level reloction expression generator VDSP style.
+ /* Top level relocation expression generator VDSP style.
If the relocation is just by itself, generate one item
else generate this convoluted expression. */
INSTR_T note = NULL_CODE;
INSTR_T note1 = NULL_CODE;
- int pcrel = 1; /* Is the parent reloc pcrelative?
+ int pcrel = 1; /* Is the parent reloc pc-relative?
This calculation here and HOWTO should match. */
if (parent_reloc)
diff --git a/gas/config/tc-cr16.c b/gas/config/tc-cr16.c
index 76de462..4205a77 100644
--- a/gas/config/tc-cr16.c
+++ b/gas/config/tc-cr16.c
@@ -334,7 +334,7 @@ get_register_pair (char *reg_name)
const reg_entry *rreg;
char tmp_rp[16]="\0";
- /* Add '(' and ')' to the reg pair, if its not present. */
+ /* Add '(' and ')' to the reg pair, if it's not present. */
if (reg_name[0] != '(')
{
tmp_rp[0] = '(';
@@ -1153,8 +1153,8 @@ getreg_image (reg r)
static void
set_operand (char *operand, ins * cr16_ins)
{
- char *operandS; /* Pointer to start of sub-opearand. */
- char *operandE; /* Pointer to end of sub-opearand. */
+ char *operandS; /* Pointer to start of sub-operand. */
+ char *operandE; /* Pointer to end of sub-operand. */
argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */
@@ -1654,7 +1654,7 @@ getidxregp_image (reg r)
return 0;
}
-/* Retrieve the opcode image of a given processort register.
+/* Retrieve the opcode image of a given processor register.
If the register is illegal for the current instruction,
issue an error. */
static int
@@ -1692,7 +1692,7 @@ getprocreg_image (int r)
return 0;
}
-/* Retrieve the opcode image of a given processort register.
+/* Retrieve the opcode image of a given processor register.
If the register is illegal for the current instruction,
issue an error. */
static int
@@ -1846,7 +1846,7 @@ print_constant (int nbits, int shift, argument *arg)
/* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
always filling the upper part of output_opcode[1]. If we mistakenly
write it to output_opcode[0], the constant prefix (that is, 'match')
- will be overriden.
+ will be overridden.
0 1 2 3
+---------+---------+---------+---------+
| 'match' | | X X X X | |
@@ -2002,7 +2002,7 @@ check_range (long *num, int bits, int unsigned flags, int update)
if (bits == 0 && value > 0) return OP_OUT_OF_RANGE;
- /* For hosts witah longs bigger than 32-bits make sure that the top
+ /* For hosts with longs bigger than 32-bits make sure that the top
bits of a 32-bit negative value read in by the parser are set,
so that the correct comparisons are made. */
if (value & 0x80000000)
@@ -2085,7 +2085,7 @@ check_range (long *num, int bits, int unsigned flags, int update)
return retval;
}
-/* Bunch of error checkings.
+/* Bunch of error checking.
The checks are made after a matching instruction was found. */
static void
@@ -2108,7 +2108,7 @@ warn_if_needed (ins *insn)
{
unsigned int count = insn->arg[0].constant, reg_val;
- /* Check if count operand caused to save/retrive the RA twice
+ /* Check if count operand caused to save/retrieve the RA twice
to generate warning message. */
if (insn->nargs > 2)
{
@@ -2289,7 +2289,7 @@ assemble_insn (const char *mnemonic, ins *insn)
goto next_insn;
/* If 'storb' instruction with 'sp' reg and 16-bit disp of
- * reg-pair, leads to undifined trap, so this should use
+ * reg-pair, leads to undefined trap, so this should use
* 20-bit disp of reg-pair. */
if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
&& (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
@@ -2356,7 +2356,7 @@ next_insn:
else
/* Full match - print the encoding to output file. */
{
- /* Make further checkings (such that couldn't be made earlier).
+ /* Make further checking (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
@@ -2538,7 +2538,7 @@ md_assemble (char *op)
;
*param++ = '\0';
- /* bCC instuctions and adjust the mnemonic by adding extra white spaces. */
+ /* bCC instructions and adjust the mnemonic by adding extra white spaces. */
if (is_bcc_insn (op))
{
strcpy (param1, get_b_cc (op));
@@ -2560,7 +2560,7 @@ md_assemble (char *op)
/* MAPPING - SHIFT INSN, if imm4/imm16 positive values
lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
- as CR16 core doesn't support lsh[b/w] right shift operaions. */
+ as CR16 core doesn't support lsh[b/w] right shift operations. */
if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
&& (param [0] == '$'))
{
diff --git a/gas/config/tc-cris.c b/gas/config/tc-cris.c
index 341b9a2..cf9b2ad 100644
--- a/gas/config/tc-cris.c
+++ b/gas/config/tc-cris.c
@@ -81,7 +81,7 @@ struct cris_prefix
expressionS expr;
/* If there's an expression, we might need a relocation. Here's the
- type of what relocation to start relaxaton with.
+ type of what relocation to start relaxation with.
The relocation is assumed to start immediately after the prefix insn,
so we don't provide an offset. */
enum bfd_reloc_code_real reloc;
diff --git a/gas/config/tc-crx.c b/gas/config/tc-crx.c
index 265f01b..be0d455 100644
--- a/gas/config/tc-crx.c
+++ b/gas/config/tc-crx.c
@@ -569,7 +569,7 @@ md_begin (void)
{
hashret = hash_insert (reg_hash, regtab->name, (void *) regtab);
if (hashret)
- as_fatal (_("Internal Error: Can't hash %s: %s"),
+ as_fatal (_("Internal error: Can't hash %s: %s"),
regtab->name,
hashret);
}
@@ -588,7 +588,7 @@ md_begin (void)
hashret = hash_insert (copreg_hash, copregtab->name,
(void *) copregtab);
if (hashret)
- as_fatal (_("Internal Error: Can't hash %s: %s"),
+ as_fatal (_("Internal error: Can't hash %s: %s"),
copregtab->name,
hashret);
}
@@ -715,8 +715,8 @@ exponent2scale (int val)
static void
set_operand (char *operand, ins * crx_ins)
{
- char *operandS; /* Pointer to start of sub-opearand. */
- char *operandE; /* Pointer to end of sub-opearand. */
+ char *operandS; /* Pointer to start of sub-operand. */
+ char *operandE; /* Pointer to end of sub-operand. */
expressionS scale;
int scale_val;
char *input_save, c;
@@ -756,7 +756,7 @@ set_operand (char *operand, ins * crx_ins)
operandE++;
*operandE = '\0';
if ((cur_arg->r = get_register (operandS)) == nullregister)
- as_bad (_("Illegal register `%s' in Instruction `%s'"),
+ as_bad (_("Illegal register `%s' in instruction `%s'"),
operandS, ins_parse);
if (cur_arg->type != arg_rbase)
@@ -776,7 +776,7 @@ set_operand (char *operand, ins * crx_ins)
operandE++;
*operandE++ = '\0';
if ((cur_arg->r = get_register (operandS)) == nullregister)
- as_bad (_("Illegal register `%s' in Instruction `%s'"),
+ as_bad (_("Illegal register `%s' in instruction `%s'"),
operandS, ins_parse);
/* Skip leading white space. */
@@ -791,7 +791,7 @@ set_operand (char *operand, ins * crx_ins)
*operandE++ = '\0';
if ((cur_arg->i_r = get_register (operandS)) == nullregister)
- as_bad (_("Illegal register `%s' in Instruction `%s'"),
+ as_bad (_("Illegal register `%s' in instruction `%s'"),
operandS, ins_parse);
/* Skip leading white space. */
@@ -1134,7 +1134,7 @@ getreg_image (reg r)
/* Issue a error message when register is illegal. */
#define IMAGE_ERR \
- as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
+ as_bad (_("Illegal register (`%s') in instruction: `%s'"), \
reg_name, ins_parse); \
break;
@@ -1261,14 +1261,14 @@ print_operand (int nbits, int shift, argument *arg)
case arg_copr:
if (arg->cr < c0 || arg->cr > c15)
- as_bad (_("Illegal Co-processor register in Instruction `%s' "),
+ as_bad (_("Illegal co-processor register in instruction `%s'"),
ins_parse);
CRX_PRINT (0, getreg_image (arg->cr), shift);
break;
case arg_copsr:
if (arg->cr < cs0 || arg->cr > cs15)
- as_bad (_("Illegal Co-processor special register in Instruction `%s' "),
+ as_bad (_("Illegal co-processor special register in instruction `%s'"),
ins_parse);
CRX_PRINT (0, getreg_image (arg->cr), shift);
break;
@@ -1610,7 +1610,7 @@ next_insn:
else
/* Full match - print the encoding to output file. */
{
- /* Make further checkings (such that couldn't be made earlier).
+ /* Make further checking (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
@@ -1648,7 +1648,7 @@ next_insn:
return 1;
}
-/* Bunch of error checkings.
+/* Bunch of error checking.
The checks are made after a matching instruction was found. */
void
@@ -1733,7 +1733,7 @@ mask_reg (int r, unsigned short int *mask)
{
if ((reg)r > (reg)sp)
{
- as_bad (_("Invalid Register in Register List"));
+ as_bad (_("Invalid register in register list"));
return;
}
@@ -1752,7 +1752,7 @@ preprocess_reglist (char *param, int *allocated)
int reg_counter = 0; /* Count number of parsed registers. */
unsigned short int mask = 0; /* Mask for 16 general purpose registers. */
char *new_param; /* New created operands string. */
- char *paramP = param; /* Pointer to original opearands string. */
+ char *paramP = param; /* Pointer to original operands string. */
char maskstring[10]; /* Array to print the mask as a string. */
int hi_found = 0, lo_found = 0; /* Boolean flags for hi/lo registers. */
reg r;
@@ -1897,7 +1897,7 @@ print_insn (ins *insn)
words[j++] = output_opcode[i] & 0xFFFF;
}
- /* Handle relaxtion. */
+ /* Handle relaxation. */
if ((instruction->flags & RELAXABLE) && relocatable)
{
int relax_subtype;
diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c
index 374a164..497b2dd 100644
--- a/gas/config/tc-d10v.c
+++ b/gas/config/tc-d10v.c
@@ -104,7 +104,7 @@ size_t md_longopts_size = sizeof (md_longopts);
static struct hash_control *d10v_hash;
/* Do a binary search of the d10v_predefined_registers array to see if
- NAME is a valid regiter name. Return the register number from the
+ NAME is a valid register name. Return the register number from the
array on success, or -1 on failure. */
static int
diff --git a/gas/config/tc-d30v.c b/gas/config/tc-d30v.c
index 268dbd2..1b3a85c 100644
--- a/gas/config/tc-d30v.c
+++ b/gas/config/tc-d30v.c
@@ -121,7 +121,7 @@ size_t md_longopts_size = sizeof (md_longopts);
static struct hash_control *d30v_hash;
/* Do a binary search of the pre_defined_registers array to see if
- NAME is a valid regiter name. Return the register number from the
+ NAME is a valid register name. Return the register number from the
array on success, or -1 on failure. */
static int
@@ -239,8 +239,8 @@ md_show_usage (FILE *stream)
fprintf (stream, _("\nD30V options:\n\
-O Make adjacent short instructions parallel if possible.\n\
-n Warn about all NOPs inserted by the assembler.\n\
--N Warn about NOPs inserted after word multiplies.\n\
--c Warn about symbols whoes names match register names.\n\
+-N Warn about NOPs inserted after word multiplies.\n\
+-c Warn about symbols whose names match register names.\n\
-C Opposite of -C. -c is the default.\n"));
}
@@ -998,7 +998,7 @@ write_2_short (struct d30v_insn *opcode1,
}
else if (prev_left_kills_right_p)
{
- /* The left instruction kils the right slot, so we
+ /* The left instruction kills the right slot, so we
must leave it empty. */
write_1_short (opcode1, insn1, fx->next, FALSE);
return 1;
diff --git a/gas/config/tc-dlx.c b/gas/config/tc-dlx.c
index de5b8e9..48ca9ee 100644
--- a/gas/config/tc-dlx.c
+++ b/gas/config/tc-dlx.c
@@ -776,7 +776,7 @@ machine_ip (char *str)
/* Macro move operand/reg. */
if (operand->X_op == O_register)
{
- /* Its a register. */
+ /* It's a register. */
reg_shift = 21;
goto general_reg;
}
diff --git a/gas/config/tc-epiphany.c b/gas/config/tc-epiphany.c
index 8a8bbcb..bd7cc1b 100644
--- a/gas/config/tc-epiphany.c
+++ b/gas/config/tc-epiphany.c
@@ -429,7 +429,7 @@ epiphany_assemble (const char *str)
#define DISPMOD _("destination register modified by displacement-post-modified address")
#define LDSTODD _("ldrd/strd requires even:odd register pair")
- /* Helper macros for spliting apart instruction fields. */
+ /* Helper macros for splitting apart instruction fields. */
#define ADDR_POST_MODIFIED(i) (((i) >> 25) & 0x1)
#define ADDR_SIZE(i) (((i) >> 5) & 3)
#define ADDR_LOADSTORE(i) (((i) >> 4) & 0x1)
@@ -1055,7 +1055,7 @@ epiphany_fix_adjustable (fixS *fixP)
return FALSE;
/* Since we don't use partial_inplace, we must not reduce symbols in
- mergable sections to their section symbol. */
+ mergeable sections to their section symbol. */
if ((S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)
return FALSE;
diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c
index 7510a97..c6e0917 100644
--- a/gas/config/tc-frv.c
+++ b/gas/config/tc-frv.c
@@ -469,7 +469,7 @@ md_show_usage (FILE * stream)
fprintf (stream, _("-mno-pack Do not allow instructions to be packed\n"));
fprintf (stream, _("-mpic Mark generated file as using small position independent code\n"));
fprintf (stream, _("-mPIC Mark generated file as using large position independent code\n"));
- fprintf (stream, _("-mlibrary-pic Mark generated file as using position indepedent code for libraries\n"));
+ fprintf (stream, _("-mlibrary-pic Mark generated file as using position independent code for libraries\n"));
fprintf (stream, _("-mfdpic Assemble for the FDPIC ABI\n"));
fprintf (stream, _("-mnopic Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"));
fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"));
diff --git a/gas/config/tc-hppa.c b/gas/config/tc-hppa.c
index 30d3229..1dbc097 100644
--- a/gas/config/tc-hppa.c
+++ b/gas/config/tc-hppa.c
@@ -7025,7 +7025,7 @@ pa_procend (int unused ATTRIBUTE_UNUSED)
#ifdef OBJ_ELF
/* ELF needs to mark the end of each function so that it can compute
- the size of the function (apparently its needed in the symbol table). */
+ the size of the function (apparently it's needed in the symbol table). */
hppa_elf_mark_end_of_function ();
#endif
diff --git a/gas/config/tc-i370.c b/gas/config/tc-i370.c
index fa6fc75..995aa4c 100644
--- a/gas/config/tc-i370.c
+++ b/gas/config/tc-i370.c
@@ -276,7 +276,7 @@ register_name (expressionS *expressionP)
(void) restore_line_pointer (c);
}
- /* If numeric, make sure its not out of bounds. */
+ /* If numeric, make sure it's not out of bounds. */
if ((0 <= reg_number) && (16 >= reg_number))
{
expressionP->X_op = O_register;
@@ -443,7 +443,7 @@ md_parse_option (int c, const char *arg)
/* Set i370_cpu if it is not already set.
Currently defaults to the reasonable superset;
- but can be made more fine grained if desred. */
+ but can be made more fine grained if desired. */
static void
i370_set_cpu (void)
@@ -887,7 +887,7 @@ i370_csect (int unused ATTRIBUTE_UNUSED)
/* DC Define Const is only partially supported.
- For samplecode on what to do, look at i370_elf_cons() above.
+ For sample code on what to do, look at i370_elf_cons() above.
This code handles pseudoops of the style
DC D'3.141592653' # in sysv4, .double 3.14159265
DC F'1' # in sysv4, .long 1. */
@@ -1187,7 +1187,7 @@ i370_elf_validate_fix (fixS *fixp, segT seg)
start of each pool part.
lit_pool_num increments from zero to infinity and uniquely id's
- -- its used to generate the *_poolP symbol name. */
+ -- it's used to generate the *_poolP symbol name. */
#define MAX_LITERAL_POOL_SIZE 1024
@@ -1325,11 +1325,11 @@ add_to_lit_pool (expressionS *exx, char *name, int sz)
/* The symbol setup for the literal pool is done in two steps. First,
a symbol that represents the start of the literal pool is created,
above, in the add_to_pool() routine. This sym ???_poolP.
- However, we don't know what fragment its in until a bit later.
+ However, we don't know what fragment it's in until a bit later.
So we defer the frag_now thing, and the symbol name, until .ltorg time. */
/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
+ a later date assign it a value. That's what these functions do. */
static void
symbol_locate (symbolS *symbolP,
@@ -1549,7 +1549,7 @@ i370_addr_cons (expressionS *exp)
=X'AB' one byte
=X'abcd' two bytes
=X'000000AB' four bytes
- =XL4'AB' four bytes, left-padded withn zero. */
+ =XL4'AB' four bytes, left-padded with zero. */
if (('X' == name[0]) && (0 > cons_len))
{
save = input_line_pointer;
@@ -1774,7 +1774,7 @@ i370_drop (int ignore ATTRIBUTE_UNUSED)
if (0 == strncmp (now_seg->name, ".text", 5))
{
if (iregno != i370_using_text_regno)
- as_bad (_("droping register %d in section %s does not match using register %d"),
+ as_bad (_("dropping register %d in section %s does not match using register %d"),
iregno, now_seg->name, i370_using_text_regno);
i370_using_text_regno = -1;
@@ -1783,11 +1783,11 @@ i370_drop (int ignore ATTRIBUTE_UNUSED)
else
{
if (iregno != i370_using_other_regno)
- as_bad (_("droping register %d in section %s does not match using register %d"),
+ as_bad (_("dropping register %d in section %s does not match using register %d"),
iregno, now_seg->name, i370_using_other_regno);
if (i370_other_section != now_seg)
- as_bad (_("droping register %d in section %s previously used in section %s"),
+ as_bad (_("dropping register %d in section %s previously used in section %s"),
iregno, now_seg->name, i370_other_section->name);
i370_using_other_regno = -1;
@@ -2009,9 +2009,9 @@ md_assemble (char *str)
}
/* Perform some off-by-one hacks on the length field of certain instructions.
- Its such a shame to have to do this, but the problem is that HLASM got
+ It's such a shame to have to do this, but the problem is that HLASM got
defined so that the lengths differ by one from the actual machine instructions.
- this code should probably be moved to a special inster-operand routine.
+ this code should probably be moved to a special inter-operand routine.
Sigh. Affected instructions are Compare Logical, Move and Exclusive OR
hack alert -- aren't *all* SS instructions affected ?? */
off_by_one = 0;
@@ -2115,7 +2115,7 @@ md_assemble (char *str)
input_line_pointer = hold;
/* Perform some off-by-one hacks on the length field of certain instructions.
- Its such a shame to have to do this, but the problem is that HLASM got
+ It's such a shame to have to do this, but the problem is that HLASM got
defined so that the programmer specifies a length that is one greater
than what the machine instruction wants. Sigh. */
if (off_by_one && (0 == strcasecmp ("SS L", operand->name)))
@@ -2249,7 +2249,7 @@ md_assemble (char *str)
if (size < 1 || size > 4)
abort ();
- printf (" gwana doo fixup %d \n", i);
+ printf (" gwana do fixup %d \n", i);
fixP = fix_new_exp (frag_now, f - frag_now->fr_literal, size,
&fixups[i].exp, reloc_howto->pc_relative,
fixups[i].reloc);
@@ -2497,7 +2497,7 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg)
We are only prepared to turn a few of the operands into
relocs. In fact, we support *zero* operand relocations ...
Why? Because we are not expecting the compiler to generate
- any operands that need relocation. Due to the 12-bit naturew of
+ any operands that need relocation. Due to the 12-bit nature of
i370 addressing, this would be unusual. */
{
const char *sfile;
diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c
index c861ec7..92ed98e 100644
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -26,7 +26,7 @@ static struct
int has_offset; /* 1 if operand has offset. */
unsigned int in_offset; /* >=1 if processing operand of offset. */
unsigned int in_bracket; /* >=1 if processing operand in brackets. */
- unsigned int in_scale; /* >=1 if processing multipication operand
+ unsigned int in_scale; /* >=1 if processing multiplication operand
* in brackets. */
i386_operand_type reloc_types; /* Value obtained from lex_got(). */
const reg_entry *base; /* Base register (if any). */
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 1fc6bc7..12b3032 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -555,7 +555,7 @@ static int allow_pseudo_reg = 0;
/* 1 if register prefix % not required. */
static int allow_naked_reg = 0;
-/* 1 if the assembler should add BND prefix for all control-tranferring
+/* 1 if the assembler should add BND prefix for all control-transferring
instructions supporting it, even if this prefix wasn't specified
explicitly. */
static int add_bnd_prefix = 0;
@@ -2463,7 +2463,7 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
{
- /* Disable an ISA entension. */
+ /* Disable an ISA extension. */
for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
if (strcmp (string + 1, cpu_noarch [j].name) == 0)
{
@@ -3140,7 +3140,7 @@ build_vex_prefix (const insn_template *t)
else
register_specifier = 0xf;
- /* Use 2-byte VEX prefix by swappping destination and source
+ /* Use 2-byte VEX prefix by swapping destination and source
operand. */
if (!i.swap_operand
&& i.operands == i.reg_operands
@@ -4956,7 +4956,7 @@ match_template (char mnem_suffix)
continue;
break;
case 2:
- /* xchg %eax, %eax is a special case. It is an aliase for nop
+ /* xchg %eax, %eax is a special case. It is an alias for nop
only in 32bit mode and we can use opcode 0x90. In 64bit
mode, we can't use 0x90 for xchg %eax, %eax since it should
zero-extend %eax to %rax. */
@@ -6209,7 +6209,7 @@ build_modrm_byte (void)
if (i.tm.opcode_modifier.immext)
{
- /* When ImmExt is set, the immdiate byte is the last
+ /* When ImmExt is set, the immediate byte is the last
operand. */
imm_slot = i.operands - 1;
source--;
@@ -9165,7 +9165,7 @@ elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
{
case BFD_RELOC_386_PLT32:
case BFD_RELOC_X86_64_PLT32:
- /* Symbol with PLT relocatin may be preempted. */
+ /* Symbol with PLT relocation may be preempted. */
return 0;
default:
abort ();
@@ -10057,7 +10057,7 @@ md_parse_option (int c, const char *arg)
else if (*cpu_arch [j].name == '.'
&& strcmp (arch, cpu_arch [j].name + 1) == 0)
{
- /* ISA entension. */
+ /* ISA extension. */
i386_cpu_flags flags;
flags = cpu_flags_or (cpu_arch_flags,
@@ -10084,7 +10084,7 @@ md_parse_option (int c, const char *arg)
if (j >= ARRAY_SIZE (cpu_arch))
{
- /* Disable an ISA entension. */
+ /* Disable an ISA extension. */
for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
if (strcmp (arch, cpu_noarch [j].name) == 0)
{
diff --git a/gas/config/tc-i960.c b/gas/config/tc-i960.c
index b1f8e98..0e2438f 100644
--- a/gas/config/tc-i960.c
+++ b/gas/config/tc-i960.c
@@ -406,7 +406,7 @@ int iclasses_seen; /* OR of instruction classes (I_* constants)
of branches taken/not-taken for later input to a utility that will
set the branch prediction bits of the instructions in accordance with
the behavior observed. (Note that the KX series does not have
- brach-prediction.)
+ branch-prediction.)
The instrumentation consists of:
@@ -980,7 +980,7 @@ parse_memop (memS *memP, /* Where to put the results. */
regnum = *intP;
*p = '\0'; /* Discard register spec. */
if (regnum == IPREL)
- /* We have to specialcase ip-rel mode. */
+ /* We have to special-case ip-rel mode. */
iprel_flag = 1;
else
{
@@ -1404,7 +1404,7 @@ get_args (char *p, /* Pointer to comma-separated operands; Mucked by us. */
n = 1;
args[1] = p;
- /* Squeze blanks out by moving non-blanks toward start of string.
+ /* Squeeze blanks out by moving non-blanks toward start of string.
Isolate operands, whenever comma is found. */
to = p;
while (*p != '\0')
@@ -1646,7 +1646,7 @@ md_assemble (char *textP)
if (!oP || !targ_has_iclass (oP->iclass))
as_bad (_("invalid opcode, \"%s\"."), args[0]);
else if (n_ops != oP->num_ops)
- as_bad (_("improper number of operands. expecting %d, got %d"),
+ as_bad (_("improper number of operands. Expecting %d, got %d"),
oP->num_ops, n_ops);
else
{
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
index fdcffb4..aa01eff 100644
--- a/gas/config/tc-ia64.c
+++ b/gas/config/tc-ia64.c
@@ -234,7 +234,7 @@ static struct
struct hash_control *const_hash; /* constant hash table */
struct hash_control *entry_hash; /* code entry hint hash table */
- /* If X_op is != O_absent, the registername for the instruction's
+ /* If X_op is != O_absent, the register name for the instruction's
qualifying predicate. If NULL, p0 is assumed for instructions
that are predictable. */
expressionS qp;
@@ -2801,7 +2801,7 @@ fixup_unw_records (unw_rec_list *list, int before_relax)
for (ptr = list; ptr; ptr = ptr->next)
{
if (ptr->slot_number == SLOT_NUM_NOT_SET)
- as_bad (_(" Insn slot not set in unwind record."));
+ as_bad (_("Insn slot not set in unwind record."));
t = slot_index (ptr->slot_number, ptr->slot_frag,
first_addr, first_frag, before_relax);
switch (ptr->r.type)
@@ -3373,7 +3373,7 @@ dot_save (int dummy ATTRIBUTE_UNUSED)
e2.X_op = O_absent;
reg1 = e1.X_add_number;
- /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
+ /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */
if (e1.X_op != O_register)
{
as_bad (_("First operand to .save not a register"));
@@ -3765,7 +3765,7 @@ dot_savemem (int psprel)
reg1 = e1.X_add_number;
val = e2.X_add_number;
- /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
+ /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */
if (e1.X_op != O_register)
{
as_bad (_("First operand to .%s not a register"), po);
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index 9f5436d..79e1585 100644
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -113,7 +113,7 @@ static int warn_explicit_parallel_conflicts = 1;
/* Non-zero if the programmer should not receive any messages about
parallel instruction with potential or real constraint violations.
The ability to suppress these messages is intended only for hardware
- vendors testing the chip. It superceedes
+ vendors testing the chip. It supersedes
warn_explicit_parallel_conflicts. */
static int ignore_parallel_conflicts = 0;
@@ -393,11 +393,11 @@ md_show_usage (FILE *stream)
fprintf (stream, _("\
-warn-explicit-parallel-conflicts warn when parallel instructions\n"));
fprintf (stream, _("\
- might violate contraints\n"));
+ might violate constraints\n"));
fprintf (stream, _("\
-no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
fprintf (stream, _("\
- instructions might violate contraints\n"));
+ instructions might violate constraints\n"));
fprintf (stream, _("\
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
@@ -2291,7 +2291,7 @@ printf(" => %s\n",reloc->howto->name);
&& S_IS_DEFINED (fixP->fx_addsy)
&& ! S_IS_EXTERNAL(fixP->fx_addsy)
&& ! S_IS_WEAK(fixP->fx_addsy))
- /* Already used fx_offset in the opcode field itseld. */
+ /* Already used fx_offset in the opcode field itself. */
reloc->addend = fixP->fx_offset;
else
reloc->addend = fixP->fx_addnumber;
diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c
index a2ac590..4e9916d 100644
--- a/gas/config/tc-m68hc11.c
+++ b/gas/config/tc-m68hc11.c
@@ -241,7 +241,7 @@ static void s_m68hc11_mark_symbol (int);
dbcc -> db!cc +3
jmp L
- Setting the flag forbidds this. */
+ Setting the flag forbids this. */
static short flag_fixed_branches = 0;
/* Force to use long jumps (absolute) instead of relative branches. */
@@ -329,11 +329,11 @@ struct option md_longopts[] =
{
#define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
{"force-long-branches", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
- {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelt version kept for backwards compatibility. */
+ {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelled version kept for backwards compatibility. */
#define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1)
{"short-branches", no_argument, NULL, OPTION_SHORT_BRANCHES},
- {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelt version kept for backwards compatibility. */
+ {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelled version kept for backwards compatibility. */
#define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
{"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
@@ -1710,7 +1710,7 @@ fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED)
}
/* XGATE Put a 1 byte expression described by 'oper'. If this expression
- containts unresolved symbols, generate an 8-bit fixup. */
+ contains unresolved symbols, generate an 8-bit fixup. */
static void
fixup8_xg (expressionS *oper, int mode, int opmode)
{
@@ -3875,7 +3875,7 @@ m68hc11_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP,
const relax_typeS *table = TC_GENERIC_RELAX_TABLE;
/* We only have to cope with frags as prepared by
- md_estimate_size_before_relax. The STATE_BITS16 case may geet here
+ md_estimate_size_before_relax. The STATE_BITS16 case may get here
because of the different reasons that it's not relaxable. */
switch (fragP->fr_subtype)
{
diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c
index d3212d0..04e57f4 100644
--- a/gas/config/tc-m68k.c
+++ b/gas/config/tc-m68k.c
@@ -138,7 +138,7 @@ static struct label_line *current_label;
/* Pointer to list holding the opcodes sorted by name. */
static struct m68k_opcode const ** m68k_sorted_opcodes;
-/* Its an arbitrary name: This means I don't approve of it.
+/* It's an arbitrary name: This means I don't approve of it.
See flames below. */
static struct obstack robyn;
@@ -369,7 +369,7 @@ struct m68k_it
}
fragb[4];
- int nrel; /* Num of reloc strucs in use. */
+ int nrel; /* Num of reloc structs in use. */
struct
{
int n;
@@ -1504,7 +1504,7 @@ m68k_ip (char *instring)
opsfound = opP - &the_ins.operands[0];
/* This ugly hack is to support the floating pt opcodes in their
- standard form. Essentially, we fake a first enty of type COP#1 */
+ standard form. Essentially, we fake a first entry of type COP#1 */
if (opcode->m_operands[0] == 'I')
{
int n;
@@ -2470,7 +2470,7 @@ m68k_ip (char *instring)
int use_pl = 0;
/* This switch is a doozy.
- Watch the first step; its a big one! */
+ Watch the first step; it's a big one! */
switch (s[0])
{
@@ -2794,7 +2794,7 @@ m68k_ip (char *instring)
default:
abort ();
}
- /* IF its simple,
+ /* IF it's simple,
GET US OUT OF HERE! */
/* Must be INDEX, with an index register. Address
@@ -3735,7 +3735,7 @@ m68k_ip (char *instring)
}
}
- /* By the time whe get here (FINALLY) the_ins contains the complete
+ /* By the time when get here (FINALLY) the_ins contains the complete
instruction, ready to be emitted. . . */
}
@@ -3924,7 +3924,7 @@ install_gen_operand (int mode, int val)
switch (mode)
{
case '/': /* Special for mask loads for mac/msac insns with
- possible mask; trailing_ampersend set in bit 8. */
+ possible mask; trailing_ampersand set in bit 8. */
the_ins.opcode[0] |= (val & 0x3f);
the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
break;
@@ -4432,7 +4432,7 @@ md_assemble (char *str)
n = 4;
break;
default:
- as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
+ as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
the_ins.reloc[m].wid);
}
@@ -5478,7 +5478,7 @@ md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
#endif
-/* Different values of OK tell what its OK to return. Things that
+/* Different values of OK tell what it's OK to return. Things that
aren't OK are an error (what a shock, no?)
0: Everything is OK
@@ -7731,7 +7731,7 @@ md_show_usage (FILE *stream)
"), default_cpu);
for (i = 0; m68k_extensions[i].name; i++)
fprintf (stream, _("\
--m[no-]%-16s enable/disable%s architecture extension\n\
+-m[no-]%-16s enable/disable %s architecture extension\n\
"), m68k_extensions[i].name,
m68k_extensions[i].alias > 0 ? " ColdFire"
: m68k_extensions[i].alias < 0 ? " m68k" : "");
diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c
index 2c9b2c2..2ffb241 100644
--- a/gas/config/tc-mcore.c
+++ b/gas/config/tc-mcore.c
@@ -241,7 +241,7 @@ check_literals (int kind, int offset)
kind == 2 means we just left a function
The dump_literals (1) call inserts a branch around the table, so
- we first look to see if its a situation where we won't have to
+ we first look to see if it's a situation where we won't have to
insert a branch (e.g., the previous instruction was an unconditional
branch).
@@ -1993,7 +1993,7 @@ md_apply_fix (fixS * fixP,
case BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2:
/* Conditional linker map jsri to bsr. */
- /* If its a local target and close enough, fix it.
+ /* If it's a local target and close enough, fix it.
NB: >= -2k for backwards bsr; < 2k for forwards... */
if (fixP->fx_addsy == 0 && val >= -2048 && val < 2048)
{
@@ -2042,7 +2042,7 @@ md_apply_fix (fixS * fixP,
void
md_operand (expressionS * expressionP)
{
- /* Ignore leading hash symbol, if poresent. */
+ /* Ignore leading hash symbol, if present. */
if (* input_line_pointer == '#')
{
input_line_pointer ++;
@@ -2080,7 +2080,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment_type)
sized - maybe it will fix up */
fragP->fr_subtype = C (COND_JUMP, DISP12);
else if (fragP->fr_symbol)
- /* Its got a segment, but its not ours, so it will always be long. */
+ /* It's got a segment, but it's not ours, so it will always be long. */
fragP->fr_subtype = C (COND_JUMP, UNDEF_WORD_DISP);
else
/* We know the abs value. */
@@ -2181,7 +2181,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
code = fixp->fx_r_type;
as_bad (_("Can not do %d byte %srelocation"),
fixp->fx_size,
- fixp->fx_pcrel ? _("pc-relative") : "");
+ fixp->fx_pcrel ? _("pc-relative ") : "");
}
break;
}
diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c
index 6a53013..4a03c5b 100644
--- a/gas/config/tc-mep.c
+++ b/gas/config/tc-mep.c
@@ -442,7 +442,7 @@ mep_machine (void)
/* The MeP version of the cgen parse_operand function. The only difference
from the standard version is that we want to avoid treating '$foo' and
'($foo...)' as references to a symbol called '$foo'. The chances are
- that '$foo' is really a misspelt register. */
+ that '$foo' is really a misspelled register. */
static const char *
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
@@ -582,7 +582,7 @@ mep_check_parallel32_scheduling (void)
an internally parallel core or an internally parallel coprocessor,
neither of which are supported at this time. */
if ( num_insns_saved > 2 )
- as_fatal("Internally paralled cores and coprocessors not supported.");
+ as_fatal("Internally paralleled cores and coprocessors not supported.");
/* If there are no insns saved, that's ok. Just return. This will
happen when mep_process_saved_insns is called when the end of the
@@ -621,7 +621,7 @@ mep_check_parallel32_scheduling (void)
1. The instruction is a 32 bit core or coprocessor insn and
can be executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
@@ -657,7 +657,7 @@ mep_check_parallel32_scheduling (void)
mep_insn insn;
/* Move the insn and it's fixups to the second element of the
- saved insns arrary and insert a 16 bit core nope into the
+ saved insns array and insert a 16 bit core nope into the
first element. */
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
&insn.fields, insn.buffer,
@@ -758,7 +758,7 @@ mep_check_parallel64_scheduling (void)
1. The instruction is a 64 bit coprocessor insn and can be
executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
@@ -773,7 +773,7 @@ mep_check_parallel64_scheduling (void)
we have to abort. */
/* If the insn is 64 bits long, it can run alone. The size check
- is done indepependantly of whether the insn is core or copro
+ is done independently of whether the insn is core or copro
in case 64 bit coprocessor insns are added later. */
if (insn0length == 64)
return;
@@ -1145,7 +1145,7 @@ mep_check_ivc2_scheduling (void)
#endif /* MEP_IVC2_SUPPORTED */
/* The scheduling functions are just filters for invalid combinations.
- If there is a violation, they terminate assembly. Otherise they
+ If there is a violation, they terminate assembly. Otherwise they
just fall through. Successful combinations cause no side effects
other than valid nop insertion. */
@@ -1800,7 +1800,7 @@ mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
break;
}
- /* Now call cgen's md_aply_fix. */
+ /* Now call cgen's md_apply_fix. */
gas_cgen_md_apply_fix (fixP, valP, seg);
}
diff --git a/gas/config/tc-mep.h b/gas/config/tc-mep.h
index e67f31b..48c74ed 100644
--- a/gas/config/tc-mep.h
+++ b/gas/config/tc-mep.h
@@ -115,6 +115,6 @@ extern flagword mep_elf_section_flags (flagword, bfd_vma, int);
/* The values of the following enum are for use with parinsnum, which
is a variable in md_assemble that keeps track of whether or not the
- next instruction is expected to be the first or second instrucion in
+ next instruction is expected to be the first or second instruction in
a parallelization group. */
typedef enum exp_par_insn_{FIRST, SECOND} EXP_PAR_INSN;
diff --git a/gas/config/tc-metag.c b/gas/config/tc-metag.c
index 3aff54a..dd67dcc 100644
--- a/gas/config/tc-metag.c
+++ b/gas/config/tc-metag.c
@@ -635,7 +635,7 @@ parse_addr_op (const char *line, metag_addr *addr)
return NULL;
}
-/* Parse the immediate portion of an addrssing mode. */
+/* Parse the immediate portion of an addressing mode. */
static const char *
parse_imm_addr (const char *line, metag_addr *addr)
{
@@ -4099,7 +4099,7 @@ __parse_dsp_reg (const char *line, const metag_reg **reg, htab_t dsp_regtab)
/* We don't entirely strip the register name because we might
actually want to match whole string in the register table,
e.g. "D0AW.1++" not just "D0AW.1". The string length of the table
- entry limits our comaprison to a reasonable bound anyway. */
+ entry limits our comparison to a reasonable bound anyway. */
while (is_register_char (*l) || *l == PLUS)
{
name[len] = *l;
@@ -5506,7 +5506,7 @@ parse_dalu (const char *line, metag_insn *insn,
insn->bits |= (1 << 2);
}
- /* Check for template definitons. */
+ /* Check for template definitions. */
if (IS_TEMPLATE_DEF (insn))
{
l = interpret_template_regs(l, insn, regs, regs_shift, &load,
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index 588f060..c3b091f 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -626,7 +626,7 @@ struct imm_type {
int otype; /* Offset Type */
};
-/* These are NOT in assending order of type, GOTOFF is ahead to make
+/* These are NOT in ascending order of type, GOTOFF is ahead to make
sure @GOTOFF does not get matched with @GOT */
static struct imm_type imm_types[] = {
{ "NONE", IMM_NONE , 0 },
@@ -2428,7 +2428,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
code = fixp->fx_r_type;
as_bad (_("Can not do %d byte %srelocation"),
fixp->fx_size,
- fixp->fx_pcrel ? _("pc-relative") : "");
+ fixp->fx_pcrel ? _("pc-relative ") : "");
}
break;
}
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 1487e73..02a4e22 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -5031,7 +5031,7 @@ match_int_operand (struct mips_arg_info *arg,
return FALSE;
if (offset_reloc[0] != BFD_RELOC_UNUSED)
- /* Relocation operators were used. Accept the arguent and
+ /* Relocation operators were used. Accept the argument and
leave the relocation value in offset_expr and offset_relocs
for the caller to process. */
return TRUE;
@@ -8608,7 +8608,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
{
/* Search until we get a match for NAME. It is assumed here that
macros will never generate MDMX, MIPS-3D, or MT instructions.
- We try to match an instruction that fulfils the branch delay
+ We try to match an instruction that fulfills the branch delay
slot instruction length requirement (if any) of the previous
instruction. While doing this we record the first instruction
seen that matches all the other conditions and use it anyway
@@ -9514,7 +9514,7 @@ move_register (int dest, int source)
LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
The two alternatives are:
- Global symbol Local sybmol
+ Global symbol Local symbol
------------- ------------
lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
... ...
@@ -17618,11 +17618,11 @@ mips_fix_adjustable (fixS *fixp)
is then identified by the section offset rather than by the symbol.
However, if we're generating REL LO16 relocations, the offset is split
- between the LO16 and parterning high part relocation. The linker will
+ between the LO16 and partnering high part relocation. The linker will
need to recalculate the complete offset in order to correctly identify
the merge data.
- The linker has traditionally not looked for the parterning high part
+ The linker has traditionally not looked for the partnering high part
relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
placed anywhere. Rather than break backwards compatibility by changing
this, it seems better not to force the issue, and instead keep the
diff --git a/gas/config/tc-mmix.c b/gas/config/tc-mmix.c
index 0d714b0..98451bb 100644
--- a/gas/config/tc-mmix.c
+++ b/gas/config/tc-mmix.c
@@ -1943,7 +1943,7 @@ s_prefix (int unused ATTRIBUTE_UNUSED)
c = get_symbol_name (&p);
- /* Reseting prefix? */
+ /* Resetting prefix? */
if (*p == ':' && p[1] == 0)
mmix_current_prefix = NULL;
else
diff --git a/gas/config/tc-mn10200.c b/gas/config/tc-mn10200.c
index e99a86c..344680f 100644
--- a/gas/config/tc-mn10200.c
+++ b/gas/config/tc-mn10200.c
@@ -133,7 +133,7 @@ static const struct reg_name other_registers[] =
(sizeof (other_registers) / sizeof (struct reg_name))
/* reg_name_search does a binary search of the given register table
- to see if "name" is a valid regiter name. Returns the register
+ to see if "name" is a valid register name. Returns the register
number from the array on success, or -1 on failure. */
static int
diff --git a/gas/config/tc-mn10300.c b/gas/config/tc-mn10300.c
index ff4abc7..3f470e5 100644
--- a/gas/config/tc-mn10300.c
+++ b/gas/config/tc-mn10300.c
@@ -284,7 +284,7 @@ static const struct reg_name other_registers[] =
#define OTHER_REG_NAME_CNT ARRAY_SIZE (other_registers)
/* Perform a binary search of the given register table REGS to see
- if NAME is a valid regiter name. Returns the register number from
+ if NAME is a valid register name. Returns the register number from
the array on success, or -1 on failure. */
static int
@@ -2422,7 +2422,7 @@ mn10300_fix_adjustable (struct fix *fixp)
/* Likewise, do not adjust symbols that won't be merged, or debug
symbols, because they too break relaxation. We do want to adjust
- other mergable symbols, like .rodata, because code relaxations
+ other mergeable symbols, like .rodata, because code relaxations
need section-relative symbols to properly relax them. */
if (! (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE))
return FALSE;
diff --git a/gas/config/tc-msp430.c b/gas/config/tc-msp430.c
index 87a774f..a24771b 100644
--- a/gas/config/tc-msp430.c
+++ b/gas/config/tc-msp430.c
@@ -294,7 +294,7 @@ target_is_430xv2 (void)
? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
/* Generate a 16-bit pc-relative relocation.
- For the 430X we generate a relocation without linkwer range checking.
+ For the 430X we generate a relocation without linker range checking.
For the 430 we generate a relocation without assembler range checking
if we are handling an immediate value or a byte-width instruction. */
#undef CHECK_RELOC_MSP430_PCREL
@@ -1878,7 +1878,7 @@ msp430_srcoperand (struct msp430_operand_s * op,
else
{
as_bad (_
- ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
+ ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
l);
return 1;
}
@@ -2538,7 +2538,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
instruction that does not support it. Look for an alternative extended
instruction that has the same name without the period. Eg: "add.a"
becomes "adda". Although this not an officially supported way of
- specifing instruction aliases other MSP430 assemblers allow it. So we
+ specifying instruction aliases other MSP430 assemblers allow it. So we
support it for compatibility purposes. */
if (addr_op && opcode->fmt >= 0)
{
@@ -3092,7 +3092,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
parse_exp (l1 + 1, &(op1.exp));
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
@@ -3163,7 +3163,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
parse_exp (l1 + 1, &(op1.exp));
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
@@ -3372,7 +3372,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
break;
default:
- as_bad (_("Illegal emulated instruction "));
+ as_bad (_("Illegal emulated instruction"));
break;
}
break;
@@ -3743,7 +3743,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
if (x > 512 || x < -511)
{
- as_bad (_("Wrong displacement %d"), x << 1);
+ as_bad (_("Wrong displacement %d"), x << 1);
break;
}
@@ -3902,7 +3902,7 @@ md_assemble (char * str)
if (!cmd[0])
{
- as_bad (_("can't find opcode "));
+ as_bad (_("can't find opcode"));
return;
}
@@ -4225,7 +4225,7 @@ tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp)
because there can be multiple incarnations of the same label, with
exactly the same name, in any given section and the linker will have
no way to identify the correct one. Instead we just have to hope
- that no relaxtion will occur between the local label and the other
+ that no relaxation will occur between the local label and the other
symbol in the expression.
Similarly we have to compute differences between symbols in the .eh_frame
@@ -4345,7 +4345,7 @@ md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
}
else if (fragP->fr_symbol)
{
- /* Its got a segment, but its not ours. Even if fr_symbol is in
+ /* It's got a segment, but it's not ours. Even if fr_symbol is in
an absolute segment, we don't know a displacement until we link
object files. So it will always be long. This also applies to
labels in a subsegment of current. Liker may relax it to short
@@ -4506,7 +4506,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
break;
default:
- as_fatal (_("internal inconsistency problem in %s: %lx"),
+ as_fatal (_("internal inconsistency problem in %s: %lx"),
__FUNCTION__, (long) fragP->fr_subtype);
break;
}
diff --git a/gas/config/tc-msp430.h b/gas/config/tc-msp430.h
index 2a8922b..6789a1e 100644
--- a/gas/config/tc-msp430.h
+++ b/gas/config/tc-msp430.h
@@ -130,7 +130,7 @@ extern int msp430_enable_polys;
#define tc_fix_adjustable(FIX) msp430_fix_adjustable (FIX)
extern bfd_boolean msp430_fix_adjustable (struct fix *);
-/* Allow hexadeciaml numbers with 'h' suffix. Note that if the number
+/* Allow hexadecimal numbers with 'h' suffix. Note that if the number
starts with a letter it will be interpreted as a symbol name not a
constant. Thus "beach" is a symbol not the hex value 0xbeac. So
is A5A5h... */
diff --git a/gas/config/tc-nds32.c b/gas/config/tc-nds32.c
index 3d8034e..19431b4 100644
--- a/gas/config/tc-nds32.c
+++ b/gas/config/tc-nds32.c
@@ -3409,24 +3409,24 @@ nds32_seg (int i)
}
/* Set if label adjustment is needed. I should not adjust .xbyte in dwarf. */
-static symbolS *nds32_last_label; /* Last label for aligment. */
+static symbolS *nds32_last_label; /* Last label for alignment. */
-/* This code is referred from D30V for adjust label to be with pedning
- aligment. For example,
+/* This code is referred from D30V for adjust label to be with pending
+ alignment. For example,
LBYTE: .byte 0x12
LHALF: .half 0x12
LWORD: .word 0x12
- Without this, the above label will not attatch to incoming data. */
+ Without this, the above label will not attach to incoming data. */
static void
nds32_adjust_label (int n)
{
- /* FIXME: I think adjust lable and alignment is
- the programmer's obligation. Saddly, VLSI team doesn't
+ /* FIXME: I think adjust label and alignment is
+ the programmer's obligation. Sadly, VLSI team doesn't
properly use .align for their test cases.
So I re-implement cons_align and auto adjust labels, again.
- I think d30v's implmentation is simple and good enough. */
+ I think d30v's implementation is simple and good enough. */
symbolS *label = nds32_last_label;
nds32_last_label = NULL;
@@ -3493,7 +3493,7 @@ nds32_cons_align (int size ATTRIBUTE_UNUSED)
There are two things should be done for auto-adjust-label.
1. Align data/instructions and adjust label to be attached to them.
- 2. Clear auto-adjust state, so incommng data/instructions will not
+ 2. Clear auto-adjust state, so incoming data/instructions will not
adjust the label.
For example,
@@ -3919,7 +3919,7 @@ nds32_pre_do_align (int n, char *fill, int len, int max)
fragP = frag_now;
frag_align_code (n, max);
- /* Tag this alignment when there is a lable before it. */
+ /* Tag this alignment when there is a label before it. */
if (label_exist)
{
fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
@@ -4011,7 +4011,7 @@ md_begin (void)
asm_desc.parse_operand = nds32_asm_parse_operand;
nds32_asm_init (&asm_desc, 0);
- /* Initial general pupose registers hash table. */
+ /* Initial general purpose registers hash table. */
nds32_gprs_hash = hash_new ();
for (k = keyword_gpr; k->name; k++)
hash_insert (nds32_gprs_hash, k->name, k);
@@ -4656,7 +4656,7 @@ static struct nds32_hint_map hint_map [] =
},
{
/* LONGJUMP5. */
- /* There is two kinds of veriation of LONGJUMP5. One of them
+ /* There is two kinds of variations of LONGJUMP5. One of them
generate EMPTY relocation for converted INSN16 if needed.
But we don't distinguish them here. */
_dummy_first_bfd_reloc_code_real,
@@ -4816,7 +4816,7 @@ nds32_find_reloc_table (struct nds32_relocs_pattern *relocs_pattern,
if (map_ptr->insn_list == 0)
{
- as_warn (_("Can not find match relax hint. line : %d"),
+ as_warn (_("Can not find match relax hint. Line: %d"),
relocs_pattern->frag->fr_line);
return FALSE;
}
@@ -4868,7 +4868,7 @@ nds32_find_reloc_table (struct nds32_relocs_pattern *relocs_pattern,
}
/* Clear final relocation. */
memset (hint_fixup, 0, sizeof (nds32_relax_fixup_info_t));
- /* Copy code sequance. */
+ /* Copy code sequence. */
memcpy (hint_code, code_seq, seq_size);
return TRUE;
}
@@ -5150,7 +5150,7 @@ nds32_check_insn_available (struct nds32_asm_insn insn, const char *str)
if ((baseline_isa & attr) == 0)
{
- as_bad (_("Not support instrcution %s in the baseline."), str);
+ as_bad (_("Instruction %s not supported in the baseline."), str);
return FALSE;
}
return TRUE;
@@ -5247,7 +5247,7 @@ md_assemble (char *str)
{
/* User assembly code branch relax for it. */
/* If fld is not NULL, it is a symbol. */
- /* Branch msut relax to proper pattern in user assembly code exclude
+ /* Branch must relax to proper pattern in user assembly code exclude
J and JAL. Keep these two in original type for users which wants
to keep their size be fixed. In general, assembler does not convert
instruction generated by compiler. But jump instruction may be
@@ -5304,7 +5304,7 @@ md_assemble (char *str)
fragP->tc_frag_data.insn = insn.insn;
fragP->fr_fix += 2;
- /* In original, we don't relax the instrucion with label on it,
+ /* In original, we don't relax the instruction with label on it,
but this may cause some redundant nop16. Therefore, tag this
relaxable instruction and relax it carefully. */
if (label)
@@ -5322,7 +5322,7 @@ md_assemble (char *str)
expressionS exp;
out = frag_var (rs_machine_dependent, insn.opcode->isize,
0, 0, NULL, 0, NULL);
- /* If this insturction is branch target, it is not relaxable. */
+ /* If this instruction is branch target, it is not relaxable. */
fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
fragP->tc_frag_data.opcode = insn.opcode;
fragP->tc_frag_data.insn = insn.insn;
@@ -5478,7 +5478,7 @@ nds32_convert_to_range_type (long offset)
return range_type;
}
-/* Set insntruction register mask. */
+/* Set instruction register mask. */
static void
nds32_elf_get_set_cond (relax_info_t *relax_info, int offset, uint32_t *insn,
@@ -5529,7 +5529,7 @@ nds32_relax_branch_instructions (segT segment, fragS *fragP,
if (fragP->fr_symbol == NULL)
return adjust;
- /* If frag_var is not enough room, the previos frag is fr_full and with
+ /* If frag_var is not enough room, the previous frag is fr_full and with
opcode. The new one is rs_dependent but without opcode. */
if (opcode == NULL)
return adjust;
@@ -5659,13 +5659,13 @@ invalid_prev_frag (fragS * fragP, fragS **prev_frag)
|| frag_t->fr_type == rs_align_code
|| frag_t->fr_type == rs_align_test)
{
- /* Relax instruction can not walk across lable. */
+ /* Relax instruction can not walk across label. */
if (frag_t->tc_frag_data.flag & NDS32_FRAG_LABEL)
{
prev_frag = NULL;
return;
}
- /* Relax previos relaxable to align rs_align frag. */
+ /* Relax previous relaxable to align rs_align frag. */
address = frag_t->fr_address + frag_t->fr_fix;
addressT offset = nds32_get_align (address, (int) frag_t->fr_offset);
if (offset & 0x2)
@@ -5720,8 +5720,8 @@ nds32_relax_frag (segT segment, fragS *fragP, long stretch ATTRIBUTE_UNUSED)
if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXABLE
&& (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED) == 0)
/* Here is considered relaxed case originally. But it may cause
- unendless loop when relaxing. Once the instruction is relaxed,
- it can not be undo. */
+ an endless loop when relaxing. Once the instruction is relaxed,
+ it can not be undone. */
prev_frag = fragP;
return adjust;
@@ -5744,7 +5744,7 @@ md_estimate_size_before_relax (fragS *fragP, segT segment)
1. relax for branch
2. relax for 32-bits to 16-bits */
- /* Save previos relaxable frag. */
+ /* Save previous relaxable frag. */
static fragS *prev_frag = NULL;
int adjust = 0;
@@ -5803,7 +5803,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragP)
if (branch_symbol == NULL && !(fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED))
return;
- /* If frag_var is not enough room, the previos frag is fr_full and with
+ /* If frag_var is not enough room, the previous frag is fr_full and with
opcode. The new one is rs_dependent but without opcode. */
if (opcode == NULL)
return;
@@ -5921,7 +5921,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragP)
origin_insn, branch_range_type);
/* Try to convert to 16-bits instruction. Currently, only the first
- insntruction in pattern can be converted. EX: bnez sethi ori jr,
+ instruction in pattern can be converted. EX: bnez sethi ori jr,
only bnez can be converted to 16 bit and ori can't. */
while (fixup_info[k].size != 0
@@ -6224,7 +6224,7 @@ nds32_insert_relax_entry (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
else
{
/* These flags are only enabled when global relax is enabled.
- Maybe we can check DISABLE_RELAX_FLAG at linke-time,
+ Maybe we can check DISABLE_RELAX_FLAG at link-time,
so we set them anyway. */
if (enable_relax_ex9)
exp.X_add_number |= R_NDS32_RELAX_ENTRY_EX9_FLAG;
@@ -6464,7 +6464,7 @@ nds32_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
fixP->tc_fix_data = NULL;
/* Transform specific relocations here for later relocation generation.
- Tag data here for ex9 relaxtion and tag tls data for linker. */
+ Tag data here for ex9 relaxation and tag tls data for linker. */
switch (fixP->fx_r_type)
{
case BFD_RELOC_NDS32_DATA:
@@ -6519,7 +6519,7 @@ nds32_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
---- 8< ---- 8< ---- 8< ---- 8< ----
We use a single relocation entry for this expression.
- * The initial distance value is stored direcly in that location
+ * The initial distance value is stored directly in that location
specified by r_offset (i.e., foo in this example.)
* The begin of the region, i.e., .LBEGIN, is specified by
r_info/R_SYM and r_addend, e.g., .text + 0x32.
@@ -6686,7 +6686,7 @@ nds32_parse_name (char const *name, expressionS *exprP,
exprP->X_op = O_symbol;
exprP->X_add_number = 0;
- /* Check the specail name if a symbol. */
+ /* Check the special name if a symbol. */
segment = S_GET_SEGMENT (exprP->X_add_symbol);
if (segment != undefined_section)
return 0;
diff --git a/gas/config/tc-nds32.h b/gas/config/tc-nds32.h
index 95eaf8a..08f097c 100644
--- a/gas/config/tc-nds32.h
+++ b/gas/config/tc-nds32.h
@@ -168,7 +168,7 @@ struct nds32_frag_type
relax_substateT flag;
struct nds32_opcode *opcode;
uint32_t insn;
- /* To Save previos label fixup if existence. */
+ /* To Save previous label fixup if existence. */
struct fix *fixup;
};
@@ -252,7 +252,7 @@ typedef struct nds32_cond_field
/* The max relaxation pattern is 20-bytes including the nop. */
#define NDS32_MAXCHAR 20
-/* In current, the max entend number of instruction for one pseudo instruction
+/* In current, the max extended number of instruction for one pseudo instruction
is 4, but its number of relocation may be 12. */
#define MAX_RELAX_NUM 4
#define MAX_RELAX_FIX 12
diff --git a/gas/config/tc-nios2.c b/gas/config/tc-nios2.c
index f3431ca..4ac3eaa 100644
--- a/gas/config/tc-nios2.c
+++ b/gas/config/tc-nios2.c
@@ -727,8 +727,8 @@ const pseudo_typeS md_pseudo_table[] = {
#define CDX_CBRANCH_SUBTYPE(N) (CDXBRANCH | CBRANCH | (N))
#define SUBTYPE_ADDIS(SUBTYPE) ((SUBTYPE) & 0xffff)
-/* For the -relax-section mode, unconditional branches require 2 extra i
- nstructions besides the addis, conditional branches require 3. */
+/* For the -relax-section mode, unconditional branches require 2 extra
+ instructions besides the addis, conditional branches require 3. */
#define UBRANCH_ADDIS_TO_SIZE(N) (((N) + 2) * 4)
#define CBRANCH_ADDIS_TO_SIZE(N) (((N) + 3) * 4)
@@ -3246,7 +3246,7 @@ nios2_translate_pseudo_insn (nios2_insn_infoS *insn)
nios2_ps_insn_infoS *ps_insn;
- /* Find which real insn the pseudo-op transates to and
+ /* Find which real insn the pseudo-op translates to and
switch the insn_info ptr to point to it. */
ps_insn = nios2_ps_lookup (insn->insn[...]
[diff truncated at 100000 bytes]