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[binutils-gdb] MIPS16: Add ASMACRO instruction support
- From: Maciej W.Rozycki <macro at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 23 Dec 2016 20:19:22 -0000
- Subject: [binutils-gdb] MIPS16: Add ASMACRO instruction support
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5284e471d53ccb7c7a1d140bd83098607ccf4b8a
commit 5284e471d53ccb7c7a1d140bd83098607ccf4b8a
Author: Maciej W. Rozycki <macro@imgtec.com>
Date: Fri Dec 23 19:40:51 2016 +0000
MIPS16: Add ASMACRO instruction support
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Diff:
---
binutils/ChangeLog | 5 +++++
.../binutils-all/mips/mips16-extend-insn.d | 12 ++++--------
gas/ChangeLog | 8 ++++++++
gas/testsuite/gas/mips/mips.exp | 2 ++
gas/testsuite/gas/mips/mips16-32@mips16-asmacro.d | 21 +++++++++++++++++++++
gas/testsuite/gas/mips/mips16-64@mips16-asmacro.d | 21 +++++++++++++++++++++
gas/testsuite/gas/mips/mips16-asmacro.d | 14 ++++++++++++++
gas/testsuite/gas/mips/mips16-asmacro.s | 13 +++++++++++++
include/ChangeLog | 5 +++++
include/opcode/mips.h | 10 ++++++++--
opcodes/ChangeLog | 6 ++++++
opcodes/mips16-opc.c | 9 +++++++++
12 files changed, 116 insertions(+), 10 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index f378262..279e98c 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,10 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+ * testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
+ ASMACRO support.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
diff --git a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d
index fc170c6..ef4f5a4 100644
--- a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d
+++ b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d
@@ -198,14 +198,10 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> f123 d0c0 sw s0,6432\(sp\)
[0-9a-f]+ <[^>]*> f123 d0e0 sw s0,6432\(sp\)
[0-9a-f]+ <[^>]*> f123 d800 sw s0,6432\(s0\)
-[0-9a-f]+ <[^>]*> f123 extend 0x123
-[0-9a-f]+ <[^>]*> e000 daddu s0,s0
-[0-9a-f]+ <[^>]*> f123 extend 0x123
-[0-9a-f]+ <[^>]*> e001 addu s0,s0
-[0-9a-f]+ <[^>]*> f123 extend 0x123
-[0-9a-f]+ <[^>]*> e002 dsubu s0,s0
-[0-9a-f]+ <[^>]*> f123 extend 0x123
-[0-9a-f]+ <[^>]*> e003 subu s0,s0
+[0-9a-f]+ <[^>]*> f123 e000 asmacro 0x1,0x0,0x0,0x0,0x3,0x1
+[0-9a-f]+ <[^>]*> f123 e001 asmacro 0x1,0x1,0x0,0x0,0x3,0x1
+[0-9a-f]+ <[^>]*> f123 e002 asmacro 0x1,0x2,0x0,0x0,0x3,0x1
+[0-9a-f]+ <[^>]*> f123 e003 asmacro 0x1,0x3,0x0,0x0,0x3,0x1
[0-9a-f]+ <[^>]*> f123 extend 0x123
[0-9a-f]+ <[^>]*> e800 jr s0
[0-9a-f]+ <[^>]*> f123 extend 0x123
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3a05d78..16575d1 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,13 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+ * testsuite/gas/mips/mips16-asmacro.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
+ * testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
+ * testsuite/gas/mips/mips16-asmacro.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
* config/tc-mips.c (mips16_immed): Limit `mips16_immed_extend'
use to operands whose LSB position is zero.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 678e8d9..0da2df9 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1357,6 +1357,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "mips16-jal-t"
run_dump_test "mips16-jal-e"
+ run_dump_test_arches "mips16-asmacro" [mips_arch_list_matching mips16-32]
+
run_dump_test "vxworks1"
run_dump_test "vxworks1-xgot"
run_dump_test "vxworks1-el"
diff --git a/gas/testsuite/gas/mips/mips16-32@mips16-asmacro.d b/gas/testsuite/gas/mips/mips16-32@mips16-asmacro.d
new file mode 100644
index 0000000..8c50a8c
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-32@mips16-asmacro.d
@@ -0,0 +1,21 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS16 ASMACRO instruction
+#as: -32
+#source: mips16-asmacro.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f000 extend 0x0
+[0-9a-f]+ <[^>]*> e000 0xe000
+[0-9a-f]+ <[^>]*> f0a4 extend 0xa4
+[0-9a-f]+ <[^>]*> e341 addu s0,v1,v0
+[0-9a-f]+ <[^>]*> f0e0 extend 0xe0
+[0-9a-f]+ <[^>]*> e71f subu a3,s0
+[0-9a-f]+ <[^>]*> f501 extend 0x501
+[0-9a-f]+ <[^>]*> e264 0xe264
+[0-9a-f]+ <[^>]*> f71f extend 0x71f
+[0-9a-f]+ <[^>]*> e0e0 0xe0e0
+[0-9a-f]+ <[^>]*> f7ff extend 0x7ff
+[0-9a-f]+ <[^>]*> e7ff subu a3,a3
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/mips16-64@mips16-asmacro.d b/gas/testsuite/gas/mips/mips16-64@mips16-asmacro.d
new file mode 100644
index 0000000..466f411
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-64@mips16-asmacro.d
@@ -0,0 +1,21 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS16 ASMACRO instruction
+#as: -32
+#source: mips16-asmacro.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f000 extend 0x0
+[0-9a-f]+ <[^>]*> e000 daddu s0,s0
+[0-9a-f]+ <[^>]*> f0a4 extend 0xa4
+[0-9a-f]+ <[^>]*> e341 addu s0,v1,v0
+[0-9a-f]+ <[^>]*> f0e0 extend 0xe0
+[0-9a-f]+ <[^>]*> e71f subu a3,s0
+[0-9a-f]+ <[^>]*> f501 extend 0x501
+[0-9a-f]+ <[^>]*> e264 daddu s1,v0,v1
+[0-9a-f]+ <[^>]*> f71f extend 0x71f
+[0-9a-f]+ <[^>]*> e0e0 daddu s0,a3
+[0-9a-f]+ <[^>]*> f7ff extend 0x7ff
+[0-9a-f]+ <[^>]*> e7ff subu a3,a3
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/mips16-asmacro.d b/gas/testsuite/gas/mips/mips16-asmacro.d
new file mode 100644
index 0000000..1a81c84
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-asmacro.d
@@ -0,0 +1,14 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS16 ASMACRO instruction
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f000 e000 asmacro 0x0,0x0,0x0,0x0,0x0,0x0
+[0-9a-f]+ <[^>]*> f0a4 e341 asmacro 0x0,0x1,0x2,0x3,0x4,0x5
+[0-9a-f]+ <[^>]*> f0e0 e71f asmacro 0x0,0x1f,0x0,0x7,0x0,0x7
+[0-9a-f]+ <[^>]*> f501 e264 asmacro 0x5,0x4,0x3,0x2,0x1,0x0
+[0-9a-f]+ <[^>]*> f71f e0e0 asmacro 0x7,0x0,0x7,0x0,0x1f,0x0
+[0-9a-f]+ <[^>]*> f7ff e7ff asmacro 0x7,0x1f,0x7,0x7,0x1f,0x7
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/mips16-asmacro.s b/gas/testsuite/gas/mips/mips16-asmacro.s
new file mode 100644
index 0000000..18d0ce1
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-asmacro.s
@@ -0,0 +1,13 @@
+ .set mips32
+ .set mips16
+foo:
+ asmacro 0, 0, 0, 0, 0, 0
+ asmacro 0, 1, 2, 3, 4, 5
+ asmacro 0, 31, 0, 7, 0, 7
+ asmacro 5, 4, 3, 2, 1, 0
+ asmacro 7, 0, 7, 0, 31, 0
+ asmacro 7, 31, 7, 7, 31, 7
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
diff --git a/include/ChangeLog b/include/ChangeLog
index 04c02ce..99d747f 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+ * opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
+ operand codes.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
`F' respectively.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index e00f682..eb80dfe 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1809,12 +1809,18 @@ extern int bfd_mips_num_opcodes;
"R" return address register ($ra or $31)
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
+ "0" 5-bit ASMACRO p0 immediate
+ "1" 3-bit ASMACRO p1 immediate
+ "2" 3-bit ASMACRO p2 immediate
+ "3" 5-bit ASMACRO p3 immediate
+ "4" 3-bit ASMACRO p4 immediate
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
"a" 26 bit jump address
"i" likewise, but flips bit 0
"e" 11 bit extension value
"l" register list for entry instruction
"L" register list for exit instruction
+ "s" 3-bit ASMACRO select immediate
"I" an immediate value used for macros
@@ -1844,10 +1850,10 @@ extern int bfd_mips_num_opcodes;
"M" 7 bit register list for restore instruction (18 bit extended)
Characters used so far, for quick reference when adding more:
- " 56 8 "
+ "0123456 8 "
".[]<"
"ABCDEF HI KLM P RS UVWXYZ"
- "a e ijklm pq vwxyz"
+ "a e ijklm pq s vwxyz"
*/
/* Save/restore encoding for the args field when all 4 registers are
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 469113f..4f336ce 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+ * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
+ `4' and `s' operand codes.
+ (mips16_opcodes): Add "asmacro" entry.
+
+2016-12-23 Maciej W. Rozycki <macro@imgtec.com>
+
* mips-dis.c (print_mips16_insn_arg): Simplify processing of
extended operands.
* mips16-opc.c (decode_mips16_operand): Switch the extended
diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index d102b8c..134630b 100644
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -51,6 +51,11 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
{
case '.': MAPPED_REG (0, 0, GP, reg_0_map);
+ case '0': HINT (5, 0);
+ case '1': HINT (3, 5);
+ case '2': HINT (3, 8);
+ case '3': HINT (5, 16);
+ case '4': HINT (3, 21);
case '6': UINT (6, 5);
case 'L': SPECIAL (6, 5, ENTRY_EXIT_LIST);
@@ -67,6 +72,7 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
case 'i': JALX (26, 0, 2);
case 'l': SPECIAL (6, 5, ENTRY_EXIT_LIST);
case 'm': SPECIAL (7, 0, SAVE_RESTORE_LIST);
+ case 's': HINT (3, 24);
case 'v': OPTIONAL_MAPPED_REG (3, 8, GP, reg_m16_map);
case 'w': OPTIONAL_MAPPED_REG (3, 5, GP, reg_m16_map);
case 'x': MAPPED_REG (3, 8, GP, reg_m16_map);
@@ -357,6 +363,9 @@ const struct mips_opcode mips16_opcodes[] =
{"zeb", "x", 0xe811, 0xf8ff, MOD_1, SH, I32, 0, 0 },
{"zeh", "x", 0xe831, 0xf8ff, MOD_1, SH, I32, 0, 0 },
{"zew", "x", 0xe851, 0xf8ff, MOD_1, SH, I64, 0, 0 },
+ /* Place asmacro at the bottom so that it catches any implementation
+ specific macros that didn't match anything. */
+{"asmacro", "s,0,1,2,3,4", 0xf000e000, 0xf800f800, 0, 0, I32, 0, 0 },
/* Place EXTEND last so that it catches any prefix that didn't match
anything. */
{"extend", "e", 0xf000, 0xf800, NODS, SH, I1, 0, 0 },