[binutils-gdb] [GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL syntax).

[Renlin Li <renlin at sourceware dot org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5689c9424b33aac68c4762ce0bda09ca7e3affe0

commit 5689c9424b33aac68c4762ce0bda09ca7e3affe0
Author: Renlin Li <renlin.li@arm.com>
Date:   Mon Nov 21 12:06:04 2016 +0000

    [GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL syntax).
    
    gas/
    
    2016-11-21  Renlin Li  <renlin.li@arm.com>
    
    	PR gas/20827
    	* config/tc-arm.c (encode_arm_shift): Don't assert for operands not
    	presented.
    	* testsuite/gas/arm/add-shift-two.d: New.
    	* testsuite/gas/arm/add-shift-two.s: New.

Diff:
---
 gas/ChangeLog                         |  8 ++++++++
 gas/config/tc-arm.c                   |  7 +++++--
 gas/testsuite/gas/arm/add-shift-two.d | 11 +++++++++++
 gas/testsuite/gas/arm/add-shift-two.s |  5 +++++
 4 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 589c986..134f24b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2016-11-21  Renlin Li  <renlin.li@arm.com>
+
+	PR gas/20827
+	* config/tc-arm.c (encode_arm_shift): Don't assert for operands not
+	presented.
+	* testsuite/gas/arm/add-shift-two.d: New.
+	* testsuite/gas/arm/add-shift-two.s: New.
+
 2016-11-21  Alan Modra  <amodra@gmail.com>
 
 	* configure.ac: Invoke ACX_PROG_CMP_IGNORE_INITIAL.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 9a12bcc..e37d354 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7435,8 +7435,11 @@ encode_arm_shift (int i)
       int index;
       for (index = 0; index <= i; ++index)
 	{
-	  gas_assert (inst.operands[index].present);
-	  if (inst.operands[index].isreg && inst.operands[index].reg == REG_PC)
+	  /* Check the operand only when it's presented.  In pre-UAL syntax,
+	     if the destination register is the same as the first operand, two
+	     register form of the instruction can be used.  */
+	  if (inst.operands[index].present && inst.operands[index].isreg
+	      && inst.operands[index].reg == REG_PC)
 	    as_warn (UNPRED_REG ("r15"));
 	}
 
diff --git a/gas/testsuite/gas/arm/add-shift-two.d b/gas/testsuite/gas/arm/add-shift-two.d
new file mode 100644
index 0000000..46a58c5
--- /dev/null
+++ b/gas/testsuite/gas/arm/add-shift-two.d
@@ -0,0 +1,11 @@
+# name: Two register form of data processing instruction with register shifted register operand
+# as:
+# objdump: -dr
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	e0855014 	add	r5, r5, r4, lsl r0
+   4:	e0855014 	add	r5, r5, r4, lsl r0
diff --git a/gas/testsuite/gas/arm/add-shift-two.s b/gas/testsuite/gas/arm/add-shift-two.s
new file mode 100644
index 0000000..72560cd
--- /dev/null
+++ b/gas/testsuite/gas/arm/add-shift-two.s
@@ -0,0 +1,5 @@
+	.arch armv7-a
+	.text
+	# PR 20827
+	add r5, r4, lsl r0
+	add r5, r5, r4, lsl r0