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[binutils-gdb] [AArch64] Add V8_2_INSN macro
- From: Richard Sandiford <rsandifo at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 23 Aug 2016 08:04:50 -0000
- Subject: [binutils-gdb] [AArch64] Add V8_2_INSN macro
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=344bde0a7f812ff03139ab53aecd61674eb143bf
commit 344bde0a7f812ff03139ab53aecd61674eb143bf
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Tue Aug 23 09:03:19 2016 +0100
[AArch64] Add V8_2_INSN macro
For consistency with the previous two patches, this one
adds a macro for the two ARMv8.2 table entries. Both table
entries need a non-null aarch64_op field.
I haven't added macros for the RAS and STAT_PROFILE entries
since there's only one of each. The series isn't getting
rid of braced entries altogether, so I've only looked at
replacing things that occur more than once.
opcodes/
* aarch64-tbl.h (V8_2_INSN): New macro.
(aarch64_opcode_table): Use it.
Diff:
---
opcodes/ChangeLog | 5 +++++
opcodes/aarch64-tbl.h | 6 ++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 07dbfc9..b5dbc41 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
+ * aarch64-tbl.h (V8_2_INSN): New macro.
+ (aarch64_opcode_table): Use it.
+
+2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
+
* aarch64-tbl.h (aarch64_opcode_table): Make more use of
CORE_INSN, __FP_INSN and SIMD_INSN.
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7dd704a..b82678f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1412,6 +1412,8 @@ static const aarch64_feature_set aarch64_feature_stat_profile =
{ NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, NULL }
#define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, NULL }
+#define V8_2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2, OPS, QUALS, FLAGS, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{
@@ -2062,7 +2064,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV),
CORE_INSN ("bfm", 0x33000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
CORE_INSN ("bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
- {"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV, NULL},
+ V8_2_INSN ("bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV),
CORE_INSN ("bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
CORE_INSN ("ubfm", 0x53000000, 0x7f800000, bitfield, 0, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N),
CORE_INSN ("ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV),
@@ -2123,7 +2125,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
CORE_INSN ("rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEW, 0),
CORE_INSN ("rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1),
- {"rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, ARMV8_2, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS, NULL},
+ V8_2_INSN ("rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS),
CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0),