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[binutils-gdb] Fix generation of AArhc64 instruction table.
- From: Nick Clifton <nickc at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 3 May 2016 10:49:28 -0000
- Subject: [binutils-gdb] Fix generation of AArhc64 instruction table.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=20f55f3866ab70778d08fec2c09626cff9ed781d
commit 20f55f3866ab70778d08fec2c09626cff9ed781d
Author: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Tue May 3 11:48:56 2016 +0100
Fix generation of AArhc64 instruction table.
* aarch64-gen.c (VERIFIER): Define.
* aarch64-opc.c (VERIFIER): Define.
(verify_ldpsw): Use static linkage.
* aarch64-opc.h (verify_ldpsw): Remove.
* aarch64-tbl.h: Use VERIFIER for verifiers.
Diff:
---
opcodes/ChangeLog | 8 ++++++++
opcodes/aarch64-gen.c | 1 +
opcodes/aarch64-opc.c | 3 ++-
opcodes/aarch64-opc.h | 3 ---
opcodes/aarch64-tbl.h | 8 ++++++--
5 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a66e93f..d166325 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-gen.c (VERIFIER): Define.
+ * aarch64-opc.c (VERIFIER): Define.
+ (verify_ldpsw): Use static linkage.
+ * aarch64-opc.h (verify_ldpsw): Remove.
+ * aarch64-tbl.h: Use VERIFIER for verifiers.
+
2016-04-28 Nick Clifton <nickc@redhat.com>
PR target/19722
diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index c106c7d..ed0834a 100644
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -28,6 +28,7 @@
#include "getopt.h"
#include "opcode/aarch64.h"
+#define VERIFIER(x) NULL
#include "aarch64-tbl.h"
static int debug = 0;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 8fbea46..d9a31e8 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3420,7 +3420,7 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
-bfd_boolean
+static bfd_boolean
verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
const aarch64_insn insn)
{
@@ -3447,4 +3447,5 @@ verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
/* Include the opcode description table as well as the operand description
table. */
+#define VERIFIER(x) verify_##x
#include "aarch64-tbl.h"
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index c5bcbb8..08494c6 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -390,7 +390,4 @@ get_logsz (unsigned int size)
return ls[size - 1];
}
-/* Instruction Verifiers. */
-extern bfd_boolean verify_ldpsw (const struct aarch64_opcode *, const aarch64_insn);
-
#endif /* OPCODES_AARCH64_OPC_H */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7a47a17..c223d18 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -21,6 +21,10 @@
#include "aarch64-opc.h"
+#ifndef VERIFIER
+#error VERIFIER must be defined.
+#endif
+
/* Operand type. */
#define OPND(x) AARCH64_OPND_##x
@@ -2383,13 +2387,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, verify_ldpsw},
+ {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)},
/* Load/store register pair (indexed). */
CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, verify_ldpsw},
+ {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, VERIFIER (ldpsw)},
/* Load register (literal). */
{"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q, NULL},
{"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0, NULL},