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[binutils-gdb] opcodes/arc: Add more nps instructions
- From: Andrew Burgess <aburgess at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 19 Apr 2016 21:55:36 -0000
- Subject: [binutils-gdb] opcodes/arc: Add more nps instructions
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c8f785f220bab3c17fc93445ac509495d00d5afe
commit c8f785f220bab3c17fc93445ac509495d00d5afe
Author: Andrew Burgess <andrew.burgess@embecosm.com>
Date: Thu Mar 31 19:51:14 2016 +0100
opcodes/arc: Add more nps instructions
Add dctcp, dcip, dcet, and dcacl instructions.
gas/ChangeLog:
* testsuite/gas/arc/nps400-4.d: New file.
* testsuite/gas/arc/nps400-4.s: New file.
* testsuite/gas/arc/nps400-5.d: New file.
* testsuite/gas/arc/nps400-5.s: New file.
include/ChangeLog:
* opcode/arc.h (insn_class_t): Add NET and ACL class.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
Diff:
---
gas/ChangeLog | 7 +++++++
gas/testsuite/gas/arc/nps400-4.d | 12 ++++++++++++
gas/testsuite/gas/arc/nps400-4.s | 11 +++++++++++
gas/testsuite/gas/arc/nps400-5.d | 10 ++++++++++
gas/testsuite/gas/arc/nps400-5.s | 5 +++++
include/ChangeLog | 4 ++++
include/opcode/arc.h | 2 ++
opcodes/ChangeLog | 4 ++++
opcodes/arc-nps400-tbl.h | 19 +++++++++++++++++++
9 files changed, 74 insertions(+)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index cfd6326..d32792a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * testsuite/gas/arc/nps400-4.d: New file.
+ * testsuite/gas/arc/nps400-4.s: New file.
+ * testsuite/gas/arc/nps400-5.d: New file.
+ * testsuite/gas/arc/nps400-5.s: New file.
+
2016-04-19 Martin Galvan <martin.galvan@tallertechnologies.com>
* doc/as.texinfo (.cfi_remember_state, .cfi_restore_state): Improve
diff --git a/gas/testsuite/gas/arc/nps400-4.d b/gas/testsuite/gas/arc/nps400-4.d
new file mode 100644
index 0000000..2caab8c
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-4.d
@@ -0,0 +1,12 @@
+#as: -mcpu=nps400
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 3a2f 1300 dctcp r10,r12
+ 4: 3e29 13cd dcip r13,r14,r15
+ 8: 382f 2442 dcet r16,r17
+ c: 3b20 2512 dcet r18,r19,r20
diff --git a/gas/testsuite/gas/arc/nps400-4.s b/gas/testsuite/gas/arc/nps400-4.s
new file mode 100644
index 0000000..d2d7814
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-4.s
@@ -0,0 +1,11 @@
+ .text
+
+ /* dctcp */
+ dctcp r10, r12
+
+ /* dcip */
+ dcip r13, r14, r15
+
+ /* dcet */
+ dcet r16, r17
+ dcet r18, r19, r20
diff --git a/gas/testsuite/gas/arc/nps400-5.d b/gas/testsuite/gas/arc/nps400-5.d
new file mode 100644
index 0000000..214e38e
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-5.d
@@ -0,0 +1,10 @@
+#as: -mcpu=nps400
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+ 0: 3925 0080 dcacl r0,r1,r2
+ 4: 3c25 8143 dcacl.f r3,r4,r5
diff --git a/gas/testsuite/gas/arc/nps400-5.s b/gas/testsuite/gas/arc/nps400-5.s
new file mode 100644
index 0000000..38a34c2
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-5.s
@@ -0,0 +1,5 @@
+ .text
+
+ /* dcacl */
+ dcacl r0, r1, r2
+ dcacl.f r3, r4, r5
diff --git a/include/ChangeLog b/include/ChangeLog
index 8c16d79..9bd4a72 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * opcode/arc.h (insn_class_t): Add NET and ACL class.
+
2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
* elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc.
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 2811877..31daeb7 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -47,6 +47,8 @@ typedef enum
LOGICAL,
MEMORY,
BITOP,
+ NET,
+ ACL,
} insn_class_t;
/* Instruction Subclass. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b3b4d6f..f231ea3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
+
2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.in: Regenerated with automake 1.11.6.
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index 832d2ff..ebafc15 100644
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -124,6 +124,25 @@
/* crc32<.r> 0,limm,u6 00111 110 01 110100 R 111 uuuuuu 111110 */
{ "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
+/**** Protocol Decoder Instructions ****/
+
+/* dctcp b,c 00111bbb001011110bbbcccccc000000 */
+{ "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }},
+
+/* dcip a,b,c 00111bbb001011110bbbccccccaaaaaa */
+{ "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }},
+
+/* dcet b,c 00111bbb001011110bbbcccccc000010 */
+{ "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }},
+
+/* dcet a,b,c 00111bbb001000000bbbccccccaaaaaa */
+{ "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }},
+
+/**** ACL Instructions ****/
+
+/* dcacl<.f> a,b,c 00111bbb001001010bbbccccccaaaaaa */
+{ "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_NPS400, ACL, NONE, { RA, RB, RC }, { C_F }},
+
/**** Pipeline Control Instructions ****/
/* schd<.rw|.rd> */