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[binutils-gdb] [OPCODES][ARM]Fix mask for a few coprocessor opcodes.

From: Renlin Li <renlin at sourceware dot org>
To: bfd-cvs at sourceware dot org
Date: 24 Feb 2016 14:03:51 -0000
Subject: [binutils-gdb] [OPCODES][ARM]Fix mask for a few coprocessor opcodes.
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3e309328e8d91e37f2f3cea15f8a686d3bdfa700

commit 3e309328e8d91e37f2f3cea15f8a686d3bdfa700
Author: Renlin Li <renlin.li@arm.com>
Date:   Wed Feb 24 13:55:30 2016 +0000

    [OPCODES][ARM]Fix mask for a few coprocessor opcodes.
    
    opcodes/
    
    2016-02-24  Renlin Li  <renlin.li@arm.com>
    
    	* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
    	vrint(mpna).
    
    gas/
    
    2016-02-24  Renlin Li  <renlin.li@arm.com>
    
    	* testsuite/gas/arm/mask_1.d: New.
    	* testsuite/gas/arm/mask_1.s: New.

Diff:
---
 gas/ChangeLog                  |  5 +++++
 gas/testsuite/gas/arm/mask_1.d | 28 ++++++++++++++++++++++++++++
 gas/testsuite/gas/arm/mask_1.s | 17 +++++++++++++++++
 opcodes/ChangeLog              |  5 +++++
 opcodes/arm-dis.c              | 16 ++++++++--------
 5 files changed, 63 insertions(+), 8 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9efeae4..37c5daa 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
 2016-02-24  Renlin Li  <renlin.li@arm.com>
 
+	* testsuite/gas/arm/mask_1.d: New.
+	* testsuite/gas/arm/mask_1.s: New.
+
+2016-02-24  Renlin Li  <renlin.li@arm.com>
+
 	* testsuite/gas/arm/copro.s: Use coprocessor other than 10, 11.
 	* testsuite/gas/arm/copro.d: Update.
 
diff --git a/gas/testsuite/gas/arm/mask_1.d b/gas/testsuite/gas/arm/mask_1.d
new file mode 100644
index 0000000..eddcd65
--- /dev/null
+++ b/gas/testsuite/gas/arm/mask_1.d
@@ -0,0 +1,28 @@
+#objdump: -dr --prefix-address --show-raw-insn
+#name: vsel, vmaxnm, vminnm, vrint decoding mask.
+#as: -march=armv8-a
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+# Test VFMA instruction disassembly
+
+.*: *file format .*arm.*
+
+
+Disassembly of section .text:
+0+000 <.*> fe011a10 	mcr2	10, 0, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+004 <.*> fe011b10 	mcr2	11, 0, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+008 <.*> fe811a10 	mcr2	10, 4, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+00c <.*> fe811b10 	mcr2	11, 4, r1, cr1, cr0, \{0\}	; <UNPREDICTABLE>
+0+010 <.*> fe811a50 	mcr2	10, 4, r1, cr1, cr0, \{2\}	; <UNPREDICTABLE>
+0+014 <.*> fe811b50 	mcr2	11, 4, r1, cr1, cr0, \{2\}	; <UNPREDICTABLE>
+0+018 <.*> fefb0ae0 			; <UNDEFINED> instruction: 0xfefb0ae0
+0+01c <.*> fefb0be0 			; <UNDEFINED> instruction: 0xfefb0be0
+0+020 <.*> fefb0ae0 			; <UNDEFINED> instruction: 0xfefb0ae0
+0+024 <.*> fefb0be0 			; <UNDEFINED> instruction: 0xfefb0be0
+0+028 <.*> fef80ae0 			; <UNDEFINED> instruction: 0xfef80ae0
+0+02c <.*> fef80be0 			; <UNDEFINED> instruction: 0xfef80be0
+0+030 <.*> fef90ae0 			; <UNDEFINED> instruction: 0xfef90ae0
+0+034 <.*> fef90be0 			; <UNDEFINED> instruction: 0xfef90be0
+0+038 <.*> fefa0ae0 			; <UNDEFINED> instruction: 0xfefa0ae0
+0+03c <.*> fefa0be0 			; <UNDEFINED> instruction: 0xfefa0be0
diff --git a/gas/testsuite/gas/arm/mask_1.s b/gas/testsuite/gas/arm/mask_1.s
new file mode 100644
index 0000000..7a347d8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mask_1.s
@@ -0,0 +1,17 @@
+	.text
+	.inst 0xfe011a10	@ mcr2	10, 0, r1, cr1, cr0, {0}	<UNPREDICTABLE>
+	.inst 0xfe011b10	@ mcr2	11, 0, r1, cr1, cr0, {0}	<UNPREDICTABLE>
+	.inst 0xfe811a10	@ mcr2	10, 4, r1, cr1, cr0, {0}	<UNPREDICTABLE>
+	.inst 0xfe811b10	@ mcr2	11, 4, r1, cr1, cr0, {0}	<UNPREDICTABLE>
+	.inst 0xfe811a50	@ mcr2	10, 4, r1, cr1, cr0, {2}	<UNPREDICTABLE>
+	.inst 0xfe811b50	@ mcr2	11, 4, r1, cr1, cr0, {2}	<UNPREDICTABLE>
+	.inst 0xfefb0ae0	@ <UNDEFINED> instruction: 0xfefb0ae0
+	.inst 0xfefb0be0	@ <UNDEFINED> instruction: 0xfefb0be0
+	.inst 0xfefb0ae0	@ <UNDEFINED> instruction: 0xfefb0ae0
+	.inst 0xfefb0be0	@ <UNDEFINED> instruction: 0xfefb0be0
+	.inst 0xfef80ae0	@ <UNDEFINED> instruction: 0xfef80ae0
+	.inst 0xfef80be0	@ <UNDEFINED> instruction: 0xfef80be0
+	.inst 0xfef90ae0	@ <UNDEFINED> instruction: 0xfef90ae0
+	.inst 0xfef90be0	@ <UNDEFINED> instruction: 0xfef90be0
+	.inst 0xfefa0ae0	@ <UNDEFINED> instruction: 0xfefa0ae0
+	.inst 0xfefa0be0	@ <UNDEFINED> instruction: 0xfefa0be0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 60d2d7d..d58f9de 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2016-02-24  Renlin Li  <renlin.li@arm.com>
 
+	* arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
+	vminnm, vrint(mpna).
+
+2016-02-24  Renlin Li  <renlin.li@arm.com>
+
 	* arm-dis.c (print_insn_coprocessor): Check co-processor number for
 	cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 4960140..6bffc6d 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -820,17 +820,17 @@ static const struct opcode32 coprocessor_opcodes[] =
 
   /* FP v5.  */
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
+    0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
+    0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
+    0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
+    0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
+    0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
+    0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
@@ -840,9 +840,9 @@ static const struct opcode32 coprocessor_opcodes[] =
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
+    0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
-    0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
+    0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 
   /* Generic coprocessor instructions.  */
   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
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