This is the mail archive of the
binutils-cvs@sourceware.org
mailing list for the binutils project.
[binutils-gdb] epiphany/gas: Update expected test results for 0 offset loads
- From: Andrew Burgess <aburgess at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 2 Feb 2016 11:10:25 -0000
- Subject: [binutils-gdb] epiphany/gas: Update expected test results for 0 offset loads
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5d7a901176b95b89deaea10bf184dbb0de0c93cd
commit 5d7a901176b95b89deaea10bf184dbb0de0c93cd
Author: Andrew Burgess <andrew.burgess@embecosm.com>
Date: Mon Feb 1 20:21:19 2016 +0000
epiphany/gas: Update expected test results for 0 offset loads
In commit 02a79b89fdeadccb67048291e6c2a1e5ce6ad623 some of the load
instructions with a zero offset (where the offset is not mentioned) were
marked as NO-DIS, meaning that the disassembler must display the offset,
even though it is zero.
This change seems a little strange to me as it was only applied to some
loads, not all, and the same change was not applied to the stores.
However, I'm reluctant to revert a specific change to the assembler,
when the output is obviously correct. With this commit then I simply
bring the expected assembler test results into line with what is
actually produced.
gas/ChangeLog:
* testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
some load instructions.
* testsuite/gas/epiphany/allinsn.d: Likewise.
* testsuite/gas/epiphany/regression.d: Likewise.
Diff:
---
gas/ChangeLog | 7 +++++++
gas/testsuite/gas/epiphany/addr-syntax.d | 2 +-
gas/testsuite/gas/epiphany/allinsn.d | 20 ++++++++++----------
gas/testsuite/gas/epiphany/regression.d | 6 +++---
4 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7133f6c..a90b3de 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+ * testsuite/gas/epiphany/addr-syntax.d: Add explicit 0 offset to
+ some load instructions.
+ * testsuite/gas/epiphany/allinsn.d: Likewise.
+ * testsuite/gas/epiphany/regression.d: Likewise.
+
+2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+
* testsuite/gas/epiphany/addr-syntax.d: Remove unneeded '.l'
suffixes from instruction mnemonics in expected output.
* testsuite/gas/epiphany/allinsn.d: Likewise.
diff --git a/gas/testsuite/gas/epiphany/addr-syntax.d b/gas/testsuite/gas/epiphany/addr-syntax.d
index 281f4d2..ae3a901 100644
--- a/gas/testsuite/gas/epiphany/addr-syntax.d
+++ b/gas/testsuite/gas/epiphany/addr-syntax.d
@@ -11,5 +11,5 @@ Disassembly of section \.text:
0: 2bcc 01ff ldr r1,\[r2,-0x7ff\]
4: 4c4c 0301 ldr r2,\[r3\],-0x8
8: 107c 2201 strd r8,\[r4\],\+0x8
- c: 506c 2400 ldrd r10,\[r12\]
+ c: 506c 2400 ldrd r10,\[r12,\+0x0\]
10: 587c 2400 strd r10,\[lr\]
diff --git a/gas/testsuite/gas/epiphany/allinsn.d b/gas/testsuite/gas/epiphany/allinsn.d
index b4c84f7..464751d 100644
--- a/gas/testsuite/gas/epiphany/allinsn.d
+++ b/gas/testsuite/gas/epiphany/allinsn.d
@@ -240,7 +240,7 @@ Disassembly of section .text:
1d4: 4c8d e580 ldrb r58,\[fp],\+r25
000001d8 \<ldrbd16\>:
- 1d8: 900c 2400 ldrb r12,\[r12]
+ 1d8: 900c 2400 ldrb r12,\[r12,\+0x0]
1dc: 6f84 ldrb r3,\[r3,0x7]
1de: 0204 ldrb r0,\[r0,0x4]
1e0: 6d8c 2400 ldrb fp,\[fp,\+0x3]
@@ -250,7 +250,7 @@ Disassembly of section .text:
1ee: 2484 ldrb r1,\[r1,0x1]
000001f0 \<ldrbd\>:
- 1f0: 900c 2400 ldrb r12,\[r12]
+ 1f0: 900c 2400 ldrb r12,\[r12,\+0x0]
1f4: 6f8c fcff ldrb r59,\[r59,\+0x7ff]
1f8: 900c 6c80 ldrb r28,\[r28,\+0x400]
1fc: 6f8c 6c7f ldrb r27,\[r27,\+0x3ff]
@@ -289,17 +289,17 @@ Disassembly of section .text:
25c: e1ad 7400 ldrh r31,\[r40],\+r3
00000260 \<ldrhd16\>:
- 260: 902c 2400 ldrh r12,\[r12]
+ 260: 902c 2400 ldrh r12,\[r12,\+0x0]
264: 6fa4 ldrh r3,\[r3,0x7]
266: 0224 ldrh r0,\[r0,0x4]
268: 6dac 2400 ldrh fp,\[fp,\+0x3]
26c: b4ac 2400 ldrh sp,\[sp,\+0x1]
- 270: c82c 2000 ldrh lr,\[r2]
+ 270: c82c 2000 ldrh lr,\[r2,\+0x0]
274: 63a4 ldrh r3,\[r0,0x7]
276: 0f24 ldrh r0,\[r3,0x6]
00000278 \<ldrhd\>:
- 278: 902c 2400 ldrh r12,\[r12]
+ 278: 902c 2400 ldrh r12,\[r12,\+0x0]
27c: 6fac fcff ldrh r59,\[r59,\+0x7ff]
280: 902c 6c80 ldrh r28,\[r28,\+0x400]
284: 6fac 6c7f ldrh r27,\[r27,\+0x3ff]
@@ -339,17 +339,17 @@ Disassembly of section .text:
2e8: 91cd 2080 ldr r12,\[r4],\+fp
000002ec \<ldrd16\>:
- 2ec: 904c 2400 ldr r12,\[r12]
+ 2ec: 904c 2400 ldr r12,\[r12,\+0x0]
2f0: 6fc4 ldr r3,\[r3,0x7]
2f2: 0244 ldr r0,\[r0,0x4]
2f4: 6dcc 2400 ldr fp,\[fp,\+0x3]
2f8: b4cc 2400 ldr sp,\[sp,\+0x1]
- 2fc: 144c 0400 ldr r0,\[sp]
+ 2fc: 144c 0400 ldr r0,\[sp,\+0x0]
300: 87cc 2000 ldr r12,\[r1,\+0x7]
304: 64cc 2000 ldr fp,\[r1,\+0x1]
00000308 \<ldrd\>:
- 308: 904c 2400 ldr r12,\[r12]
+ 308: 904c 2400 ldr r12,\[r12,\+0x0]
30c: 6fcc fcff ldr r59,\[r59,\+0x7ff]
310: 904c 6c80 ldr r28,\[r28,\+0x400]
314: 6fcc 6c7f ldr r27,\[r27,\+0x3ff]
@@ -393,7 +393,7 @@ Disassembly of section .text:
386: 41ed f080 ldrd r58,\[r32],\+fp
0000038a \<ldrdd16\>:
- 38a: 906c 2400 ldrd r12,\[r12]
+ 38a: 906c 2400 ldrd r12,\[r12,\+0x0]
38e: 8fe4 ldrd r4,\[r3,0x7]
390: 0264 ldrd r0,\[r0,0x4]
392: 0dec 4400 ldrd r16,\[fp,\+0x3]
@@ -403,7 +403,7 @@ Disassembly of section .text:
3a2: d0ec 2400 ldrd lr,\[r12,\+0x1]
000003a6 \<ldrdd\>:
- 3a6: 906c 2400 ldrd r12,\[r12]
+ 3a6: 906c 2400 ldrd r12,\[r12,\+0x0]
3aa: 4fec fcff ldrd r58,\[r59,\+0x7ff]
3ae: 906c 6c80 ldrd r28,\[r28,\+0x400]
3b2: 4fec 0c7f ldrd r2,\[r27,\+0x3ff]
diff --git a/gas/testsuite/gas/epiphany/regression.d b/gas/testsuite/gas/epiphany/regression.d
index c993f23..8cf80b8 100644
--- a/gas/testsuite/gas/epiphany/regression.d
+++ b/gas/testsuite/gas/epiphany/regression.d
@@ -77,7 +77,7 @@ Disassembly of section \.text:
0000006e \<NEXT\>:
6e: 8014 strb r4,\[r0\]
- 70: e00c e000 ldrb r63,\[r0\]
+ 70: e00c e000 ldrb r63,\[r0,\+0x0\]
74: fe3f fc0a sub r63,r63,r4
78: 0300 beq 7e \<STOREB\>
7a: 0023 mov r0,0x1
@@ -93,7 +93,7 @@ Disassembly of section \.text:
00000090 \<STORES\>:
90: 8034 strh r4,\[r0\]
- 92: e02c e000 ldrh r63,\[r0\]
+ 92: e02c e000 ldrh r63,\[r0,\+0x0\]
96: fe3f fc0a sub r63,r63,r4
9a: 0300 beq a0 \<STORES2\>
9c: 0023 mov r0,0x1
@@ -109,7 +109,7 @@ Disassembly of section \.text:
000000b2 \<STORE\>:
b2: 8054 str r4,\[r0\]
- b4: e04c e000 ldr r63,\[r0\]
+ b4: e04c e000 ldr r63,\[r0,\+0x0\]
b8: fe3f fc0a sub r63,r63,r4
bc: 0300 beq c2 \<STORE2\>
be: 0023 mov r0,0x1