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[binutils-gdb] Remove trailing spaces in opcodes
- From: H.J.Lu <hjl at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 12 Aug 2015 11:47:39 -0000
- Subject: [binutils-gdb] Remove trailing spaces in opcodes
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=43e65147c07b1400ae0dbb6694882eceb2363713
commit 43e65147c07b1400ae0dbb6694882eceb2363713
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Wed Aug 12 04:45:07 2015 -0700
Remove trailing spaces in opcodes
Diff:
---
opcodes/ChangeLog-2006 | 20 +-
opcodes/ChangeLog-2007 | 4 +-
opcodes/Makefile.am | 16 +-
opcodes/Makefile.in | 6 +-
opcodes/aarch64-gen.c | 2 +-
opcodes/alpha-opc.c | 2 +-
opcodes/arc-dis.c | 6 +-
opcodes/arc-dis.h | 8 +-
opcodes/arc-ext.h | 10 +-
opcodes/arm-dis.c | 114 +-
opcodes/avr-dis.c | 42 +-
opcodes/cgen-asm.c | 2 +-
opcodes/cgen-asm.in | 36 +-
opcodes/cgen-dis.c | 2 +-
opcodes/cgen-dis.in | 8 +-
opcodes/cgen-ibld.in | 4 +-
opcodes/cgen-opc.c | 6 +-
opcodes/cgen.sh | 2 +-
opcodes/configure.ac | 6 +-
opcodes/configure.com | 4 +-
opcodes/cr16-dis.c | 8 +-
opcodes/cris-dis.c | 2 +-
opcodes/crx-dis.c | 12 +-
opcodes/d10v-opc.c | 2 +-
opcodes/d30v-opc.c | 2 +-
opcodes/dis-buf.c | 2 +-
opcodes/dlx-dis.c | 2 +-
opcodes/epiphany-asm.c | 38 +-
opcodes/epiphany-desc.c | 186 +--
opcodes/epiphany-dis.c | 10 +-
opcodes/epiphany-ibld.c | 8 +-
opcodes/fr30-asm.c | 38 +-
opcodes/fr30-desc.c | 102 +-
opcodes/fr30-dis.c | 12 +-
opcodes/fr30-ibld.c | 8 +-
opcodes/frv-asm.c | 66 +-
opcodes/frv-desc.c | 182 +--
opcodes/frv-dis.c | 12 +-
opcodes/frv-ibld.c | 8 +-
opcodes/frv-opc.c | 10 +-
opcodes/h8300-dis.c | 32 +-
opcodes/i370-opc.c | 2 +-
opcodes/i386-opc.h | 2 +-
opcodes/i860-dis.c | 12 +-
opcodes/ia64-asmtab.c | 2778 ++++++++++++++++++++++-----------------------
opcodes/ia64-asmtab.h | 12 +-
opcodes/ia64-dis.c | 2 +-
opcodes/ia64-gen.c | 136 +--
opcodes/ia64-opc-m.c | 8 +-
opcodes/ip2k-asm.c | 58 +-
opcodes/ip2k-desc.c | 30 +-
opcodes/ip2k-dis.c | 10 +-
opcodes/ip2k-ibld.c | 8 +-
opcodes/ip2k-opc.c | 2 +-
opcodes/iq2000-asm.c | 48 +-
opcodes/iq2000-desc.c | 68 +-
opcodes/iq2000-dis.c | 10 +-
opcodes/iq2000-ibld.c | 8 +-
opcodes/lm32-asm.c | 38 +-
opcodes/lm32-desc.c | 40 +-
opcodes/lm32-dis.c | 10 +-
opcodes/lm32-ibld.c | 8 +-
opcodes/lm32-opc.h | 2 +-
opcodes/m10200-dis.c | 12 +-
opcodes/m10200-opc.c | 10 +-
opcodes/m10300-opc.c | 24 +-
opcodes/m32c-asm.c | 78 +-
opcodes/m32c-desc.c | 422 +++----
opcodes/m32c-dis.c | 14 +-
opcodes/m32c-ibld.c | 8 +-
opcodes/m32c-opc.c | 8 +-
opcodes/m32r-asm.c | 38 +-
opcodes/m32r-desc.c | 60 +-
opcodes/m32r-dis.c | 10 +-
opcodes/m32r-ibld.c | 8 +-
opcodes/m68hc11-dis.c | 4 +-
opcodes/m68hc11-opc.c | 2 +-
opcodes/m68k-dis.c | 6 +-
opcodes/m68k-opc.c | 18 +-
opcodes/m88k-dis.c | 14 +-
opcodes/makefile.vms | 4 +-
opcodes/mcore-opc.h | 4 +-
opcodes/mep-asm.c | 74 +-
opcodes/mep-desc.c | 298 ++---
opcodes/mep-dis.c | 50 +-
opcodes/mep-ibld.c | 8 +-
opcodes/mep-opc.h | 2 +-
opcodes/microblaze-dis.h | 4 +-
opcodes/microblaze-opc.h | 44 +-
opcodes/microblaze-opcm.h | 16 +-
opcodes/mips-dis.c | 6 +-
opcodes/mips-opc.c | 8 +-
opcodes/moxie-dis.c | 2 +-
opcodes/msp430-decode.c | 86 +-
opcodes/msp430-dis.c | 18 +-
opcodes/mt-asm.c | 56 +-
opcodes/mt-desc.c | 114 +-
opcodes/mt-dis.c | 10 +-
opcodes/mt-ibld.c | 8 +-
opcodes/mt-opc.c | 2 +-
opcodes/nios2-dis.c | 10 +-
opcodes/ns32k-dis.c | 6 +-
opcodes/opintl.h | 2 +-
opcodes/or1k-asm.c | 38 +-
opcodes/or1k-desc.c | 66 +-
opcodes/or1k-dis.c | 10 +-
opcodes/or1k-ibld.c | 8 +-
opcodes/ppc-dis.c | 2 +-
opcodes/ppc-opc.c | 120 +-
opcodes/rl78-decode.c | 752 ++++++------
opcodes/rl78-decode.opc | 18 +-
opcodes/rl78-dis.c | 4 +-
opcodes/rx-decode.c | 462 ++++----
opcodes/rx-decode.opc | 8 +-
opcodes/score-dis.c | 96 +-
opcodes/score-opc.h | 74 +-
opcodes/score7-dis.c | 70 +-
opcodes/sh-dis.c | 2 +-
opcodes/sh-opc.h | 12 +-
opcodes/sh64-opc.c | 2 +-
opcodes/sparc-dis.c | 2 +-
opcodes/spu-opc.c | 6 +-
opcodes/tic80-opc.c | 2 +-
opcodes/v850-opc.c | 8 +-
opcodes/vax-dis.c | 4 +-
opcodes/w65-opc.h | 2 +-
opcodes/xc16x-asm.c | 40 +-
opcodes/xc16x-desc.c | 134 +--
opcodes/xc16x-dis.c | 10 +-
opcodes/xc16x-ibld.c | 8 +-
opcodes/xc16x-opc.c | 2 +-
opcodes/xstormy16-asm.c | 52 +-
opcodes/xstormy16-desc.c | 82 +-
opcodes/xstormy16-dis.c | 10 +-
opcodes/xstormy16-ibld.c | 8 +-
opcodes/xtensa-dis.c | 4 +-
opcodes/z80-dis.c | 4 +-
137 files changed, 4012 insertions(+), 4012 deletions(-)
diff --git a/opcodes/ChangeLog-2006 b/opcodes/ChangeLog-2006
index f7c2a49..b65e86d 100644
--- a/opcodes/ChangeLog-2006
+++ b/opcodes/ChangeLog-2006
@@ -193,11 +193,11 @@
2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
- * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
+ * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
amdfam10 architecture.
(PREGRP37): NEW.
(print_insn): Disallow REP prefix for POPCNT.
-
+
2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
* sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
@@ -274,9 +274,9 @@
* i386-dis.c (MXC,EMC): Define.
(OP_MXC): New function to handle cvt* (convert instructions) between
%xmm and %mm register correctly.
- (OP_EMC): ditto.
- (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
- instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
+ (OP_EMC): ditto.
+ (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
+ instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
with EMC/MXC.
2006-07-29 Richard Sandiford <richard@codesourcery.com>
@@ -689,7 +689,7 @@
New cases '$' and '%' for read/write hyperprivileged register.
* sparc-opc.c (sparc_opcodes): Add new entries for UA2005
window handling and rdhpr/wrhpr instructions.
-
+
2006-02-24 DJ Delorie <dj@redhat.com>
* m32c-desc.c: Regenerate with linker relaxation attributes.
@@ -742,13 +742,13 @@
* xc16x-desc.h: New file
* xc16x-desc.c: New file
- * xc16x-opc.h: New file
+ * xc16x-opc.h: New file
* xc16x-opc.c: New file
* xc16x-ibld.c: New file
* xc16x-asm.c: New file
* xc16x-dis.c: New file
- * Makefile.am: Entries for xc16x
- * Makefile.in: Regenerate
+ * Makefile.am: Entries for xc16x
+ * Makefile.in: Regenerate
* cofigure.in: Add xc16x target information.
* configure: Regenerate.
* disassemble.c: Add xc16x target information.
@@ -783,7 +783,7 @@
* z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
ld_d_r, pref_xd_cb): Use signed char to hold data to be
- disassembled.
+ disassembled.
* z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
buffer overflows when disassembling instructions like
ld (ix+123),0x23
diff --git a/opcodes/ChangeLog-2007 b/opcodes/ChangeLog-2007
index d628f1c..5942489 100644
--- a/opcodes/ChangeLog-2007
+++ b/opcodes/ChangeLog-2007
@@ -1071,7 +1071,7 @@
* s390-mkopc.c (struct s390_cond_ext_format): New global struct.
(s390_cond_ext_format): New global variable.
(expandConditionalJump): New function.
- (main): Invoke expandConditionalJump for mnemonics containing '*'.
+ (main): Invoke expandConditionalJump for mnemonics containing '*'.
* s390-opc.txt: Replace mnemonics with conditional
mask extensions with instructions using the newly introduced '*' tag.
@@ -1096,7 +1096,7 @@
* ia64-gen.c: (main): Add missing newline to copyright message.
* ia64-ic.tbl (fp-non-arith): Add xmpy.
* ia64-asmtab.c: Regenerate.
-
+
2007-08-01 Michael Snyder <msnyder@access-company.com>
* i386-dis.c (print_insn): Guard against NULL.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 4adc6ff..6a4f6c1 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -6,12 +6,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
@@ -392,15 +392,15 @@ EPIPHANY_DEPS =
FR30_DEPS =
FRV_DEPS =
IP2K_DEPS =
-IQ2000_DEPS =
-LM32_DEPS =
+IQ2000_DEPS =
+LM32_DEPS =
M32C_DEPS =
M32R_DEPS =
MEP_DEPS =
MT_DEPS =
-OR1K_DEPS =
-XC16X_DEPS =
-XSTORMY16_DEPS =
+OR1K_DEPS =
+XC16X_DEPS =
+XSTORMY16_DEPS =
endif
run-cgen:
@@ -546,7 +546,7 @@ i386-gen.o: i386-gen.c i386-opc.h $(srcdir)/../include/opcode/i386.h \
config.h i386-opc.h sysdep.h
$(COMPILE_FOR_BUILD) -c $(srcdir)/i386-gen.c
-$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
+$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
@echo $@
$(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 0bc3e16..3517739 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -22,12 +22,12 @@
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
@@ -1416,7 +1416,7 @@ i386-gen.o: i386-gen.c i386-opc.h $(srcdir)/../include/opcode/i386.h \
config.h i386-opc.h sysdep.h
$(COMPILE_FOR_BUILD) -c $(srcdir)/i386-gen.c
-$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
+$(srcdir)/i386-tbl.h: $(srcdir)/i386-init.h
@echo $@
$(srcdir)/i386-init.h: @MAINT@ i386-gen$(EXEEXT_FOR_BUILD) i386-opc.tbl i386-reg.tbl
diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c
index 3815105..bc1e58a 100644
--- a/opcodes/aarch64-gen.c
+++ b/opcodes/aarch64-gen.c
@@ -209,7 +209,7 @@ static int max_num_opcodes_at_leaf_node = 0;
is decided to be undividable and OPCODE will be assigned to BITTREE->LIST.
The function recursively call itself until OPCODE is undividable.
-
+
N.B. the nature of this algrithm determines that given any value in the
32-bit space, the computed decision tree will always be able to find one or
more opcodes entries for it, regardless whether there is a valid instruction
diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c
index ed86238..c0b70f6 100644
--- a/opcodes/alpha-opc.c
+++ b/opcodes/alpha-opc.c
@@ -274,7 +274,7 @@ const struct alpha_operand alpha_operands[] =
/* The signed "23-bit" aligned displacement of Branch format insns. */
#define BDISP (MDISP + 1)
- { 21, 0, BFD_RELOC_23_PCREL_S2,
+ { 21, 0, BFD_RELOC_23_PCREL_S2,
AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
/* The 26-bit PALcode function */
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 92f69da..617511b 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -35,18 +35,18 @@
#define dbg (0)
#endif
-/* Classification of the opcodes for the decoder to print
+/* Classification of the opcodes for the decoder to print
the instructions. */
typedef enum
{
- CLASS_A4_ARITH,
+ CLASS_A4_ARITH,
CLASS_A4_OP3_GENERAL,
CLASS_A4_FLAG,
/* All branches other than JC. */
CLASS_A4_BRANCH,
CLASS_A4_JC ,
- /* All loads other than immediate
+ /* All loads other than immediate
indexed loads. */
CLASS_A4_LD0,
CLASS_A4_LD1,
diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h
index f90f8a5..dc73322 100644
--- a/opcodes/arc-dis.h
+++ b/opcodes/arc-dis.h
@@ -21,14 +21,14 @@
#ifndef ARCDIS_H
#define ARCDIS_H
-enum
+enum
{
BR_exec_when_no_jump,
BR_exec_always,
BR_exec_when_jump
};
-enum Flow
+enum Flow
{
noflow,
direct_jump,
@@ -41,7 +41,7 @@ enum Flow
enum { no_reg = 99 };
enum { allOperandsSize = 256 };
-struct arcDisState
+struct arcDisState
{
void *_this;
int instructionLen;
@@ -50,7 +50,7 @@ struct arcDisState
const char *(*auxRegName)(void*, int);
const char *(*condCodeName)(void*, int);
const char *(*instName)(void*, int, int, int*);
-
+
unsigned char* instruction;
unsigned index;
const char *comm[6]; /* instr name, cond, NOP, 3 operands */
diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h
index 07dabb3..8a7d7c4 100644
--- a/opcodes/arc-ext.h
+++ b/opcodes/arc-ext.h
@@ -30,20 +30,20 @@ enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)};
enum {NUM_EXT_CORE = 59-32+1};
enum {NUM_EXT_COND = 0x1f-0x10+1};
-struct ExtInstruction
+struct ExtInstruction
{
char flags;
char *name;
-};
+};
-struct ExtAuxRegister
+struct ExtAuxRegister
{
long address;
char *name;
- struct ExtAuxRegister *next;
+ struct ExtAuxRegister *next;
};
-struct arcExtMap
+struct arcExtMap
{
struct ExtAuxRegister *auxRegisters;
struct ExtInstruction *instructions[NUM_EXT_INST];
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ab9638b..46bda78 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -125,7 +125,7 @@ struct opcode16
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
-
+
%L print as an iWMMXt N/M width field.
%Z print the Immediate of a WSHUFH instruction.
%l like 'A' except use byte offsets for 'B' & 'H'
@@ -920,7 +920,7 @@ static const struct opcode32 coprocessor_opcodes[] =
%<bitfield>Sn print byte scaled width limited by n
%<bitfield>Tn print short scaled width limited by n
%<bitfield>Un print long scaled width limited by n
-
+
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order. */
@@ -1539,10 +1539,10 @@ static const struct opcode32 neon_opcodes[] =
%<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
%<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
%<bitfield>d print the bitfield in decimal
- %<bitfield>W print the bitfield plus one in decimal
+ %<bitfield>W print the bitfield plus one in decimal
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
-
+
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
@@ -3084,8 +3084,8 @@ arm_decode_bitfield (const char *ptr,
{
unsigned long value = 0;
int width = 0;
-
- do
+
+ do
{
int start, end;
int bits;
@@ -3310,7 +3310,7 @@ print_insn_coprocessor (bfd_vma pc,
func (stream, "\t; ");
/* For unaligned PCs, apply off-by-alignment
correction. */
- info->print_address_func (offset + pc
+ info->print_address_func (offset + pc
+ info->bytes_per_chunk * 2
- (pc & 3),
info);
@@ -3897,7 +3897,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
else
return FALSE;
}
-
+
for (insn = neon_opcodes; insn->assembler; insn++)
{
if ((given & insn->mask) == insn->value)
@@ -3928,7 +3928,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 'A':
{
- static const unsigned char enc[16] =
+ static const unsigned char enc[16] =
{
0x4, 0x14, /* st4 0,1 */
0x4, /* st1 2 */
@@ -3950,7 +3950,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
int n = enc[type] & 0xf;
int stride = (enc[type] >> 4) + 1;
int ix;
-
+
func (stream, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
@@ -3969,7 +3969,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, ", %s", arm_regnames[rm]);
}
break;
-
+
case 'B':
{
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
@@ -3985,7 +3985,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
if (length > 1 && size > 0)
stride = (idx_align & (1 << size)) ? 2 : 1;
-
+
switch (length)
{
case 1:
@@ -4002,19 +4002,19 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
}
}
break;
-
+
case 2:
if (size == 2 && (idx_align & 2) != 0)
return FALSE;
align = (idx_align & 1) ? 16 << size : 0;
break;
-
+
case 3:
if ((size == 2 && (idx_align & 3) != 0)
|| (idx_align & 1) != 0)
return FALSE;
break;
-
+
case 4:
if (size == 2)
{
@@ -4025,11 +4025,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
else
align = (idx_align & 1) ? 32 << size : 0;
break;
-
+
default:
abort ();
}
-
+
func (stream, "{");
for (i = 0; i < length; i++)
func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
@@ -4044,7 +4044,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, ", %s", arm_regnames[rm]);
}
break;
-
+
case 'C':
{
int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
@@ -4056,12 +4056,12 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
int n = type + 1;
int stride = ((given >> 5) & 0x1);
int ix;
-
+
if (stride && (n == 1))
n++;
else
stride++;
-
+
func (stream, "{");
if (stride > 1)
for (ix = 0; ix != n; ix++)
@@ -4088,18 +4088,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
func (stream, ", %s", arm_regnames[rm]);
}
break;
-
+
case 'D':
{
int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
int size = (given >> 20) & 3;
int reg = raw_reg & ((4 << size) - 1);
int ix = raw_reg >> size >> 2;
-
+
func (stream, "d%d[%d]", reg, ix);
}
break;
-
+
case 'E':
/* Neon encoded constant for mov, mvn, vorr, vbic. */
{
@@ -4110,11 +4110,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
unsigned shift;
int size = 0;
int isfloat = 0;
-
+
bits |= ((given >> 24) & 1) << 7;
bits |= ((given >> 16) & 7) << 4;
bits |= ((given >> 0) & 15) << 0;
-
+
if (cmode < 8)
{
shift = (cmode >> 1) & 3;
@@ -4141,7 +4141,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
/* Bit replication into bytes. */
int ix;
unsigned long mask;
-
+
value = 0;
hival = 0;
for (ix = 7; ix >= 0; ix--)
@@ -4165,7 +4165,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
{
/* Floating point encoding. */
int tmp;
-
+
value = (unsigned long) (bits & 0x7f) << 19;
value |= (unsigned long) (bits & 0x80) << 24;
tmp = bits & 0x40 ? 0x3c : 0x40;
@@ -4185,7 +4185,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 8:
func (stream, "#%ld\t; 0x%.2lx", value, value);
break;
-
+
case 16:
func (stream, "#%ld\t; 0x%.4lx", value, value);
break;
@@ -4195,24 +4195,24 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
{
unsigned char valbytes[4];
double fvalue;
-
+
/* Do this a byte at a time so we don't have to
worry about the host's endianness. */
valbytes[0] = value & 0xff;
valbytes[1] = (value >> 8) & 0xff;
valbytes[2] = (value >> 16) & 0xff;
valbytes[3] = (value >> 24) & 0xff;
-
- floatformat_to_double
+
+ floatformat_to_double
(& floatformat_ieee_single_little, valbytes,
& fvalue);
-
+
func (stream, "#%.7g\t; 0x%.8lx", fvalue,
value);
}
else
func (stream, "#%ld\t; 0x%.8lx",
- (long) (((value & 0x80000000L) != 0)
+ (long) (((value & 0x80000000L) != 0)
? value | ~0xffffffffL : value),
value);
break;
@@ -4220,18 +4220,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 64:
func (stream, "#0x%.8lx%.8lx", hival, value);
break;
-
+
default:
abort ();
}
}
break;
-
+
case 'F':
{
int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
int num = (given >> 8) & 0x3;
-
+
if (!num)
func (stream, "{d%d}", regno);
else if (num + regno >= 32)
@@ -4249,7 +4249,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
unsigned long value;
c = arm_decode_bitfield (c, given, &value, &width);
-
+
switch (*c)
{
case 'r':
@@ -4262,7 +4262,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
case 'e':
func (stream, "%ld", (1ul << width) - value);
break;
-
+
case 'S':
case 'T':
case 'U':
@@ -4302,7 +4302,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
else
func (stream, "q%ld", value >> 1);
break;
-
+
case '`':
c++;
if (value == 0)
@@ -4345,20 +4345,20 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
/* Return the name of a v7A special register. */
-static const char *
+static const char *
banked_regname (unsigned reg)
{
switch (reg)
{
case 15: return "CPSR";
- case 32: return "R8_usr";
+ case 32: return "R8_usr";
case 33: return "R9_usr";
case 34: return "R10_usr";
case 35: return "R11_usr";
case 36: return "R12_usr";
case 37: return "SP_usr";
case 38: return "LR_usr";
- case 40: return "R8_fiq";
+ case 40: return "R8_fiq";
case 41: return "R9_fiq";
case 42: return "R10_fiq";
case 43: return "R11_fiq";
@@ -4739,7 +4739,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
}
else
{
- func (stream, "%cPSR_",
+ func (stream, "%cPSR_",
(given & 0x00400000) ? 'S' : 'C');
if (given & 0x80000)
func (stream, "f");
@@ -4753,7 +4753,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'U':
- if ((given & 0xf0) == 0x60)
+ if ((given & 0xf0) == 0x60)
{
switch (given & 0xf)
{
@@ -4762,8 +4762,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
func (stream, "#%d", (int) given & 0xf);
break;
}
- }
- else
+ }
+ else
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
@@ -4780,7 +4780,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
unsigned long value;
c = arm_decode_bitfield (c, given, &value, &width);
-
+
switch (*c)
{
case 'R':
@@ -5317,7 +5317,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
value_in_comment = imm;
}
break;
-
+
case 'J':
{
unsigned int imm = 0;
@@ -5647,7 +5647,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'U':
- if ((given & 0xf0) == 0x60)
+ if ((given & 0xf0) == 0x60)
{
switch (given & 0xf)
{
@@ -5657,7 +5657,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
break;
}
}
- else
+ else
{
const char * opt = data_barrier_option (given & 0xf);
if (opt != NULL)
@@ -5688,7 +5688,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
sysm |= (given & 0x30);
sysm |= (given & 0x00100000) >> 14;
name = banked_regname (sysm);
-
+
if (name != NULL)
func (stream, "%s", name);
else
@@ -5727,7 +5727,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
unsigned long val;
c = arm_decode_bitfield (c, given, &val, &width);
-
+
switch (*c)
{
case 'd':
@@ -5766,7 +5766,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
if (val == ((1ul << width) - 1))
func (stream, "%c", *c);
break;
-
+
case '`':
c++;
if (val == 0)
@@ -5777,7 +5777,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
func (stream, "%c", c[(1 << width) - (int) val]);
c += 1 << width;
break;
-
+
case 'x':
func (stream, "0x%lx", val & 0xffffffffUL);
break;
@@ -5855,7 +5855,7 @@ arm_symbol_is_valid (asymbol * sym,
struct disassemble_info * info ATTRIBUTE_UNUSED)
{
const char * name;
-
+
if (sym == NULL)
return FALSE;
@@ -5918,7 +5918,7 @@ parse_disassembler_options (char *options)
++ options;
/* Skip forward past seperators. */
while (ISSPACE (*options) || (*options == ','))
- ++ options;
+ ++ options;
}
}
@@ -6151,7 +6151,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
/* If the user did not use the -m command line switch then default to
disassembling all types of ARM instruction.
-
+
The info->mach value has to be ignored as this will be based on
the default archictecture for the target and/or hints in the notes
section, but it will never be greater than the current largest arm
diff --git a/opcodes/avr-dis.c b/opcodes/avr-dis.c
index d2b26d1..0f97b2c 100644
--- a/opcodes/avr-dis.c
+++ b/opcodes/avr-dis.c
@@ -62,7 +62,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */
else
insn = (insn & 0x01f0) >> 4; /* Destination register. */
-
+
sprintf (buf, "r%d", insn);
break;
@@ -72,11 +72,11 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
else
sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4));
break;
-
+
case 'w':
sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3));
break;
-
+
case 'a':
if (regs)
sprintf (buf, "r%d", 16 + (insn & 7));
@@ -138,11 +138,11 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
case 'b':
{
unsigned int x;
-
+
x = (insn & 7);
x |= (insn >> 7) & (3 << 3);
x |= (insn >> 8) & (1 << 5);
-
+
if (insn & 0x8)
*buf++ = 'Y';
else
@@ -151,17 +151,17 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
sprintf (comment, "0x%02x", x);
}
break;
-
+
case 'h':
*sym = 1;
*sym_addr = ((((insn & 1) | ((insn & 0x1f0) >> 3)) << 16) | insn2) * 2;
/* See PR binutils/2454. Ideally we would like to display the hex
value of the address only once, but this would mean recoding
objdump_print_address() which would affect many targets. */
- sprintf (buf, "%#lx", (unsigned long) *sym_addr);
+ sprintf (buf, "%#lx", (unsigned long) *sym_addr);
strcpy (comment, comment_start);
break;
-
+
case 'L':
{
int rel_addr = (((insn & 0xfff) ^ 0x800) - 0x800) * 2;
@@ -197,7 +197,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
sprintf (buf, "%d", val);
}
break;
-
+
case 'M':
sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
@@ -208,7 +208,7 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
fprintf (stderr, _("Internal disassembler error"));
ok = 0;
break;
-
+
case 'K':
{
unsigned int x;
@@ -218,15 +218,15 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
sprintf (comment, "%d", x);
}
break;
-
+
case 's':
sprintf (buf, "%d", insn & 7);
break;
-
+
case 'S':
sprintf (buf, "%d", (insn >> 4) & 7);
break;
-
+
case 'P':
{
unsigned int x;
@@ -241,21 +241,21 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
case 'p':
{
unsigned int x;
-
+
x = (insn >> 3) & 0x1f;
sprintf (buf, "0x%02x", x);
sprintf (comment, "%d", x);
}
break;
-
+
case 'E':
sprintf (buf, "%d", (insn >> 4) & 15);
break;
-
+
case '?':
*buf = '\0';
break;
-
+
default:
sprintf (buf, "??");
fprintf (stderr, _("unknown constraint `%c'"), constraint);
@@ -309,7 +309,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
comment_start = " ";
nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
-
+
avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));
for (opcode = avr_opcodes, maskptr = avr_bin_masks;
@@ -319,7 +319,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
char * s;
unsigned int bin = 0;
unsigned int mask = 0;
-
+
for (s = opcode->opcode; *s; ++s)
{
bin <<= 1;
@@ -336,7 +336,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
}
insn = avrdis_opcode (addr, info);
-
+
for (opcode = avr_opcodes, maskptr = avr_bin_masks;
opcode->name;
opcode++, maskptr++)
@@ -346,7 +346,7 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
if ((insn & *maskptr) == opcode->bin_opcode)
break;
}
-
+
/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
`std b+0,r' as `st b,r' (next entry in the table). */
diff --git a/opcodes/cgen-asm.c b/opcodes/cgen-asm.c
index 6c4f66d..f4f81d7 100644
--- a/opcodes/cgen-asm.c
+++ b/opcodes/cgen-asm.c
@@ -212,7 +212,7 @@ cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
character of the suffix ('.') is special. */
if (*p)
++p;
-
+
/* Allow letters, digits, and any special characters. */
while (((p - start) < (int) sizeof (buf))
&& *p
diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in
index 6faa34b..9b7c63e 100644
--- a/opcodes/cgen-asm.in
+++ b/opcodes/cgen-asm.in
@@ -60,9 +60,9 @@ static const char * parse_insn_normal
Returns NULL for success, an error message for failure. */
-char *
+char *
@arch@_cgen_build_insn_regex (CGEN_INSN *insn)
-{
+{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@@ -101,18 +101,18 @@ char *
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
- if (CGEN_SYNTAX_CHAR_P (* syn))
+ if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
- switch (c)
+ switch (c)
{
/* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
+ case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@@ -142,20 +142,20 @@ char *
}
/* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
/* But anchor it after that. */
- * rx++ = '$';
+ * rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
- if (reg_err == 0)
+ if (reg_err == 0)
return NULL;
else
{
@@ -354,7 +354,7 @@ const CGEN_INSN *
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@@ -414,7 +414,7 @@ const CGEN_INSN *
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@@ -423,11 +423,11 @@ const CGEN_INSN *
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
-
+
*errmsg = errbuf;
return NULL;
}
diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c
index 1eee434..7357b53 100644
--- a/opcodes/cgen-dis.c
+++ b/opcodes/cgen-dis.c
@@ -49,7 +49,7 @@ count_decodable_bits (const CGEN_INSN *insn)
return bits;
}
-/* Add an instruction to the hash chain. */
+/* Add an instruction to the hash chain. */
static void
add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf,
const CGEN_INSN *insn,
diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in
index 49b9768..c2953d4 100644
--- a/opcodes/cgen-dis.in
+++ b/opcodes/cgen-dis.in
@@ -231,7 +231,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! @arch@_cgen_insn_supported (cd, insn))
@@ -249,7 +249,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@@ -368,7 +368,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
-
+
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@@ -409,7 +409,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in
index 73e8a3e..af2e02c 100644
--- a/opcodes/cgen-ibld.in
+++ b/opcodes/cgen-ibld.in
@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
-
+
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
-
+
if (value < minval || value > maxval)
{
sprintf
diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c
index 115e1bf..caea033 100644
--- a/opcodes/cgen-opc.c
+++ b/opcodes/cgen-opc.c
@@ -127,7 +127,7 @@ cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke)
&& ! strchr (kt->nonalpha_chars, ke->name[i]))
{
size_t idx = strlen (kt->nonalpha_chars);
-
+
/* If you hit this limit, please don't just
increase the size of the field, instead
look for a better algorithm. */
@@ -369,7 +369,7 @@ cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length)
segments, and endian-convert them, one at a time. */
int i;
- /* Enforce divisibility. */
+ /* Enforce divisibility. */
if ((length % insn_chunk_bitsize) != 0)
abort ();
@@ -408,7 +408,7 @@ cgen_put_insn_value (CGEN_CPU_DESC cd,
segments, and endian-convert them, one at a time. */
int i;
- /* Enforce divisibility. */
+ /* Enforce divisibility. */
if ((length % insn_chunk_bitsize) != 0)
abort ();
diff --git a/opcodes/cgen.sh b/opcodes/cgen.sh
index 6865601..283649f 100644
--- a/opcodes/cgen.sh
+++ b/opcodes/cgen.sh
@@ -26,7 +26,7 @@
# cgen.sh action srcdir cgen cgendir cgenflags arch prefix \
# arch-file opc-file options [extrafiles]
#
-# ACTION is currently always "opcodes". It exists to be consistent with the
+# ACTION is currently always "opcodes". It exists to be consistent with the
# simulator.
# ARCH is the name of the architecture.
# It is substituted into @arch@ and @ARCH@ in the generated files.
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index 4cdca85..07e3162 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -6,12 +6,12 @@ dnl This file is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU General Public License as published by
dnl the Free Software Foundation; either version 3 of the License, or
dnl (at your option) any later version.
-dnl
+dnl
dnl This program is distributed in the hope that it will be useful,
dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
dnl GNU General Public License for more details.
-dnl
+dnl
dnl You should have received a copy of the GNU General Public License
dnl along with this program; see the file COPYING3. If not see
dnl <http://www.gnu.org/licenses/>.
@@ -234,7 +234,7 @@ do
. $srcdir/../bfd/config.bfd
selarchs="$selarchs $targ_archs"
fi
-done
+done
# Utility var, documents generic cgen support files.
diff --git a/opcodes/configure.com b/opcodes/configure.com
index b2eb160..13705a0 100644
--- a/opcodes/configure.com
+++ b/opcodes/configure.com
@@ -12,12 +12,12 @@ $! This file is free software; you can redistribute it and/or modify
$! it under the terms of the GNU General Public License as published by
$! the Free Software Foundation; either version 3 of the License, or
$! (at your option) any later version.
-$!
+$!
$! This program is distributed in the hope that it will be useful,
$! but WITHOUT ANY WARRANTY; without even the implied warranty of
$! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
$! GNU General Public License for more details.
-$!
+$!
$! You should have received a copy of the GNU General Public License
$! along with this program; see the file COPYING3. If not see
$! <http://www.gnu.org/licenses/>.
diff --git a/opcodes/cr16-dis.c b/opcodes/cr16-dis.c
index 749f80e..00c672e 100644
--- a/opcodes/cr16-dis.c
+++ b/opcodes/cr16-dis.c
@@ -358,7 +358,7 @@ make_argument (argument * a, int start_bits)
switch (a->type)
{
case arg_r:
- p = makelongparameter (cr16_allWords,
+ p = makelongparameter (cr16_allWords,
inst_bit_size - (start_bits + a->size),
inst_bit_size - start_bits);
a->r = p.val;
@@ -386,7 +386,7 @@ make_argument (argument * a, int start_bits)
break;
case arg_ic:
- p = makelongparameter (cr16_allWords,
+ p = makelongparameter (cr16_allWords,
inst_bit_size - (start_bits + a->size),
inst_bit_size - start_bits);
a->constant = p.val;
@@ -466,7 +466,7 @@ make_argument (argument * a, int start_bits)
}
else if (instruction->size == 2)
{
- p = makelongparameter (cr16_allWords, inst_bit_size - 16,
+ p = makelongparameter (cr16_allWords, inst_bit_size - 16,
inst_bit_size);
a->constant = p.val;
}
@@ -795,7 +795,7 @@ get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info)
for (i = 0, mem = memaddr; i < 3; i++, mem += 2)
cr16_words[i] = get_word_at_PC (mem, info);
- cr16_allWords = ((ULONGLONG) cr16_words[0] << 32)
+ cr16_allWords = ((ULONGLONG) cr16_words[0] << 32)
+ ((unsigned long) cr16_words[1] << 16) + cr16_words[2];
}
diff --git a/opcodes/cris-dis.c b/opcodes/cris-dis.c
index 1a68136..0d440dd 100644
--- a/opcodes/cris-dis.c
+++ b/opcodes/cris-dis.c
@@ -813,7 +813,7 @@ print_with_operands (const struct cris_opcode *opcodep,
*tp++ = 'c';
*tp++ = 'r';
break;
-
+
case '[':
case ']':
case ',':
diff --git a/opcodes/crx-dis.c b/opcodes/crx-dis.c
index 75bcfb0..893dcc5 100644
--- a/opcodes/crx-dis.c
+++ b/opcodes/crx-dis.c
@@ -60,9 +60,9 @@ cinv_entry;
/* CRX 'cinv' options. */
const cinv_entry crx_cinvs[] =
{
- {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
- {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
- {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
+ {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
+ {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
+ {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
{"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
};
@@ -76,7 +76,7 @@ typedef enum REG_ARG_TYPE
/* CO-Processor register (c<N>). */
COP_ARG,
/* CO-Processor special register (cs<N>). */
- COPS_ARG
+ COPS_ARG
}
REG_ARG_TYPE;
@@ -534,8 +534,8 @@ print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info)
else if (INST_HAS_REG_LIST)
{
- REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
- COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
+ REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ?
+ COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
COPS_ARG : (instruction->flags & USER_REG) ?
USER_REG_ARG : REG_ARG;
diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c
index 0f2b280..0032d9a 100644
--- a/opcodes/d10v-opc.c
+++ b/opcodes/d10v-opc.c
@@ -89,7 +89,7 @@ const struct pd_reg d10v_predefined_registers[] =
{ "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
};
-int
+int
d10v_reg_name_cnt (void)
{
return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg));
diff --git a/opcodes/d30v-opc.c b/opcodes/d30v-opc.c
index 0e366f3..24f77d9 100644
--- a/opcodes/d30v-opc.c
+++ b/opcodes/d30v-opc.c
@@ -194,7 +194,7 @@ const struct pd_reg pre_defined_registers[] =
{ "va", NULL, OPERAND_FLAG + 6 },
};
-int
+int
reg_name_cnt (void)
{
return sizeof (pre_defined_registers) / sizeof (struct pd_reg);
diff --git a/opcodes/dis-buf.c b/opcodes/dis-buf.c
index 7c5d9ad..eb03e62 100644
--- a/opcodes/dis-buf.c
+++ b/opcodes/dis-buf.c
@@ -33,7 +33,7 @@ buffer_read_memory (bfd_vma memaddr,
{
unsigned int opb = info->octets_per_byte;
unsigned int end_addr_offset = length / opb;
- unsigned int max_addr_offset = info->buffer_length / opb;
+ unsigned int max_addr_offset = info->buffer_length / opb;
unsigned int octets = (memaddr - info->buffer_vma) * opb;
if (memaddr < info->buffer_vma
diff --git a/opcodes/dlx-dis.c b/opcodes/dlx-dis.c
index 7e6853c..459ff63 100644
--- a/opcodes/dlx-dis.c
+++ b/opcodes/dlx-dis.c
@@ -295,7 +295,7 @@ dlx_aluI_type (struct disassemble_info* info)
{ OPC(SGTUIOP), "sgtui" }, /* Store word. */
{ OPC(SLEUIOP), "sleui" }, /* Store word. */
{ OPC(SGEUIOP), "sgeui" }, /* Store word. */
-#if 0
+#if 0
{ OPC(MVTSOP), "mvts" }, /* Store word. */
{ OPC(MVFSOP), "mvfs" }, /* Store word. */
#endif
diff --git a/opcodes/epiphany-asm.c b/opcodes/epiphany-asm.c
index 1837f13..df347bd 100644
--- a/opcodes/epiphany-asm.c
+++ b/opcodes/epiphany-asm.c
@@ -458,7 +458,7 @@ epiphany_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
-cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
+cgen_parse_fn * const epiphany_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@@ -488,9 +488,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
-char *
+char *
epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
-{
+{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@@ -529,18 +529,18 @@ epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
- if (CGEN_SYNTAX_CHAR_P (* syn))
+ if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
- switch (c)
+ switch (c)
{
/* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
+ case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@@ -570,20 +570,20 @@ epiphany_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
/* But anchor it after that. */
- * rx++ = '$';
+ * rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
- if (reg_err == 0)
+ if (reg_err == 0)
return NULL;
else
{
@@ -782,7 +782,7 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@@ -842,7 +842,7 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@@ -851,11 +851,11 @@ epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
-
+
*errmsg = errbuf;
return NULL;
}
diff --git a/opcodes/epiphany-desc.c b/opcodes/epiphany-desc.c
index b488415..834dc7f 100644
--- a/opcodes/epiphany-desc.c
+++ b/opcodes/epiphany-desc.c
@@ -534,367 +534,367 @@ const CGEN_OPERAND epiphany_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: integer zero bit */
{ "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: integer neg bit */
{ "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: integer carry bit */
{ "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: integer overflow bit */
{ "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bzbit: floating point zero bit */
{ "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bnbit: floating point neg bit */
{ "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bvbit: floating point ovfl bit */
{ "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bcbit: floating point carry bit */
{ "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bubit: floating point underfl bit */
{ "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bibit: floating point invalid bit */
{ "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vsbit: integer overflow sticky */
{ "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bvsbit: floating point overflow sticky */
{ "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bisbit: floating point invalid sticky */
{ "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* busbit: floating point underflow sticky */
{ "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause0bit: exceprion cause bit0 */
{ "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause1bit: exceprion cause bit1 */
{ "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* expcause2bit: external load stalled bit */
{ "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* extFstallbit: external fetch stalled bit */
{ "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* trmbit: 0=round to nearest, 1=trunacte selct bit */
{ "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* invExcEnbit: invalid exception enable bit */
{ "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ovfExcEnbit: overflow exception enable bit */
{ "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* unExcEnbit: underflow exception enable bit */
{ "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit0: timer 0 mode selection 0 */
{ "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit1: timer 0 mode selection 1 */
{ "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit2: timer 0 mode selection 2 */
{ "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer0bit3: timer 0 mode selection 3 */
{ "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit0: timer 1 mode selection 0 */
{ "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit1: timer 1 mode selection 1 */
{ "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit2: timer 1 mode selection 2 */
{ "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* timer1bit3: timer 1 mode selection 3 */
{ "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* mbkptEnbit: multicore bkpt enable */
{ "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* clockGateEnbit: clock gate enable enable */
{ "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit0: arithmetic mode bit0 */
{ "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit1: arithmetic mode bit1 */
{ "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* arithmetic-modebit2: arithmetic mode bit2 */
{ "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit12: core config bit 12 */
{ "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit13: core config bit 13 */
{ "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit14: core config bit 14 */
{ "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit15: core config bit 15 */
{ "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit16: core config bit 16 */
{ "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit20: core config bit 20 */
{ "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit21: core config bit 21 */
{ "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit24: core config bit 24 */
{ "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit25: core config bit 25 */
{ "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit26: core config bit 26 */
{ "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit27: core config bit 27 */
{ "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit28: core config bit 28 */
{ "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit29: core config bit 29 */
{ "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit30: core config bit 30 */
{ "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* coreCfgResBit31: core config bit 31 */
{ "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* gidisablebit: global interrupt disable bit */
{ "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* kmbit: kernel mode bit */
{ "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* caibit: core actibe indicator bit */
{ "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sflagbit: sflag bit */
{ "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* memaddr: memory effective address */
{ "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* simm24: branch address pc-relative */
{ "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* simm8: branch address pc-relative */
{ "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* rd: destination register */
{ "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rn: source register */
{ "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rm: source register */
{ "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frd: fp destination register */
{ "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frn: fp source register */
{ "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* frm: fp source register */
{ "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* rd6: destination register */
{ "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
- { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rn6: source register */
{ "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
- { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* rm6: source register */
{ "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
- { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frd6: fp destination register */
{ "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
- { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frn6: fp source register */
{ "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
- { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* frm6: fp source register */
{ "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
- { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sd: special destination */
{ "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sn: special source */
{ "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sd6: special destination register */
{ "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sn6: special source register */
{ "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sddma: dma register */
{ "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sndma: dma register */
{ "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sdmem: mem register */
{ "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* snmem: mem register */
{ "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sdmesh: mesh register */
{ "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
- { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* snmesh: mesh register */
{ "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
- { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* simm3: signed 3-bit literal */
{ "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
{ 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
/* simm11: signed 11-bit literal */
{ "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
- { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
{ 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* disp3: short data displacement */
{ "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* trapnum6: parameter for swi or trap */
{ "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* swi_num: unsigned 6-bit swi# */
{ "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* disp11: sign-magnitude data displacement */
{ "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
- { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* shift: immediate shift amount */
{ "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm16: 16-bit unsigned literal */
{ "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
- { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
{ 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* imm8: 8-bit unsigned literal */
{ "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
{ 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
/* direction: +/- indexing */
{ "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dpmi: +/- magnitude immediate displacement */
{ "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
- { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
+ { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@@ -2212,7 +2212,7 @@ epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
-
+
return (CGEN_CPU_DESC) cd;
}
@@ -2252,7 +2252,7 @@ epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
- }
+ }
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c
index 338ebde..a20ab7a 100644
--- a/opcodes/epiphany-dis.c
+++ b/opcodes/epiphany-dis.c
@@ -279,7 +279,7 @@ epiphany_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
-cgen_print_fn * const epiphany_cgen_print_handlers[] =
+cgen_print_fn * const epiphany_cgen_print_handlers[] =
{
print_insn_normal,
};
@@ -469,7 +469,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! epiphany_cgen_insn_supported (cd, insn))
@@ -487,7 +487,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@@ -606,7 +606,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
-
+
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@@ -647,7 +647,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
diff --git a/opcodes/epiphany-ibld.c b/opcodes/epiphany-ibld.c
index b862216..7315273 100644
--- a/opcodes/epiphany-ibld.c
+++ b/opcodes/epiphany-ibld.c
@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
-
+
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
-
+
if (value < minval || value > maxval)
{
sprintf
@@ -1170,12 +1170,12 @@ epiphany_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
-cgen_insert_fn * const epiphany_cgen_insert_handlers[] =
+cgen_insert_fn * const epiphany_cgen_insert_handlers[] =
{
insert_insn_normal,
};
-cgen_extract_fn * const epiphany_cgen_extract_handlers[] =
+cgen_extract_fn * const epiphany_cgen_extract_handlers[] =
{
extract_insn_normal,
};
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index cca20d4..79465a0 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -313,7 +313,7 @@ fr30_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
-cgen_parse_fn * const fr30_cgen_parse_handlers[] =
+cgen_parse_fn * const fr30_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@@ -343,9 +343,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
-char *
+char *
fr30_cgen_build_insn_regex (CGEN_INSN *insn)
-{
+{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@@ -384,18 +384,18 @@ fr30_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
- if (CGEN_SYNTAX_CHAR_P (* syn))
+ if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
- switch (c)
+ switch (c)
{
/* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
+ case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@@ -425,20 +425,20 @@ fr30_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
/* But anchor it after that. */
- * rx++ = '$';
+ * rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
- if (reg_err == 0)
+ if (reg_err == 0)
return NULL;
else
{
@@ -637,7 +637,7 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@@ -697,7 +697,7 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@@ -706,11 +706,11 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
-
+
*errmsg = errbuf;
return NULL;
}
diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c
index b6db90c..0788bc2 100644
--- a/opcodes/fr30-desc.c
+++ b/opcodes/fr30-desc.c
@@ -364,199 +364,199 @@ const CGEN_OPERAND fr30_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R14: General Register 14 */
{ "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* R15: General Register 15 */
{ "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ps: Program Status register */
{ "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
- { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
- { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
+ { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: overflow bit */
{ "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: zero bit */
{ "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: carry bit */
{ "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ibit: interrupt bit */
{ "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sbit: stack bit */
{ "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbit: trace trap bit */
{ "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d0bit: division 0 bit */
{ "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* d1bit: division 1 bit */
{ "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ccr: condition code bits */
{ "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* scr: system condition bits */
{ "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ilm: interrupt level mask */
{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@@ -1689,7 +1689,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
-
+
return (CGEN_CPU_DESC) cd;
}
@@ -1729,7 +1729,7 @@ fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
- }
+ }
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index b91d994..b5db9b5 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -79,7 +79,7 @@ print_register_list (void * dis_info,
(*info->fprintf_func) (info->stream, "r%li", reg_index + offset);
comma = ",";
}
-
+
for (reg_index = 1; reg_index <= 7; ++reg_index)
{
if (load_store)
@@ -301,7 +301,7 @@ fr30_cgen_print_operand (CGEN_CPU_DESC cd,
}
}
-cgen_print_fn * const fr30_cgen_print_handlers[] =
+cgen_print_fn * const fr30_cgen_print_handlers[] =
{
print_insn_normal,
};
@@ -491,7 +491,7 @@ print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! fr30_cgen_insn_supported (cd, insn))
@@ -509,7 +509,7 @@ print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@@ -628,7 +628,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
-
+
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@@ -669,7 +669,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c
index 78d2bc7..177a12b 100644
--- a/opcodes/fr30-ibld.c
+++ b/opcodes/fr30-ibld.c
@@ -154,7 +154,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
-
+
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@@ -192,7 +192,7 @@ insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
-
+
if (value < minval || value > maxval)
{
sprintf
@@ -936,12 +936,12 @@ fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
-cgen_insert_fn * const fr30_cgen_insert_handlers[] =
+cgen_insert_fn * const fr30_cgen_insert_handlers[] =
{
insert_insn_normal,
};
-cgen_extract_fn * const fr30_cgen_extract_handlers[] =
+cgen_extract_fn * const fr30_cgen_extract_handlers[] =
{
extract_insn_normal,
};
diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c
index a9e8e68..c64cb86 100644
--- a/opcodes/frv-asm.c
+++ b/opcodes/frv-asm.c
@@ -99,10 +99,10 @@ parse_ldd_annotation (CGEN_CPU_DESC cd,
return errmsg;
}
}
-
+
while (**strp == ' ' || **strp == '\t')
++*strp;
-
+
if (**strp != '@')
return "missing `@'";
@@ -138,10 +138,10 @@ parse_call_annotation (CGEN_CPU_DESC cd,
return errmsg;
}
}
-
+
while (**strp == ' ' || **strp == '\t')
++*strp;
-
+
if (**strp != '@')
return "missing `@'";
@@ -177,10 +177,10 @@ parse_ld_annotation (CGEN_CPU_DESC cd,
return errmsg;
}
}
-
+
while (**strp == ' ' || **strp == '\t')
++*strp;
-
+
if (**strp != '@')
return "missing `@'";
@@ -198,7 +198,7 @@ parse_ulo16 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
-
+
if (**strp == '#' || **strp == '%')
{
if (strncasecmp (*strp + 1, "lo(", 3) == 0)
@@ -324,7 +324,7 @@ parse_uslo16 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
-
+
if (**strp == '#' || **strp == '%')
{
if (strncasecmp (*strp + 1, "lo(", 3) == 0)
@@ -450,7 +450,7 @@ parse_uhi16 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
-
+
if (**strp == '#' || **strp == '%')
{
if (strncasecmp (*strp + 1, "hi(", 3) == 0)
@@ -635,7 +635,7 @@ parse_d12 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
-
+
/* Check for small data reference. */
if (**strp == '#' || **strp == '%')
{
@@ -748,7 +748,7 @@ parse_s12 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
-
+
/* Check for small data reference. */
if (**strp == '#' || **strp == '%')
{
@@ -864,7 +864,7 @@ parse_u12 (CGEN_CPU_DESC cd,
const char *errmsg;
enum cgen_parse_operand_result result_type;
bfd_vma value;
-
+
/* Check for small data reference. */
if ((**strp == '#' || **strp == '%')
&& strncasecmp (*strp + 1, "gprel12(", 8) == 0)
@@ -895,7 +895,7 @@ parse_A (CGEN_CPU_DESC cd,
unsigned long A)
{
const char *errmsg;
-
+
if (**strp == '#')
++*strp;
@@ -957,7 +957,7 @@ parse_call_label (CGEN_CPU_DESC cd,
{
const char *errmsg;
bfd_vma value;
-
+
/* Check for small data reference. */
if (opinfo == 0 && (**strp == '#' || **strp == '%'))
{
@@ -1266,7 +1266,7 @@ frv_cgen_parse_operand (CGEN_CPU_DESC cd,
return errmsg;
}
-cgen_parse_fn * const frv_cgen_parse_handlers[] =
+cgen_parse_fn * const frv_cgen_parse_handlers[] =
{
parse_insn_normal,
};
@@ -1296,9 +1296,9 @@ CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
-char *
+char *
frv_cgen_build_insn_regex (CGEN_INSN *insn)
-{
+{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@@ -1337,18 +1337,18 @@ frv_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
- if (CGEN_SYNTAX_CHAR_P (* syn))
+ if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
- switch (c)
+ switch (c)
{
/* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
+ case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@@ -1378,20 +1378,20 @@ frv_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
/* But anchor it after that. */
- * rx++ = '$';
+ * rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
- if (reg_err == 0)
+ if (reg_err == 0)
return NULL;
else
{
@@ -1590,7 +1590,7 @@ frv_cgen_assemble_insn (CGEN_CP[...]
[diff truncated at 100000 bytes]