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[binutils-gdb/binutils-2_25-branch] [AArch64] Backport support id_mmfr4 system register

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=1f036f00dfb63a855e8b4fdfdac9ce594f0f69fd

commit 1f036f00dfb63a855e8b4fdfdac9ce594f0f69fd
Author: Jiong Wang <jiong.wang@arm.com>
Date:   Tue Jun 16 16:48:13 2015 +0100

    [AArch64] Backport support id_mmfr4 system register
    
    2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
    
    	Applied from master
    	2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
    
    	opcode/
    	  * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
    
    	gas/testsuite/
    	  * sysreg.d: Add id_mmfr4_el1, update expected output.
    	  * sysreg.s: Add id_mmfr4_el1.

Diff:
---
 gas/testsuite/ChangeLog            |  8 ++++++++
 gas/testsuite/gas/aarch64/sysreg.d | 23 ++++++++++++-----------
 gas/testsuite/gas/aarch64/sysreg.s |  1 +
 opcodes/ChangeLog                  |  7 +++++++
 opcodes/aarch64-opc.c              |  1 +
 5 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6477054..bc581b9 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+	Applied from master.
+	2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+	* sysreg.d: Add id_mmfr4_el1, update expected output.
+	* sysreg.s: Add id_mmfr4_el1.
+
 2015-06-04  Matthew Wahab  <matthew.wahab@arm.com>
 
 	* gas/aarch64/codealign.d: Add test for code section alignment.
diff --git a/gas/testsuite/gas/aarch64/sysreg.d b/gas/testsuite/gas/aarch64/sysreg.d
index 7795b4d..157340c 100644
--- a/gas/testsuite/gas/aarch64/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg.d
@@ -17,14 +17,15 @@ Disassembly of section \.text:
   24:	d53801a0 	mrs	x0, id_mmfr1_el1
   28:	d53801c0 	mrs	x0, id_mmfr2_el1
   2c:	d53801e0 	mrs	x0, id_mmfr3_el1
-  30:	d5380200 	mrs	x0, id_isar0_el1
-  34:	d5380220 	mrs	x0, id_isar1_el1
-  38:	d5380240 	mrs	x0, id_isar2_el1
-  3c:	d5380260 	mrs	x0, id_isar3_el1
-  40:	d5380280 	mrs	x0, id_isar4_el1
-  44:	d53802a0 	mrs	x0, id_isar5_el1
-  48:	d538cc00 	mrs	x0, s3_0_c12_c12_0
-  4c:	d5384600 	mrs	x0, s3_0_c4_c6_0
-  50:	d5184600 	msr	s3_0_c4_c6_0, x0
-  54:	d5310300 	mrs	x0, s2_1_c0_c3_0
-  58:	d5110300 	msr	s2_1_c0_c3_0, x0
+  30:	d53802c0 	mrs	x0, id_mmfr4_el1
+  34:	d5380200 	mrs	x0, id_isar0_el1
+  38:	d5380220 	mrs	x0, id_isar1_el1
+  3c:	d5380240 	mrs	x0, id_isar2_el1
+  40:	d5380260 	mrs	x0, id_isar3_el1
+  44:	d5380280 	mrs	x0, id_isar4_el1
+  48:	d53802a0 	mrs	x0, id_isar5_el1
+  4c:	d538cc00 	mrs	x0, s3_0_c12_c12_0
+  50:	d5384600 	mrs	x0, s3_0_c4_c6_0
+  54:	d5184600 	msr	s3_0_c4_c6_0, x0
+  58:	d5310300 	mrs	x0, s2_1_c0_c3_0
+  5c:	d5110300 	msr	s2_1_c0_c3_0, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg.s b/gas/testsuite/gas/aarch64/sysreg.s
index b7e5ff6..8974674 100644
--- a/gas/testsuite/gas/aarch64/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg.s
@@ -16,6 +16,7 @@
 	mrs x0, id_mmfr1_el1
 	mrs x0, id_mmfr2_el1
 	mrs x0, id_mmfr3_el1
+	mrs x0, id_mmfr4_el1
 	mrs x0, id_isar0_el1
 	mrs x0, id_isar1_el1
 	mrs x0, id_isar2_el1
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2d01f5a..53afdd2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+	Applied from master
+	2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
+
+	* aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
+
 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 
 	Applied from master.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 430cf5b..e168b9d 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2765,6 +2765,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "id_mmfr1_el1",     CPENC(3,0,C0,C1,5),	0 }, /* RO */
   { "id_mmfr2_el1",     CPENC(3,0,C0,C1,6),	0 }, /* RO */
   { "id_mmfr3_el1",     CPENC(3,0,C0,C1,7),	0 }, /* RO */
+  { "id_mmfr4_el1",     CPENC(3,0,C0,C2,6),	0 }, /* RO */
   { "id_isar0_el1",     CPENC(3,0,C0,C2,0),	0 }, /* RO */
   { "id_isar1_el1",     CPENC(3,0,C0,C2,1),	0 }, /* RO */
   { "id_isar2_el1",     CPENC(3,0,C0,C2,2),	0 }, /* RO */
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