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[binutils-gdb] [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
- From: Jiong Wang <jiwang at sourceware dot org>
- To: bfd-cvs at sourceware dot org
- Date: 15 Apr 2015 16:45:09 -0000
- Subject: [binutils-gdb] [ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f0fba320ab5effaff5255b5526a37f0987637e3e
commit f0fba320ab5effaff5255b5526a37f0987637e3e
Author: Renlin Li <renlin.li@arm.com>
Date: Wed Apr 15 17:44:03 2015 +0100
[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
2015-04-15 Renlin Li <renlin.li@arm.com>
opcodes/:
* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
use it for ssat and ssat16.
(print_insn_thumb32): Add handle case for 'D' control code.
gas/testsuite/:
* gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
* gas/arm/thumb32.d: Likewise.
Diff:
---
gas/testsuite/ChangeLog | 5 +++++
gas/testsuite/gas/arm/arch7em.d | 8 ++++----
gas/testsuite/gas/arm/thumb32.d | 24 ++++++++++++------------
opcodes/ChangeLog | 6 ++++++
opcodes/arm-dis.c | 10 ++++++++--
5 files changed, 35 insertions(+), 18 deletions(-)
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6076b89..ea6a87a 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-04-15 Renlin Li <renlin.li@arm.com>
+
+ * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
+ * gas/arm/thumb32.d: Likewise.
+
2015-04-14 Nick Clifton <nickc@redhat.com>
* gas/lns/lns.exp: Add RL78 to list of targets using
diff --git a/gas/testsuite/gas/arm/arch7em.d b/gas/testsuite/gas/arm/arch7em.d
index cd1f939..9e3e286 100644
--- a/gas/testsuite/gas/arm/arch7em.d
+++ b/gas/testsuite/gas/arm/arch7em.d
@@ -115,10 +115,10 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0
0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0
0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0
-0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #9, r0
-0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #0, r9
+0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #10, r0
+0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #1, r9
0[0-9a-f]+ <[^>]+> f3a0 0000 usat16 r0, #0, r0
0[0-9a-f]+ <[^>]+> f3a0 0900 usat16 r9, #0, r0
0[0-9a-f]+ <[^>]+> f3a0 0009 usat16 r0, #9, r0
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 9fd5f24..8e593a5 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -895,18 +895,18 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0
0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0
0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0
-0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0900 ssat r9, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0011 ssat r0, #17, r0
-0[0-9a-f]+ <[^>]+> f309 0000 ssat r0, #0, r9
-0[0-9a-f]+ <[^>]+> f300 7000 ssat r0, #0, r0, lsl #28
-0[0-9a-f]+ <[^>]+> f320 00c0 ssat r0, #0, r0, asr #3
-0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #9, r0
-0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #0, r9
+0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0900 ssat r9, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0011 ssat r0, #18, r0
+0[0-9a-f]+ <[^>]+> f309 0000 ssat r0, #1, r9
+0[0-9a-f]+ <[^>]+> f300 7000 ssat r0, #1, r0, lsl #28
+0[0-9a-f]+ <[^>]+> f320 00c0 ssat r0, #1, r0, asr #3
+0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #10, r0
+0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #1, r9
0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0
0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0
0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 832e843..ffec856 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2015-04-15 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
+ use it for ssat and ssat16.
+ (print_insn_thumb32): Add handle case for 'D' control code.
+
2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index c626bc9..1585a4f 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2471,6 +2471,7 @@ static const struct opcode16 thumb_opcodes[] =
%X print "\t; unpredictable <IT:code>" if conditional
%<bitfield>d print bitfield in decimal
+ %<bitfield>D print bitfield plus one in decimal
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
@@ -2731,7 +2732,7 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
+ 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -2839,7 +2840,7 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
+ 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -5679,6 +5680,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
value_in_comment = val;
break;
+ case 'D':
+ func (stream, "%lu", val + 1);
+ value_in_comment = val + 1;
+ break;
+
case 'W':
func (stream, "%lu", val * 4);
value_in_comment = val * 4;