src/opcodes ChangeLog cgen-dis.in cgen-ibld.in ...

[brolley at sourceware dot cygnus dot com]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	brolley@sourceware.cygnus.com	2000-08-28 11:17:54

Modified files:
	opcodes        : ChangeLog cgen-dis.in cgen-ibld.in fr30-asm.c 
	                 fr30-desc.c fr30-desc.h fr30-dis.c fr30-ibld.c 
	                 fr30-opc.c fr30-opc.h m32r-asm.c m32r-desc.c 
	                 m32r-desc.h m32r-dis.c m32r-ibld.c m32r-opc.c 

Log message:
	2000-08-28  Dave Brolley  <brolley@redhat.com>
	
	* cgen-ibld.in (cgen_put_insn_int_value): New function.
	(insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
	(insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P.
	(extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P.
	* cgen-dis.in (read_insn): New static function.
	(print_insn): Use read_insn to read the insn into the buffer and set
	up for disassembly.
	(print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is
	in the buffer.
	* fr30-asm.c: Regenerated.
	* fr30-desc.c: Regenerated.
	* fr30-desc.h Regenerated.
	* fr30-dis.c: Regenerated.
	* fr30-ibld.c: Regenerated.
	* fr30-opc.c: Regenerated.
	* fr30-opc.h Regenerated.
	* m32r-asm.c: Regenerated.
	* m32r-desc.c: Regenerated.
	* m32r-desc.h Regenerated.
	* m32r-dis.c: Regenerated.
	* m32r-ibld.c: Regenerated.
	* m32r-opc.c: Regenerated.

Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.171&r2=1.172
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/cgen-dis.in.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/cgen-ibld.in.diff?cvsroot=src&r1=1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/fr30-asm.c.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/fr30-desc.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/fr30-desc.h.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/fr30-dis.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/fr30-ibld.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/fr30-opc.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/fr30-opc.h.diff?cvsroot=src&r1=1.1.1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-asm.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-desc.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-desc.h.diff?cvsroot=src&r1=1.5&r2=1.6
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-dis.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-ibld.c.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/m32r-opc.c.diff?cvsroot=src&r1=1.3&r2=1.4