Current CGEN bugs

Future enhancements:
dummy ER

   associated with the first encountered/described ISA is used.  This
   causes problems when ISAs of different base instruction size are
   defined in the same cpu file. 

   The base instruction size of the ISA associated with the instruction
   in question should be used.
   
   File: cgen/mach.scm
   Routine: state_base_insn_bitsize + feeder routines

2. When rereading a little endian instruction with a base instruction

   size of 16 bits plus a 16 bit immediate, the byte ordering gets
   hosed.  The problem occurs due to the 32 bits being interpreted as
   one little endian int not two 16 bit, little endian shorts.    

   File: opcodes/cgen-dis.in
   Routine: print_insn()