(Category) (Category) CGEN Faq-O-Matic :
To-do items
Until a formal system like GNATS is required for tracking CGEN issues, please add Faq-O-Matic Answer objects for each item of interest.
Known problems:
(Answer) Current CGEN bugs

Future enhancements:
(Answer) dummy ER

[New Answer in "To-do items"]
(Answer) (Category) CGEN Faq-O-Matic : (Category) To-do items :
Current CGEN bugs
I have two bugs that need attention when we have a moment:
1. When multiple ISAs are defined, only the base instruction size
   associated with the first encountered/described ISA is used.  This
   causes problems when ISAs of different base instruction size are
   defined in the same cpu file. 
The base instruction size of the ISA associated with the instruction in question should be used. File: cgen/mach.scm Routine: state_base_insn_bitsize + feeder routines

2. When rereading a little endian instruction with a base instruction

   size of 16 bits plus a 16 bit immediate, the byte ordering gets
   hosed.  The problem occurs due to the 32 bits being interpreted as
   one little endian int not two 16 bit, little endian shorts.    
File: opcodes/cgen-dis.in Routine: print_insn()

[Append to This Answer]
(Answer) (Category) CGEN Faq-O-Matic : (Category) To-do items :
dummy ER
[Append to This Answer]
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