M32R Architecture Documentation
DISCLAIMER: This documentation is derived from the cgen cpu description
of this architecture, and does not represent official documentation
of the chip maker.
In cgen-parlance, an architecture consists of machines and models.
A `machine' is the specification of a variant of the architecture,
and a `model' is the implementation of that specification.
Typically there is a one-to-one correspondance between machine and model.
The distinction allows for separation of what application programs see
(the machine), and how to tune for the chip (what the compiler sees).
A "cpu family" is a cgen concoction to help organize the generated code.
Chip variants that are quite dissimilar can be treated separately by the
generated code even though they're both members of the same architecture.
M32R Architecture
This section describes various things about the cgen description of
the M32R architecture. Familiarity with cgen cpu descriptions
is assumed.
Bit number orientation (arch.lsb0?): msb = 0
ISA description
-
m32r -
- default-insn-word-bitsize: 32
- default-insn-bitsize: 32
- base-insn-bitsize: 32
- decode-assist: 0 1 2 3 8 9 10 11
- decode-splits:
- liw-insns: 2
- parallel-insns: 2
CPU Families
-
m32r2f - Renesas M32R2 family
Machines:
-
m32r2 - M32R2 cpu
Models:
-
m32rbf - Renesas M32R base family
Machines:
-
m32r - Generic M32R cpu
Models:
-
m32r/d - m32r/d
-
test - test
-
m32rxf - Renesas M32Rx family
Machines:
-
m32rx - M32RX cpu
Models:
Machine variants
m32r - Generic M32R cpu
-
bfd-name: m32r
-
isas: m32r
m32r2 - M32R2 cpu
-
bfd-name: m32r2
-
isas: m32r
m32rx - M32RX cpu
-
bfd-name: m32rx
-
isas: m32r
Model variants
m32r/d - m32r/d
m32r2 - m32r2
m32rx - m32rx
test - test
Registers
h-accum - accumulator
-
machines: base
-
bitsize: 64
h-accums - accumulators
-
machines: m32rx m32r2
-
bitsize: 64
-
array: [2]
names:
a0 |
0 |
a1 |
1 |
h-bbpsw - backup bpsw
-
machines: base
-
bitsize: 8
h-bpsw - backup psw
-
machines: base
-
bitsize: 8
h-cond - condition bit
-
machines: base
-
bitsize: 1
h-cr - control registers
-
machines: base
-
bitsize: 32
-
array: [16]
names:
psw |
0 |
cbr |
1 |
spi |
2 |
spu |
3 |
bpc |
6 |
bbpsw |
8 |
bbpc |
14 |
evb |
5 |
cr0 |
0 |
cr1 |
1 |
cr2 |
2 |
cr3 |
3 |
cr4 |
4 |
cr5 |
5 |
cr6 |
6 |
cr7 |
7 |
cr8 |
8 |
cr9 |
9 |
cr10 |
10 |
cr11 |
11 |
cr12 |
12 |
cr13 |
13 |
cr14 |
14 |
cr15 |
15 |
h-gr - general registers
-
machines: base
-
bitsize: 32
-
array: [16]
names:
fp |
13 |
lr |
14 |
sp |
15 |
r0 |
0 |
r1 |
1 |
r2 |
2 |
r3 |
3 |
r4 |
4 |
r5 |
5 |
r6 |
6 |
r7 |
7 |
r8 |
8 |
r9 |
9 |
r10 |
10 |
r11 |
11 |
r12 |
12 |
r13 |
13 |
r14 |
14 |
r15 |
15 |
h-lock - lock
-
machines: base
-
bitsize: 1
h-pc - program counter
-
machines: base
-
bitsize: 32
h-psw - psw part of psw
-
machines: base
-
bitsize: 8
Assembler supplemental
This documentation was machine generated from the cgen cpu description
files for this architecture.
http://sources.redhat.com/cgen/