Node:howto manager,
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Up:Relocations
The howto manager
When an application wants to create a relocation, but doesn't
know what the target machine might call it, it can find out by
using this bit of code.
bfd_reloc_code_type
Description
The insides of a reloc code. The idea is that, eventually, there
will be one enumerator for every type of relocation we ever do.
Pass one of these values to bfd_reloc_type_lookup
, and it'll
return a howto pointer.
This does mean that the application must determine the correct
enumerator value; you can't get a howto pointer from a random set
of attributes.
Here are the possible values for enum bfd_reloc_code_real
:
BFD_RELOC_64
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BFD_RELOC_32
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BFD_RELOC_26
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BFD_RELOC_24
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BFD_RELOC_16
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BFD_RELOC_14
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BFD_RELOC_8
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Basic absolute relocations of N bits.
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BFD_RELOC_64_PCREL
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BFD_RELOC_32_PCREL
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BFD_RELOC_24_PCREL
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BFD_RELOC_16_PCREL
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BFD_RELOC_12_PCREL
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BFD_RELOC_8_PCREL
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PC-relative relocations. Sometimes these are relative to the address
of the relocation itself; sometimes they are relative to the start of
the section containing the relocation. It depends on the specific target.
The 24-bit relocation is used in some Intel 960 configurations.
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BFD_RELOC_32_GOT_PCREL
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BFD_RELOC_16_GOT_PCREL
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BFD_RELOC_8_GOT_PCREL
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BFD_RELOC_32_GOTOFF
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BFD_RELOC_16_GOTOFF
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BFD_RELOC_LO16_GOTOFF
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BFD_RELOC_HI16_GOTOFF
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BFD_RELOC_HI16_S_GOTOFF
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BFD_RELOC_8_GOTOFF
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BFD_RELOC_64_PLT_PCREL
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BFD_RELOC_32_PLT_PCREL
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BFD_RELOC_24_PLT_PCREL
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BFD_RELOC_16_PLT_PCREL
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BFD_RELOC_8_PLT_PCREL
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BFD_RELOC_64_PLTOFF
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BFD_RELOC_32_PLTOFF
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BFD_RELOC_16_PLTOFF
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BFD_RELOC_LO16_PLTOFF
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BFD_RELOC_HI16_PLTOFF
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BFD_RELOC_HI16_S_PLTOFF
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BFD_RELOC_8_PLTOFF
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BFD_RELOC_68K_GLOB_DAT
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BFD_RELOC_68K_JMP_SLOT
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BFD_RELOC_68K_RELATIVE
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Relocations used by 68K ELF.
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BFD_RELOC_32_BASEREL
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BFD_RELOC_16_BASEREL
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BFD_RELOC_LO16_BASEREL
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BFD_RELOC_HI16_BASEREL
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BFD_RELOC_HI16_S_BASEREL
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BFD_RELOC_8_BASEREL
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BFD_RELOC_RVA
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Absolute 8-bit relocation, but used to form an address like 0xFFnn.
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BFD_RELOC_32_PCREL_S2
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BFD_RELOC_16_PCREL_S2
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BFD_RELOC_23_PCREL_S2
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These PC-relative relocations are stored as word displacements -
i.e., byte displacements shifted right two bits. The 30-bit word
displacement (<<32_PCREL_S2>> - 32 bits, shifted 2) is used on the
SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
signed 16-bit displacement is used on the MIPS, and the 23-bit
displacement is used on the Alpha.
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BFD_RELOC_HI22
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BFD_RELOC_LO10
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High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
the target word. These are used on the SPARC.
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BFD_RELOC_GPREL16
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BFD_RELOC_GPREL32
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For systems that allocate a Global Pointer register, these are
displacements off that register. These relocation types are
handled specially, because the value the register will have is
decided relatively late.
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Reloc types used for i960/b.out.
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BFD_RELOC_NONE
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BFD_RELOC_SPARC_WDISP22
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BFD_RELOC_SPARC22
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BFD_RELOC_SPARC13
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BFD_RELOC_SPARC_GOT10
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BFD_RELOC_SPARC_GOT13
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BFD_RELOC_SPARC_GOT22
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BFD_RELOC_SPARC_PC10
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BFD_RELOC_SPARC_PC22
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BFD_RELOC_SPARC_WPLT30
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BFD_RELOC_SPARC_COPY
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BFD_RELOC_SPARC_GLOB_DAT
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BFD_RELOC_SPARC_JMP_SLOT
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BFD_RELOC_SPARC_RELATIVE
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BFD_RELOC_SPARC_UA16
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BFD_RELOC_SPARC_UA32
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BFD_RELOC_SPARC_UA64
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SPARC ELF relocations. There is probably some overlap with other
relocation types already defined.
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BFD_RELOC_SPARC_BASE13
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BFD_RELOC_SPARC_BASE22
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I think these are specific to SPARC a.out (e.g., Sun 4).
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BFD_RELOC_SPARC_64
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BFD_RELOC_SPARC_10
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BFD_RELOC_SPARC_11
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BFD_RELOC_SPARC_OLO10
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BFD_RELOC_SPARC_HH22
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BFD_RELOC_SPARC_HM10
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BFD_RELOC_SPARC_LM22
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BFD_RELOC_SPARC_PC_HH22
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BFD_RELOC_SPARC_PC_HM10
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BFD_RELOC_SPARC_PC_LM22
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BFD_RELOC_SPARC_WDISP16
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BFD_RELOC_SPARC_WDISP19
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BFD_RELOC_SPARC_7
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BFD_RELOC_SPARC_6
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BFD_RELOC_SPARC_5
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BFD_RELOC_SPARC_DISP64
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BFD_RELOC_SPARC_PLT32
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BFD_RELOC_SPARC_PLT64
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BFD_RELOC_SPARC_HIX22
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BFD_RELOC_SPARC_LOX10
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BFD_RELOC_SPARC_H44
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BFD_RELOC_SPARC_M44
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BFD_RELOC_SPARC_L44
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BFD_RELOC_SPARC_REGISTER
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SPARC little endian relocation
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BFD_RELOC_ALPHA_GPDISP_HI16
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Alpha ECOFF and ELF relocations. Some of these treat the symbol or
"addend" in some special way.
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
writing; when reading, it will be the absolute section symbol. The
addend is the displacement in bytes of the "lda" instruction from
the "ldah" instruction (which is at the address of this reloc).
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BFD_RELOC_ALPHA_GPDISP_LO16
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For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
with GPDISP_HI16 relocs. The addend is ignored when writing the
relocations out, and is filled in with the file's GP value on
reading, for convenience.
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The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
relocation except that there is no accompanying GPDISP_LO16
relocation.
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BFD_RELOC_ALPHA_LITERAL
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BFD_RELOC_ALPHA_ELF_LITERAL
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BFD_RELOC_ALPHA_LITUSE
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The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
the assembler turns it into a LDQ instruction to load the address of
the symbol, and then fills in a register in the real instruction.
The LITERAL reloc, at the LDQ instruction, refers to the .lita
section symbol. The addend is ignored when writing, but is filled
in with the file's GP value on reading, for convenience, as with the
GPDISP_LO16 reloc.
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
It should refer to the symbol to be referenced, as with 16_GOTOFF,
but it generates output not based on the position within the .got
section, but relative to the GP value chosen for the file during the
final link stage.
The LITUSE reloc, on the instruction using the loaded address, gives
information to the linker that it might be able to use to optimize
away some literal section references. The symbol is ignored (read
as the absolute section symbol), and the "addend" indicates the type
of instruction using the register:
1 - "memory" fmt insn
2 - byte-manipulation (byte offset reg)
3 - jsr (target of branch)
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The HINT relocation indicates a value that should be filled into the
"hint" field of a jmp/jsr/ret instruction, for possible branch-
prediction logic which may be provided on some processors.
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The LINKAGE relocation outputs a linkage pair in the object file,
which is filled by the linker.
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The CODEADDR relocation outputs a STO_CA in the object file,
which is filled by the linker.
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BFD_RELOC_ALPHA_GPREL_HI16
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BFD_RELOC_ALPHA_GPREL_LO16
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The GPREL_HI/LO relocations together form a 32-bit offset from the
GP register.
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Like BFD_RELOC_23_PCREL_S2, except that the source and target must
share a common GP, and the target address is adjusted for
STO_ALPHA_STD_GPLOAD.
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Bits 27..2 of the relocation address shifted right 2 bits;
simple reloc otherwise.
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The MIPS16 jump instruction.
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MIPS16 GP relative reloc.
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High 16 bits of 32-bit value; simple reloc.
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High 16 bits of 32-bit value but the low 16 bits will be sign
extended and added to form the final result. If the low 16
bits form a negative number, we need to add one to the high value
to compensate for the borrow when the low bits are added.
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Like BFD_RELOC_HI16_S, but PC relative.
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Like BFD_RELOC_LO16, but PC relative.
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Relocation against a MIPS literal section.
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BFD_RELOC_MIPS_GOT16
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BFD_RELOC_MIPS_CALL16
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BFD_RELOC_MIPS_GOT_HI16
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BFD_RELOC_MIPS_GOT_LO16
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BFD_RELOC_MIPS_CALL_HI16
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BFD_RELOC_MIPS_CALL_LO16
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BFD_RELOC_MIPS_SUB
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BFD_RELOC_MIPS_GOT_PAGE
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BFD_RELOC_MIPS_GOT_OFST
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BFD_RELOC_MIPS_GOT_DISP
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BFD_RELOC_MIPS_SHIFT5
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BFD_RELOC_MIPS_SHIFT6
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BFD_RELOC_MIPS_INSERT_A
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BFD_RELOC_MIPS_INSERT_B
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BFD_RELOC_MIPS_DELETE
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BFD_RELOC_MIPS_HIGHEST
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BFD_RELOC_MIPS_HIGHER
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BFD_RELOC_MIPS_SCN_DISP
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BFD_RELOC_MIPS_REL16
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BFD_RELOC_MIPS_RELGOT
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BFD_RELOC_MIPS_JALR
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BFD_RELOC_SH_GOT_LOW16
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BFD_RELOC_SH_GOT_MEDLOW16
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BFD_RELOC_SH_GOT_MEDHI16
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BFD_RELOC_SH_GOT_HI16
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BFD_RELOC_SH_GOTPLT_LOW16
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BFD_RELOC_SH_GOTPLT_MEDLOW16
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BFD_RELOC_SH_GOTPLT_MEDHI16
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BFD_RELOC_SH_GOTPLT_HI16
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BFD_RELOC_SH_PLT_LOW16
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BFD_RELOC_SH_PLT_MEDLOW16
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BFD_RELOC_SH_PLT_MEDHI16
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BFD_RELOC_SH_PLT_HI16
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BFD_RELOC_SH_GOTOFF_LOW16
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BFD_RELOC_SH_GOTOFF_MEDLOW16
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BFD_RELOC_SH_GOTOFF_MEDHI16
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BFD_RELOC_SH_GOTOFF_HI16
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BFD_RELOC_SH_GOTPC_LOW16
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BFD_RELOC_SH_GOTPC_MEDLOW16
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BFD_RELOC_SH_GOTPC_MEDHI16
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BFD_RELOC_SH_GOTPC_HI16
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BFD_RELOC_SH_COPY64
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BFD_RELOC_SH_GLOB_DAT64
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BFD_RELOC_SH_JMP_SLOT64
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BFD_RELOC_SH_RELATIVE64
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BFD_RELOC_SH_GOT10BY4
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BFD_RELOC_SH_GOT10BY8
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BFD_RELOC_SH_GOTPLT10BY4
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BFD_RELOC_SH_GOTPLT10BY8
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BFD_RELOC_SH_GOTPLT32
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BFD_RELOC_SH_SHMEDIA_CODE
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BFD_RELOC_SH_IMMU5
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BFD_RELOC_SH_IMMS6
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BFD_RELOC_SH_IMMS6BY32
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BFD_RELOC_SH_IMMU6
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BFD_RELOC_SH_IMMS10
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BFD_RELOC_SH_IMMS10BY2
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BFD_RELOC_SH_IMMS10BY4
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BFD_RELOC_SH_IMMS10BY8
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BFD_RELOC_SH_IMMS16
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BFD_RELOC_SH_IMMU16
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BFD_RELOC_SH_IMM_LOW16
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BFD_RELOC_SH_IMM_LOW16_PCREL
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BFD_RELOC_SH_IMM_MEDLOW16
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BFD_RELOC_SH_IMM_MEDLOW16_PCREL
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BFD_RELOC_SH_IMM_MEDHI16
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BFD_RELOC_SH_IMM_MEDHI16_PCREL
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BFD_RELOC_SH_IMM_HI16
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BFD_RELOC_SH_IMM_HI16_PCREL
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BFD_RELOC_SH_PT_16
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BFD_RELOC_386_GOT32
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BFD_RELOC_386_PLT32
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BFD_RELOC_386_COPY
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BFD_RELOC_386_GLOB_DAT
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BFD_RELOC_386_JUMP_SLOT
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BFD_RELOC_386_RELATIVE
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BFD_RELOC_386_GOTOFF
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BFD_RELOC_386_GOTPC
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BFD_RELOC_X86_64_GOT32
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BFD_RELOC_X86_64_PLT32
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BFD_RELOC_X86_64_COPY
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BFD_RELOC_X86_64_GLOB_DAT
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BFD_RELOC_X86_64_JUMP_SLOT
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BFD_RELOC_X86_64_RELATIVE
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BFD_RELOC_X86_64_GOTPCREL
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BFD_RELOC_X86_64_32S
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BFD_RELOC_NS32K_IMM_8
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BFD_RELOC_NS32K_IMM_16
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BFD_RELOC_NS32K_IMM_32
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BFD_RELOC_NS32K_IMM_8_PCREL
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BFD_RELOC_NS32K_IMM_16_PCREL
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BFD_RELOC_NS32K_IMM_32_PCREL
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BFD_RELOC_NS32K_DISP_8
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BFD_RELOC_NS32K_DISP_16
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BFD_RELOC_NS32K_DISP_32
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BFD_RELOC_NS32K_DISP_8_PCREL
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BFD_RELOC_NS32K_DISP_16_PCREL
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BFD_RELOC_NS32K_DISP_32_PCREL
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BFD_RELOC_PDP11_DISP_8_PCREL
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BFD_RELOC_PDP11_DISP_6_PCREL
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BFD_RELOC_PJ_CODE_HI16
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BFD_RELOC_PJ_CODE_LO16
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BFD_RELOC_PJ_CODE_DIR16
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BFD_RELOC_PJ_CODE_DIR32
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BFD_RELOC_PJ_CODE_REL16
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BFD_RELOC_PJ_CODE_REL32
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Picojava relocs. Not all of these appear in object files.
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BFD_RELOC_PPC_B26
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BFD_RELOC_PPC_BA26
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BFD_RELOC_PPC_TOC16
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BFD_RELOC_PPC_B16
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BFD_RELOC_PPC_B16_BRTAKEN
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BFD_RELOC_PPC_B16_BRNTAKEN
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BFD_RELOC_PPC_BA16
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BFD_RELOC_PPC_BA16_BRTAKEN
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BFD_RELOC_PPC_BA16_BRNTAKEN
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BFD_RELOC_PPC_COPY
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BFD_RELOC_PPC_GLOB_DAT
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BFD_RELOC_PPC_JMP_SLOT
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BFD_RELOC_PPC_RELATIVE
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BFD_RELOC_PPC_LOCAL24PC
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BFD_RELOC_PPC_EMB_NADDR32
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BFD_RELOC_PPC_EMB_NADDR16
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BFD_RELOC_PPC_EMB_NADDR16_LO
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BFD_RELOC_PPC_EMB_NADDR16_HI
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BFD_RELOC_PPC_EMB_NADDR16_HA
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BFD_RELOC_PPC_EMB_SDAI16
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BFD_RELOC_PPC_EMB_SDA2I16
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BFD_RELOC_PPC_EMB_SDA2REL
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BFD_RELOC_PPC_EMB_SDA21
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BFD_RELOC_PPC_EMB_MRKREF
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BFD_RELOC_PPC_EMB_RELSEC16
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BFD_RELOC_PPC_EMB_RELST_LO
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BFD_RELOC_PPC_EMB_RELST_HI
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BFD_RELOC_PPC_EMB_RELST_HA
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BFD_RELOC_PPC_EMB_BIT_FLD
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BFD_RELOC_PPC_EMB_RELSDA
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BFD_RELOC_PPC64_HIGHER
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BFD_RELOC_PPC64_HIGHER_S
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BFD_RELOC_PPC64_HIGHEST
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BFD_RELOC_PPC64_HIGHEST_S
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BFD_RELOC_PPC64_TOC16_LO
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BFD_RELOC_PPC64_TOC16_HI
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BFD_RELOC_PPC64_TOC16_HA
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BFD_RELOC_PPC64_TOC
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BFD_RELOC_PPC64_PLTGOT16
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BFD_RELOC_PPC64_PLTGOT16_LO
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BFD_RELOC_PPC64_PLTGOT16_HI
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BFD_RELOC_PPC64_PLTGOT16_HA
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BFD_RELOC_PPC64_ADDR16_DS
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BFD_RELOC_PPC64_ADDR16_LO_DS
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BFD_RELOC_PPC64_GOT16_DS
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BFD_RELOC_PPC64_GOT16_LO_DS
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BFD_RELOC_PPC64_PLT16_LO_DS
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BFD_RELOC_PPC64_SECTOFF_DS
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BFD_RELOC_PPC64_SECTOFF_LO_DS
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BFD_RELOC_PPC64_TOC16_DS
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BFD_RELOC_PPC64_TOC16_LO_DS
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BFD_RELOC_PPC64_PLTGOT16_DS
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BFD_RELOC_PPC64_PLTGOT16_LO_DS
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Power(rs6000) and PowerPC relocations.
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The type of reloc used to build a contructor table - at the moment
probably a 32 bit wide absolute relocation, but the target can choose.
It generally does map to one of the other relocation types.
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BFD_RELOC_ARM_PCREL_BRANCH
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ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
not stored in the instruction.
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ARM 26 bit pc-relative branch. The lowest bit must be zero and is
not stored in the instruction. The 2nd lowest bit comes from a 1 bit
field in the instruction.
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BFD_RELOC_THUMB_PCREL_BLX
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Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
not stored in the instruction. The 2nd lowest bit comes from a 1 bit
field in the instruction.
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BFD_RELOC_ARM_IMMEDIATE
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BFD_RELOC_ARM_ADRL_IMMEDIATE
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BFD_RELOC_ARM_OFFSET_IMM
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BFD_RELOC_ARM_SHIFT_IMM
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BFD_RELOC_ARM_SWI
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BFD_RELOC_ARM_MULTI
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BFD_RELOC_ARM_CP_OFF_IMM
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BFD_RELOC_ARM_ADR_IMM
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BFD_RELOC_ARM_LDR_IMM
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BFD_RELOC_ARM_LITERAL
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BFD_RELOC_ARM_IN_POOL
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BFD_RELOC_ARM_OFFSET_IMM8
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BFD_RELOC_ARM_HWLITERAL
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BFD_RELOC_ARM_THUMB_ADD
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BFD_RELOC_ARM_THUMB_IMM
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BFD_RELOC_ARM_THUMB_SHIFT
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BFD_RELOC_ARM_THUMB_OFFSET
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BFD_RELOC_ARM_GOT12
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BFD_RELOC_ARM_GOT32
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BFD_RELOC_ARM_JUMP_SLOT
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BFD_RELOC_ARM_COPY
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BFD_RELOC_ARM_GLOB_DAT
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BFD_RELOC_ARM_PLT32
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BFD_RELOC_ARM_RELATIVE
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BFD_RELOC_ARM_GOTOFF
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BFD_RELOC_ARM_GOTPC
|
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These relocs are only used within the ARM assembler. They are not
(at present) written to any object files.
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BFD_RELOC_SH_PCDISP8BY2
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BFD_RELOC_SH_PCDISP12BY2
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BFD_RELOC_SH_IMM4
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BFD_RELOC_SH_IMM4BY2
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BFD_RELOC_SH_IMM4BY4
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BFD_RELOC_SH_IMM8
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BFD_RELOC_SH_IMM8BY2
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BFD_RELOC_SH_IMM8BY4
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BFD_RELOC_SH_PCRELIMM8BY2
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BFD_RELOC_SH_PCRELIMM8BY4
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BFD_RELOC_SH_SWITCH16
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BFD_RELOC_SH_SWITCH32
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BFD_RELOC_SH_USES
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BFD_RELOC_SH_COUNT
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BFD_RELOC_SH_ALIGN
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BFD_RELOC_SH_CODE
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BFD_RELOC_SH_DATA
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BFD_RELOC_SH_LABEL
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BFD_RELOC_SH_LOOP_START
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BFD_RELOC_SH_LOOP_END
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BFD_RELOC_SH_COPY
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BFD_RELOC_SH_GLOB_DAT
|
|
BFD_RELOC_SH_JMP_SLOT
|
|
BFD_RELOC_SH_RELATIVE
|
|
BFD_RELOC_SH_GOTPC
|
|
Hitachi SH relocs. Not all of these appear in object files.
|
BFD_RELOC_THUMB_PCREL_BRANCH9
|
|
BFD_RELOC_THUMB_PCREL_BRANCH12
|
|
BFD_RELOC_THUMB_PCREL_BRANCH23
|
|
Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must
be zero and is not stored in the instruction.
|
ARC Cores relocs.
ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
not stored in the instruction. The high 20 bits are installed in bits 26
through 7 of the instruction.
|
ARC 26 bit absolute branch. The lowest two bits must be zero and are not
stored in the instruction. The high 24 bits are installed in bits 23
through 0.
|
BFD_RELOC_D10V_10_PCREL_R
|
|
Mitsubishi D10V relocs.
This is a 10-bit reloc with the right 2 bits
assumed to be 0.
|
BFD_RELOC_D10V_10_PCREL_L
|
|
Mitsubishi D10V relocs.
This is a 10-bit reloc with the right 2 bits
assumed to be 0. This is the same as the previous reloc
except it is in the left container, i.e.,
shifted left 15 bits.
|
This is an 18-bit reloc with the right 2 bits
assumed to be 0.
|
This is an 18-bit reloc with the right 2 bits
assumed to be 0.
|
Mitsubishi D30V relocs.
This is a 6-bit absolute reloc.
|
This is a 6-bit pc-relative reloc with
the right 3 bits assumed to be 0.
|
This is a 6-bit pc-relative reloc with
the right 3 bits assumed to be 0. Same
as the previous reloc but on the right side
of the container.
|
This is a 12-bit absolute reloc with the
right 3 bitsassumed to be 0.
|
This is a 12-bit pc-relative reloc with
the right 3 bits assumed to be 0.
|
BFD_RELOC_D30V_15_PCREL_R
|
|
This is a 12-bit pc-relative reloc with
the right 3 bits assumed to be 0. Same
as the previous reloc but on the right side
of the container.
|
This is an 18-bit absolute reloc with
the right 3 bits assumed to be 0.
|
This is an 18-bit pc-relative reloc with
the right 3 bits assumed to be 0.
|
BFD_RELOC_D30V_21_PCREL_R
|
|
This is an 18-bit pc-relative reloc with
the right 3 bits assumed to be 0. Same
as the previous reloc but on the right side
of the container.
|
This is a 32-bit absolute reloc.
|
This is a 32-bit pc-relative reloc.
|
Mitsubishi M32R relocs.
This is a 24 bit absolute address.
|
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
|
This is an 18-bit reloc with the right 2 bits assumed to be 0.
|
This is a 26-bit reloc with the right 2 bits assumed to be 0.
|
This is a 16-bit reloc containing the high 16 bits of an address
used when the lower 16 bits are treated as unsigned.
|
This is a 16-bit reloc containing the high 16 bits of an address
used when the lower 16 bits are treated as signed.
|
This is a 16-bit reloc containing the lower 16 bits of an address.
|
This is a 16-bit reloc containing the small data area offset for use in
add3, load, and store instructions.
|
BFD_RELOC_V850_SDA_16_16_OFFSET
|
|
This is a 16 bit offset from the short data area pointer.
|
BFD_RELOC_V850_SDA_15_16_OFFSET
|
|
This is a 16 bit offset (of which only 15 bits are used) from the
short data area pointer.
|
BFD_RELOC_V850_ZDA_16_16_OFFSET
|
|
This is a 16 bit offset from the zero data area pointer.
|
BFD_RELOC_V850_ZDA_15_16_OFFSET
|
|
This is a 16 bit offset (of which only 15 bits are used) from the
zero data area pointer.
|
BFD_RELOC_V850_TDA_6_8_OFFSET
|
|
This is an 8 bit offset (of which only 6 bits are used) from the
tiny data area pointer.
|
BFD_RELOC_V850_TDA_7_8_OFFSET
|
|
This is an 8bit offset (of which only 7 bits are used) from the tiny
data area pointer.
|
BFD_RELOC_V850_TDA_7_7_OFFSET
|
|
This is a 7 bit offset from the tiny data area pointer.
|
BFD_RELOC_V850_TDA_16_16_OFFSET
|
|
This is a 16 bit offset from the tiny data area pointer.
|
BFD_RELOC_V850_TDA_4_5_OFFSET
|
|
This is a 5 bit offset (of which only 4 bits are used) from the tiny
data area pointer.
|
BFD_RELOC_V850_TDA_4_4_OFFSET
|
|
This is a 4 bit offset from the tiny data area pointer.
|
BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
|
|
This is a 16 bit offset from the short data area pointer, with the
bits placed non-contigously in the instruction.
|
BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
|
|
This is a 16 bit offset from the zero data area pointer, with the
bits placed non-contigously in the instruction.
|
BFD_RELOC_V850_CALLT_6_7_OFFSET
|
|
This is a 6 bit offset from the call table base pointer.
|
BFD_RELOC_V850_CALLT_16_16_OFFSET
|
|
This is a 16 bit offset from the call table base pointer.
|
BFD_RELOC_MN10300_32_PCREL
|
|
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
instruction.
|
BFD_RELOC_MN10300_16_PCREL
|
|
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
instruction.
|
This is a 8bit DP reloc for the tms320c30, where the most
significant 8 bits of a 24 bit word are placed into the least
significant 8 bits of the opcode.
|
This is a 7bit reloc for the tms320c54x, where the least
significant 7 bits of a 16 bit word are placed into the least
significant 7 bits of the opcode.
|
This is a 9bit DP reloc for the tms320c54x, where the most
significant 9 bits of a 16 bit word are placed into the least
significant 9 bits of the opcode.
|
This is an extended address 23-bit reloc for the tms320c54x.
|
BFD_RELOC_TIC54X_16_OF_23
|
|
This is a 16-bit reloc for the tms320c54x, where the least
significant 16 bits of a 23-bit extended address are placed into
the opcode.
|
BFD_RELOC_TIC54X_MS7_OF_23
|
|
This is a reloc for the tms320c54x, where the most
significant 7 bits of a 23-bit extended address are placed into
the opcode.
|
This is a 48 bit reloc for the FR30 that stores 32 bits.
|
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
two sections.
|
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4 bits.
|
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
into 8 bits.
|
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
into 8 bits.
|
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
into 8 bits.
|
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
short offset into 8 bits.
|
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
short offset into 11 bits.
|
BFD_RELOC_MCORE_PCREL_IMM8BY4
|
|
BFD_RELOC_MCORE_PCREL_IMM11BY2
|
|
BFD_RELOC_MCORE_PCREL_IMM4BY2
|
|
BFD_RELOC_MCORE_PCREL_32
|
|
BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
|
|
BFD_RELOC_MCORE_RVA
|
|
Motorola Mcore relocations.
|
BFD_RELOC_MMIX_GETA
|
|
BFD_RELOC_MMIX_GETA_1
|
|
BFD_RELOC_MMIX_GETA_2
|
|
BFD_RELOC_MMIX_GETA_3
|
|
These are relocations for the GETA instruction.
|
BFD_RELOC_MMIX_CBRANCH
|
|
BFD_RELOC_MMIX_CBRANCH_J
|
|
BFD_RELOC_MMIX_CBRANCH_1
|
|
BFD_RELOC_MMIX_CBRANCH_2
|
|
BFD_RELOC_MMIX_CBRANCH_3
|
|
These are relocations for a conditional branch instruction.
|
BFD_RELOC_MMIX_PUSHJ
|
|
BFD_RELOC_MMIX_PUSHJ_1
|
|
BFD_RELOC_MMIX_PUSHJ_2
|
|
BFD_RELOC_MMIX_PUSHJ_3
|
|
These are relocations for the PUSHJ instruction.
|
BFD_RELOC_MMIX_JMP
|
|
BFD_RELOC_MMIX_JMP_1
|
|
BFD_RELOC_MMIX_JMP_2
|
|
BFD_RELOC_MMIX_JMP_3
|
|
These are relocations for the JMP instruction.
|
This is a relocation for a relative address as in a GETA instruction or
a branch.
|
This is a relocation for a relative address as in a JMP instruction.
|
BFD_RELOC_MMIX_REG_OR_BYTE
|
|
This is a relocation for an instruction field that may be a general
register or a value 0..255.
|
This is a relocation for an instruction field that may be a general
register.
|
BFD_RELOC_MMIX_BASE_PLUS_OFFSET
|
|
This is a relocation for two instruction fields holding a register and
an offset, the equivalent of the relocation.
|
This relocation is an assertion that the expression is not allocated as
a global register. It does not modify contents.
|
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
short offset into 7 bits.
|
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
short offset into 12 bits.
|
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
program memory address) into 16 bits.
|
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
data memory address) into 8 bit immediate value of LDI insn.
|
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
of data memory address) into 8 bit immediate value of LDI insn.
|
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
of program memory address) into 8 bit immediate value of LDI insn.
|
BFD_RELOC_AVR_LO8_LDI_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(usually data memory address) into 8 bit immediate value of SUBI insn.
|
BFD_RELOC_AVR_HI8_LDI_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(high 8 bit of data memory address) into 8 bit immediate value of
SUBI insn.
|
BFD_RELOC_AVR_HH8_LDI_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(most high 8 bit of program memory address) into 8 bit immediate value
of LDI or SUBI insn.
|
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
command address) into 8 bit immediate value of LDI insn.
|
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
of command address) into 8 bit immediate value of LDI insn.
|
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
of command address) into 8 bit immediate value of LDI insn.
|
BFD_RELOC_AVR_LO8_LDI_PM_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(usually command address) into 8 bit immediate value of SUBI insn.
|
BFD_RELOC_AVR_HI8_LDI_PM_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(high 8 bit of 16 bit command address) into 8 bit immediate value
of SUBI insn.
|
BFD_RELOC_AVR_HH8_LDI_PM_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
(high 6 bit of 22 bit command address) into 8 bit immediate
value of SUBI insn.
|
This is a 32 bit reloc for the AVR that stores 23 bit value
into 22 bits.
|
32 bit PC relative PLT address.
|
32 bit PC relative offset to GOT.
|
PC relative 16 bit shifted by 1.
|
16 bit PC rel. PLT shifted by 1.
|
PC relative 32 bit shifted by 1.
|
32 bit PC rel. PLT shifted by 1.
|
32 bit PC rel. GOT shifted by 1.
|
64 bit PC relative PLT address.
|
32 bit rel. offset to GOT entry.
|
BFD_RELOC_VTABLE_INHERIT
|
|
BFD_RELOC_VTABLE_ENTRY
|
|
These two relocations are used by the linker to determine which of
the entries in a C++ virtual function table are actually used. When
the -gc-sections option is given, the linker will zero out the entries
that are not used, so that the code for those functions need not be
included in the output.
VTABLE_INHERIT is a zero-space relocation used to describe to the
linker the inheritence tree of a C++ virtual function table. The
relocation's symbol should be the parent class' vtable, and the
relocation should be located at the child vtable.
VTABLE_ENTRY is a zero-space relocation that describes the use of a
virtual function table entry. The reloc's symbol should refer to the
table of the class mentioned in the code. Off of that base, an offset
describes the entry that is being used. For Rela hosts, this offset
is stored in the reloc's addend. For Rel hosts, we are forced to put
this offset in the reloc's section offset.
|
BFD_RELOC_IA64_IMM14
|
|
BFD_RELOC_IA64_IMM22
|
|
BFD_RELOC_IA64_IMM64
|
|
BFD_RELOC_IA64_DIR32MSB
|
|
BFD_RELOC_IA64_DIR32LSB
|
|
BFD_RELOC_IA64_DIR64MSB
|
|
BFD_RELOC_IA64_DIR64LSB
|
|
BFD_RELOC_IA64_GPREL22
|
|
BFD_RELOC_IA64_GPREL64I
|
|
BFD_RELOC_IA64_GPREL32MSB
|
|
BFD_RELOC_IA64_GPREL32LSB
|
|
BFD_RELOC_IA64_GPREL64MSB
|
|
BFD_RELOC_IA64_GPREL64LSB
|
|
BFD_RELOC_IA64_LTOFF22
|
|
BFD_RELOC_IA64_LTOFF64I
|
|
BFD_RELOC_IA64_PLTOFF22
|
|
BFD_RELOC_IA64_PLTOFF64I
|
|
BFD_RELOC_IA64_PLTOFF64MSB
|
|
BFD_RELOC_IA64_PLTOFF64LSB
|
|
BFD_RELOC_IA64_FPTR64I
|
|
BFD_RELOC_IA64_FPTR32MSB
|
|
BFD_RELOC_IA64_FPTR32LSB
|
|
BFD_RELOC_IA64_FPTR64MSB
|
|
BFD_RELOC_IA64_FPTR64LSB
|
|
BFD_RELOC_IA64_PCREL21B
|
|
BFD_RELOC_IA64_PCREL21BI
|
|
BFD_RELOC_IA64_PCREL21M
|
|
BFD_RELOC_IA64_PCREL21F
|
|
BFD_RELOC_IA64_PCREL22
|
|
BFD_RELOC_IA64_PCREL60B
|
|
BFD_RELOC_IA64_PCREL64I
|
|
BFD_RELOC_IA64_PCREL32MSB
|
|
BFD_RELOC_IA64_PCREL32LSB
|
|
BFD_RELOC_IA64_PCREL64MSB
|
|
BFD_RELOC_IA64_PCREL64LSB
|
|
BFD_RELOC_IA64_LTOFF_FPTR22
|
|
BFD_RELOC_IA64_LTOFF_FPTR64I
|
|
BFD_RELOC_IA64_LTOFF_FPTR32MSB
|
|
BFD_RELOC_IA64_LTOFF_FPTR32LSB
|
|
BFD_RELOC_IA64_LTOFF_FPTR64MSB
|
|
BFD_RELOC_IA64_LTOFF_FPTR64LSB
|
|
BFD_RELOC_IA64_SEGREL32MSB
|
|
BFD_RELOC_IA64_SEGREL32LSB
|
|
BFD_RELOC_IA64_SEGREL64MSB
|
|
BFD_RELOC_IA64_SEGREL64LSB
|
|
BFD_RELOC_IA64_SECREL32MSB
|
|
BFD_RELOC_IA64_SECREL32LSB
|
|
BFD_RELOC_IA64_SECREL64MSB
|
|
BFD_RELOC_IA64_SECREL64LSB
|
|
BFD_RELOC_IA64_REL32MSB
|
|
BFD_RELOC_IA64_REL32LSB
|
|
BFD_RELOC_IA64_REL64MSB
|
|
BFD_RELOC_IA64_REL64LSB
|
|
BFD_RELOC_IA64_LTV32MSB
|
|
BFD_RELOC_IA64_LTV32LSB
|
|
BFD_RELOC_IA64_LTV64MSB
|
|
BFD_RELOC_IA64_LTV64LSB
|
|
BFD_RELOC_IA64_IPLTMSB
|
|
BFD_RELOC_IA64_IPLTLSB
|
|
BFD_RELOC_IA64_COPY
|
|
BFD_RELOC_IA64_TPREL22
|
|
BFD_RELOC_IA64_TPREL64MSB
|
|
BFD_RELOC_IA64_TPREL64LSB
|
|
BFD_RELOC_IA64_LTOFF_TP22
|
|
BFD_RELOC_IA64_LTOFF22X
|
|
BFD_RELOC_IA64_LDXMOV
|
|
Motorola 68HC11 reloc.
This is the 8 bits high part of an absolute address.
|
Motorola 68HC11 reloc.
This is the 8 bits low part of an absolute address.
|
Motorola 68HC11 reloc.
This is the 3 bits of a value.
|
BFD_RELOC_CRIS_BDISP8
|
|
BFD_RELOC_CRIS_UNSIGNED_5
|
|
BFD_RELOC_CRIS_SIGNED_6
|
|
BFD_RELOC_CRIS_UNSIGNED_6
|
|
BFD_RELOC_CRIS_UNSIGNED_4
|
|
These relocs are only used within the CRIS assembler. They are not
(at present) written to any object files.
|
BFD_RELOC_CRIS_COPY
|
|
BFD_RELOC_CRIS_GLOB_DAT
|
|
BFD_RELOC_CRIS_JUMP_SLOT
|
|
BFD_RELOC_CRIS_RELATIVE
|
|
Relocs used in ELF shared libraries for CRIS.
|
32-bit offset to symbol-entry within GOT.
|
16-bit offset to symbol-entry within GOT.
|
32-bit offset to symbol-entry within GOT, with PLT handling.
|
16-bit offset to symbol-entry within GOT, with PLT handling.
|
32-bit offset to symbol, relative to GOT.
|
BFD_RELOC_CRIS_32_PLT_GOTREL
|
|
32-bit offset to symbol with PLT entry, relative to GOT.
|
BFD_RELOC_CRIS_32_PLT_PCREL
|
|
32-bit offset to symbol with PLT entry, relative to this relocation.
|
BFD_RELOC_860_COPY
|
|
BFD_RELOC_860_GLOB_DAT
|
|
BFD_RELOC_860_JUMP_SLOT
|
|
BFD_RELOC_860_RELATIVE
|
|
BFD_RELOC_860_PC26
|
|
BFD_RELOC_860_PLT26
|
|
BFD_RELOC_860_PC16
|
|
BFD_RELOC_860_LOW0
|
|
BFD_RELOC_860_SPLIT0
|
|
BFD_RELOC_860_LOW1
|
|
BFD_RELOC_860_SPLIT1
|
|
BFD_RELOC_860_LOW2
|
|
BFD_RELOC_860_SPLIT2
|
|
BFD_RELOC_860_LOW3
|
|
BFD_RELOC_860_LOGOT0
|
|
BFD_RELOC_860_SPGOT0
|
|
BFD_RELOC_860_LOGOT1
|
|
BFD_RELOC_860_SPGOT1
|
|
BFD_RELOC_860_LOGOTOFF0
|
|
BFD_RELOC_860_SPGOTOFF0
|
|
BFD_RELOC_860_LOGOTOFF1
|
|
BFD_RELOC_860_SPGOTOFF1
|
|
BFD_RELOC_860_LOGOTOFF2
|
|
BFD_RELOC_860_LOGOTOFF3
|
|
BFD_RELOC_860_LOPC
|
|
BFD_RELOC_860_HIGHADJ
|
|
BFD_RELOC_860_HAGOT
|
|
BFD_RELOC_860_HAGOTOFF
|
|
BFD_RELOC_860_HAPC
|
|
BFD_RELOC_860_HIGH
|
|
BFD_RELOC_860_HIGOT
|
|
BFD_RELOC_860_HIGOTOFF
|
|
BFD_RELOC_OPENRISC_ABS_26
|
|
BFD_RELOC_OPENRISC_REL_26
|
|
BFD_RELOC_H8_DIR16A8
|
|
BFD_RELOC_H8_DIR16R8
|
|
BFD_RELOC_H8_DIR24A8
|
|
BFD_RELOC_H8_DIR24R8
|
|
BFD_RELOC_H8_DIR32A16
|
|
BFD_RELOC_XSTORMY16_REL_12
|
|
BFD_RELOC_XSTORMY16_24
|
|
BFD_RELOC_XSTORMY16_FPTR16
|
|
Sony Xstormy16 Relocations.
|
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
bfd_reloc_type_lookup
Synopsis
reloc_howto_type *
bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code);
Description
Return a pointer to a howto structure which, when
invoked, will perform the relocation code on data from the
architecture noted.
bfd_default_reloc_type_lookup
Synopsis
reloc_howto_type *bfd_default_reloc_type_lookup
(bfd *abfd, bfd_reloc_code_real_type code);
Description
Provides a default relocation lookup routine for any architecture.
bfd_get_reloc_code_name
Synopsis
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
Description
Provides a printable name for the supplied relocation code.
Useful mainly for printing error messages.
bfd_generic_relax_section
Synopsis
boolean bfd_generic_relax_section
(bfd *abfd,
asection *section,
struct bfd_link_info *,
boolean *);
Description
Provides default handling for relaxing for back ends which
don't do relaxing - i.e., does nothing.
bfd_generic_gc_sections
Synopsis
boolean bfd_generic_gc_sections
(bfd *, struct bfd_link_info *);
Description
Provides default handling for relaxing for back ends which
don't do section gc - i.e., does nothing.
bfd_generic_merge_sections
Synopsis
boolean bfd_generic_merge_sections
(bfd *, struct bfd_link_info *);
Description
Provides default handling for SEC_MERGE section merging for back ends
which don't have SEC_MERGE support - i.e., does nothing.
bfd_generic_get_relocated_section_contents
Synopsis
bfd_byte *
bfd_generic_get_relocated_section_contents (bfd *abfd,
struct bfd_link_info *link_info,
struct bfd_link_order *link_order,
bfd_byte *data,
boolean relocateable,
asymbol **symbols);
Description
Provides default handling of relocation effort for back ends
which can't be bothered to do it efficiently.